KR102719982B1 - 3차원 nor 메모리 어레이 아키텍처 및 그의 제조 방법 - Google Patents

3차원 nor 메모리 어레이 아키텍처 및 그의 제조 방법 Download PDF

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KR102719982B1
KR102719982B1 KR1020207000747A KR20207000747A KR102719982B1 KR 102719982 B1 KR102719982 B1 KR 102719982B1 KR 1020207000747 A KR1020207000747 A KR 1020207000747A KR 20207000747 A KR20207000747 A KR 20207000747A KR 102719982 B1 KR102719982 B1 KR 102719982B1
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layer
memory structure
stack
active strips
active
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KR20200015743A (ko
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일리 하라리
스콧 브래드 헤르너
우-이 치엔
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선라이즈 메모리 코포레이션
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H01L21/31111—
    • H01L21/76802—
    • H01L21/7682—
    • H01L23/562—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/072—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/46—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means

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  • Semiconductor Memories (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Non-Volatile Memory (AREA)
KR1020207000747A 2017-06-20 2018-06-19 3차원 nor 메모리 어레이 아키텍처 및 그의 제조 방법 Active KR102719982B1 (ko)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US201762522665P 2017-06-20 2017-06-20
US201762522666P 2017-06-20 2017-06-20
US201762522661P 2017-06-20 2017-06-20
US62/522,665 2017-06-20
US62/522,666 2017-06-20
US62/522,661 2017-06-20
US201762550553P 2017-08-25 2017-08-25
US62/550,553 2017-08-25
PCT/US2018/038373 WO2018236937A1 (en) 2017-06-20 2018-06-19 NON-THREE DIMENSIONAL MEMORY MATRIX ARCHITECTURE AND METHODS OF MAKING THE SAME

Publications (2)

Publication Number Publication Date
KR20200015743A KR20200015743A (ko) 2020-02-12
KR102719982B1 true KR102719982B1 (ko) 2024-10-22

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Country Status (6)

Country Link
US (4) US10608011B2 (https=)
EP (1) EP3642841A4 (https=)
JP (1) JP7203054B2 (https=)
KR (1) KR102719982B1 (https=)
CN (1) CN111033625B (https=)
WO (1) WO2018236937A1 (https=)

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