JP6587792B2 - 埋め込み型半導体デバイスパッケージおよびその製造方法 - Google Patents
埋め込み型半導体デバイスパッケージおよびその製造方法 Download PDFInfo
- Publication number
- JP6587792B2 JP6587792B2 JP2014192072A JP2014192072A JP6587792B2 JP 6587792 B2 JP6587792 B2 JP 6587792B2 JP 2014192072 A JP2014192072 A JP 2014192072A JP 2014192072 A JP2014192072 A JP 2014192072A JP 6587792 B2 JP6587792 B2 JP 6587792B2
- Authority
- JP
- Japan
- Prior art keywords
- dielectric
- semiconductor device
- package structure
- dielectric layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2401—Structure
- H01L2224/2402—Laminated, e.g. MCM-L type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
- H01L2224/2731—Manufacturing methods by local deposition of the material of the layer connector in liquid form
- H01L2224/2732—Screen printing, i.e. using a stencil
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
- H01L2224/2741—Manufacturing methods by blanket deposition of the material of the layer connector in liquid form
- H01L2224/27416—Spin coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82009—Pre-treatment of the connector or the bonding area
- H01L2224/8201—Cleaning, e.g. oxide removal step, desmearing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82009—Pre-treatment of the connector or the bonding area
- H01L2224/8203—Reshaping, e.g. forming vias
- H01L2224/82031—Reshaping, e.g. forming vias by chemical means, e.g. etching, anodisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82009—Pre-treatment of the connector or the bonding area
- H01L2224/8203—Reshaping, e.g. forming vias
- H01L2224/82035—Reshaping, e.g. forming vias by heating means
- H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82009—Pre-treatment of the connector or the bonding area
- H01L2224/8203—Reshaping, e.g. forming vias
- H01L2224/82047—Reshaping, e.g. forming vias by mechanical means, e.g. severing, pressing, stamping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/821—Forming a build-up interconnect
- H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
- H01L2224/83132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1433—Application-specific integrated circuit [ASIC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
- H01L2924/15747—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0187—Dielectric layers with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0278—Flat pressure, e.g. for connecting terminals with anisotropic conductive adhesive
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/063—Lamination of preperforated insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/16—Inspection; Monitoring; Aligning
- H05K2203/166—Alignment or registration; Control of registration
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
- H05K3/305—Affixing by adhesive
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
- H05K3/4605—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated made from inorganic insulating material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Manufacturing & Machinery (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/037,728 US9209151B2 (en) | 2013-09-26 | 2013-09-26 | Embedded semiconductor device package and method of manufacturing thereof |
| US14/037,728 | 2013-09-26 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2015070269A JP2015070269A (ja) | 2015-04-13 |
| JP2015070269A5 JP2015070269A5 (enExample) | 2017-10-19 |
| JP6587792B2 true JP6587792B2 (ja) | 2019-10-09 |
Family
ID=51539201
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014192072A Active JP6587792B2 (ja) | 2013-09-26 | 2014-09-22 | 埋め込み型半導体デバイスパッケージおよびその製造方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US9209151B2 (enExample) |
| EP (1) | EP2854168A3 (enExample) |
| JP (1) | JP6587792B2 (enExample) |
| KR (1) | KR102295990B1 (enExample) |
| CN (1) | CN104681520A (enExample) |
| TW (2) | TWI634632B (enExample) |
Families Citing this family (82)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103857210A (zh) * | 2012-11-28 | 2014-06-11 | 宏启胜精密电子(秦皇岛)有限公司 | 承载电路板、承载电路板的制作方法及封装结构 |
| TWI474450B (zh) * | 2013-09-27 | 2015-02-21 | 旭德科技股份有限公司 | 封裝載板及其製作方法 |
| US9704781B2 (en) | 2013-11-19 | 2017-07-11 | Micron Technology, Inc. | Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods |
| KR102042137B1 (ko) * | 2014-05-30 | 2019-11-28 | 한국전자통신연구원 | 전자장치 및 그 제조 방법 |
| JP2015228455A (ja) * | 2014-06-02 | 2015-12-17 | 株式会社東芝 | 半導体装置及びその製造方法 |
| US20150366081A1 (en) * | 2014-06-15 | 2015-12-17 | Unimicron Technology Corp. | Manufacturing method for circuit structure embedded with electronic device |
| US10297572B2 (en) * | 2014-10-06 | 2019-05-21 | Mc10, Inc. | Discrete flexible interconnects for modules of integrated circuits |
| CN207166882U (zh) * | 2014-10-16 | 2018-03-30 | 株式会社村田制作所 | 复合器件 |
| JP6048481B2 (ja) * | 2014-11-27 | 2016-12-21 | 株式会社豊田自動織機 | 電子機器 |
| KR20160084143A (ko) * | 2015-01-05 | 2016-07-13 | 삼성전기주식회사 | 전자소자 내장기판 및 그 제조 방법 |
| JP6430883B2 (ja) * | 2015-04-10 | 2018-11-28 | 株式会社ジェイデバイス | 半導体パッケージ及びその製造方法 |
| US9806058B2 (en) * | 2015-07-02 | 2017-10-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip package having die structures of different heights and method of forming same |
| US10535633B2 (en) | 2015-07-02 | 2020-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip package having die structures of different heights and method of forming same |
| KR101923659B1 (ko) * | 2015-08-31 | 2019-02-22 | 삼성전자주식회사 | 반도체 패키지 구조체, 및 그 제조 방법 |
| WO2017039275A1 (ko) | 2015-08-31 | 2017-03-09 | 한양대학교 산학협력단 | 반도체 패키지 구조체, 및 그 제조 방법 |
| JP6862087B2 (ja) * | 2015-12-11 | 2021-04-21 | 株式会社アムコー・テクノロジー・ジャパン | 配線基板、配線基板を有する半導体パッケージ、およびその製造方法 |
| EP3443584B1 (en) * | 2016-04-11 | 2021-11-03 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Batch manufacturing of component carriers and their related semi-finished product |
| US10660208B2 (en) * | 2016-07-13 | 2020-05-19 | General Electric Company | Embedded dry film battery module and method of manufacturing thereof |
| CN107872925A (zh) | 2016-09-27 | 2018-04-03 | 奥特斯奥地利科技与系统技术有限公司 | 将部件嵌入导电箔上的芯中 |
| SG10201608773PA (en) * | 2016-10-19 | 2018-05-30 | Delta Electronics Intl Singapore Pte Ltd | Method Of Packaging Semiconductor Device |
| US9966361B1 (en) | 2016-11-04 | 2018-05-08 | General Electric Company | Electronics package having a multi-thickness conductor layer and method of manufacturing thereof |
| US9966371B1 (en) | 2016-11-04 | 2018-05-08 | General Electric Company | Electronics package having a multi-thickness conductor layer and method of manufacturing thereof |
| US20180130732A1 (en) * | 2016-11-04 | 2018-05-10 | General Electric Company | Electronics package having a multi-thickness conductor layer and method of manufacturing thereof |
| US10700035B2 (en) | 2016-11-04 | 2020-06-30 | General Electric Company | Stacked electronics package and method of manufacturing thereof |
| US10312194B2 (en) | 2016-11-04 | 2019-06-04 | General Electric Company | Stacked electronics package and method of manufacturing thereof |
| US9953917B1 (en) * | 2016-12-12 | 2018-04-24 | General Electric Company | Electronics package with embedded through-connect and resistor structure and method of manufacturing thereof |
| US9953913B1 (en) | 2016-12-12 | 2018-04-24 | General Electric Company | Electronics package with embedded through-connect structure and method of manufacturing thereof |
| CN106601701B (zh) * | 2017-01-19 | 2023-03-28 | 贵州煜立电子科技有限公司 | 大功率二端表面引出脚电子元器件立体封装方法及结构 |
| CN110235243B (zh) * | 2017-01-30 | 2023-07-18 | 三菱电机株式会社 | 功率半导体装置的制造方法及功率半导体装置 |
| JP6809294B2 (ja) * | 2017-03-02 | 2021-01-06 | 三菱電機株式会社 | パワーモジュール |
| EP3606758A4 (en) * | 2017-04-03 | 2021-01-20 | Creative IC3D Ltd | PROCESS FOR MANUFACTURING THREE-DIMENSIONAL STRUCTURES |
| US10541209B2 (en) | 2017-08-03 | 2020-01-21 | General Electric Company | Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof |
| US10804115B2 (en) | 2017-08-03 | 2020-10-13 | General Electric Company | Electronics package with integrated interconnect structure and method of manufacturing thereof |
| US10541153B2 (en) | 2017-08-03 | 2020-01-21 | General Electric Company | Electronics package with integrated interconnect structure and method of manufacturing thereof |
| US10910290B2 (en) * | 2017-10-19 | 2021-02-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structures and methods for heat dissipation of semiconductor devices |
| US10643919B2 (en) * | 2017-11-08 | 2020-05-05 | Samsung Electronics Co., Ltd. | Fan-out semiconductor package |
| WO2019117967A1 (en) | 2017-12-15 | 2019-06-20 | Hewlett-Packard Development Company, L.P. | Three-dimensional printing |
| CN111788676B (zh) * | 2018-03-07 | 2024-12-10 | 三菱电机株式会社 | 半导体装置以及电力变换装置 |
| US10497648B2 (en) | 2018-04-03 | 2019-12-03 | General Electric Company | Embedded electronics package with multi-thickness interconnect structure and method of making same |
| KR102164795B1 (ko) * | 2018-09-06 | 2020-10-13 | 삼성전자주식회사 | 팬-아웃 반도체 패키지 |
| US11296001B2 (en) * | 2018-10-19 | 2022-04-05 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
| JP6573415B1 (ja) * | 2018-11-15 | 2019-09-11 | 有限会社アイピーシステムズ | ビア配線形成用基板及びビア配線形成用基板の製造方法並びに半導体装置実装部品の製造方法 |
| US20200161206A1 (en) * | 2018-11-20 | 2020-05-21 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and semiconductor manufacturing process |
| CN109727969A (zh) * | 2018-12-29 | 2019-05-07 | 华进半导体封装先导技术研发中心有限公司 | 一种基板埋入式功率器件封装结构及其制造方法 |
| US11342256B2 (en) | 2019-01-24 | 2022-05-24 | Applied Materials, Inc. | Method of fine redistribution interconnect formation for advanced packaging applications |
| EP3716326A1 (en) * | 2019-03-25 | 2020-09-30 | Mitsubishi Electric R&D Centre Europe B.V. | Electrically power assembly with thick electrically conductive layers |
| US12245377B2 (en) | 2019-03-29 | 2025-03-04 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Component carrier with embedded semiconductor component and embedded highly-conductive block which are mutually coupled |
| EP3716321B1 (en) * | 2019-03-29 | 2025-01-29 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Component carrier with embedded semiconductor component and embedded highly conductive block which are mutually coupled |
| IT201900006736A1 (it) * | 2019-05-10 | 2020-11-10 | Applied Materials Inc | Procedimenti di fabbricazione di package |
| IT201900006740A1 (it) | 2019-05-10 | 2020-11-10 | Applied Materials Inc | Procedimenti di strutturazione di substrati |
| CN110600440B (zh) * | 2019-05-13 | 2021-12-14 | 华为技术有限公司 | 一种埋入式封装结构及其制备方法、终端 |
| US11931855B2 (en) | 2019-06-17 | 2024-03-19 | Applied Materials, Inc. | Planarization methods for packaging substrates |
| KR102574409B1 (ko) * | 2019-07-01 | 2023-09-04 | 삼성전기주식회사 | 반도체 패키지 |
| CN112447777A (zh) * | 2019-08-30 | 2021-03-05 | 旭景科技股份有限公司 | 集成电路封装结构及其形成方法 |
| US11632860B2 (en) | 2019-10-25 | 2023-04-18 | Infineon Technologies Ag | Power electronic assembly and method of producing thereof |
| EP3836208A1 (en) * | 2019-11-19 | 2021-06-16 | Mitsubishi Electric R & D Centre Europe B.V. | Method and system for interconnecting a power device embedded in a substrate using conducting paste into cavities |
| US11862546B2 (en) | 2019-11-27 | 2024-01-02 | Applied Materials, Inc. | Package core assembly and fabrication methods |
| CN111564414B (zh) * | 2019-12-12 | 2021-09-24 | 奥特斯(中国)有限公司 | 部件承载件及制造部件承载件的方法 |
| WO2021156958A1 (ja) * | 2020-02-05 | 2021-08-12 | 太陽誘電株式会社 | 半導体モジュールおよび電源モジュール |
| EP3869923B1 (en) | 2020-02-20 | 2025-01-08 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Cooling profile integration for embedded power systems |
| US11257790B2 (en) * | 2020-03-10 | 2022-02-22 | Applied Materials, Inc. | High connectivity device stacking |
| US11454884B2 (en) | 2020-04-15 | 2022-09-27 | Applied Materials, Inc. | Fluoropolymer stamp fabrication method |
| US11400545B2 (en) | 2020-05-11 | 2022-08-02 | Applied Materials, Inc. | Laser ablation for package fabrication |
| US11398445B2 (en) | 2020-05-29 | 2022-07-26 | General Electric Company | Mechanical punched via formation in electronics package and electronics package formed thereby |
| TWI753468B (zh) * | 2020-06-24 | 2022-01-21 | 欣興電子股份有限公司 | 具散熱結構之基板結構及其製造方法 |
| US11342248B2 (en) * | 2020-07-14 | 2022-05-24 | Gan Systems Inc. | Embedded die packaging for power semiconductor devices |
| US11232951B1 (en) | 2020-07-14 | 2022-01-25 | Applied Materials, Inc. | Method and apparatus for laser drilling blind vias |
| US11676832B2 (en) | 2020-07-24 | 2023-06-13 | Applied Materials, Inc. | Laser ablation system for package fabrication |
| CN120897497A (zh) * | 2020-10-24 | 2025-11-04 | Pep创新私人有限公司 | 一种芯片封装、芯片结构及其制造方法 |
| US11521937B2 (en) | 2020-11-16 | 2022-12-06 | Applied Materials, Inc. | Package structures with built-in EMI shielding |
| US11404318B2 (en) | 2020-11-20 | 2022-08-02 | Applied Materials, Inc. | Methods of forming through-silicon vias in substrates for advanced packaging |
| TWI766540B (zh) * | 2021-01-13 | 2022-06-01 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
| JP7168828B2 (ja) * | 2021-03-31 | 2022-11-10 | 株式会社Flosfia | 半導体装置および半導体システム |
| US11705365B2 (en) | 2021-05-18 | 2023-07-18 | Applied Materials, Inc. | Methods of micro-via formation for advanced packaging |
| US11950394B2 (en) | 2021-10-12 | 2024-04-02 | Ge Aviation Systems Llc | Liquid-cooled assembly and method |
| US12183684B2 (en) | 2021-10-26 | 2024-12-31 | Applied Materials, Inc. | Semiconductor device packaging methods |
| WO2023175675A1 (ja) | 2022-03-14 | 2023-09-21 | 三菱電機株式会社 | パワーモジュール半導体パッケージおよび半導体装置 |
| US20230378042A1 (en) * | 2022-05-23 | 2023-11-23 | Taiwan Semiconductor Manufacturing Company Limited | Reinforced substrates to mitigate underflow stress and package warp and methods of making the same |
| TWI844243B (zh) * | 2023-01-18 | 2024-06-01 | 宏碁股份有限公司 | 電子封裝結構 |
| US20240321674A1 (en) * | 2023-03-23 | 2024-09-26 | Mediatek Inc. | Semiconductor device |
| CN118173455A (zh) * | 2024-02-20 | 2024-06-11 | 深南电路股份有限公司 | 一种功率芯片埋入式的封装基板及封装方法 |
| CN119993913A (zh) * | 2025-04-15 | 2025-05-13 | 江苏长晶科技股份有限公司 | 芯片封装方法、芯片结构及电子设备 |
Family Cites Families (32)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5353498A (en) | 1993-02-08 | 1994-10-11 | General Electric Company | Method for fabricating an integrated circuit module |
| US6306680B1 (en) | 1999-02-22 | 2001-10-23 | General Electric Company | Power overlay chip scale packages for discrete power devices |
| US6232151B1 (en) | 1999-11-01 | 2001-05-15 | General Electric Company | Power electronic module packaging |
| JP3815239B2 (ja) * | 2001-03-13 | 2006-08-30 | 日本電気株式会社 | 半導体素子の実装構造及びプリント配線基板 |
| US6706563B2 (en) * | 2002-04-10 | 2004-03-16 | St Assembly Test Services Pte Ltd | Heat spreader interconnect methodology for thermally enhanced PBGA packages |
| EP1542519A4 (en) * | 2002-07-31 | 2010-01-06 | Sony Corp | METHOD FOR PCB CONSTRUCTION WITH AN INTEGRATED EQUIPMENT AND PCB WITH INTEGRATED EQUIPMENT AND METHOD FOR PRODUCING A PRINTED PCB AND PRINTED PCB |
| US20050233122A1 (en) * | 2004-04-19 | 2005-10-20 | Mikio Nishimura | Manufacturing method of laminated substrate, and manufacturing apparatus of semiconductor device for module and laminated substrate for use therein |
| JP4800606B2 (ja) * | 2004-11-19 | 2011-10-26 | Okiセミコンダクタ株式会社 | 素子内蔵基板の製造方法 |
| TWI245388B (en) * | 2005-01-06 | 2005-12-11 | Phoenix Prec Technology Corp | Three dimensional package structure of semiconductor chip embedded in substrate and method for fabricating the same |
| US7518236B2 (en) | 2005-10-26 | 2009-04-14 | General Electric Company | Power circuit package and fabrication method |
| US20080190748A1 (en) | 2007-02-13 | 2008-08-14 | Stephen Daley Arthur | Power overlay structure for mems devices and method for making power overlay structure for mems devices |
| DE102007009521B4 (de) * | 2007-02-27 | 2011-12-15 | Infineon Technologies Ag | Bauteil und Verfahren zu dessen Herstellung |
| JP5042762B2 (ja) * | 2007-09-27 | 2012-10-03 | 株式会社テラミクロス | 半導体装置 |
| WO2009020240A2 (en) * | 2007-08-08 | 2009-02-12 | Casio Computer Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US7935893B2 (en) * | 2008-02-14 | 2011-05-03 | Ibiden Co., Ltd. | Method of manufacturing printed wiring board with built-in electronic component |
| US8507320B2 (en) * | 2008-03-18 | 2013-08-13 | Infineon Technologies Ag | Electronic device including a carrier and a semiconductor chip attached to the carrier and manufacturing thereof |
| TWI443789B (zh) * | 2008-07-04 | 2014-07-01 | 欣興電子股份有限公司 | 嵌埋有半導體晶片之電路板及其製法 |
| KR101486420B1 (ko) * | 2008-07-25 | 2015-01-26 | 삼성전자주식회사 | 칩 패키지, 이를 이용한 적층형 패키지 및 그 제조 방법 |
| TWI417993B (zh) * | 2009-02-04 | 2013-12-01 | Unimicron Technology Corp | 具凹穴結構的封裝基板、半導體封裝體及其製作方法 |
| US8358000B2 (en) | 2009-03-13 | 2013-01-22 | General Electric Company | Double side cooled power module with power overlay |
| JP2010251688A (ja) | 2009-03-25 | 2010-11-04 | Nec Toppan Circuit Solutions Inc | 部品内蔵印刷配線板及びその製造方法 |
| JPWO2011016555A1 (ja) * | 2009-08-07 | 2013-01-17 | 日本電気株式会社 | 半導体装置とその製造方法 |
| US8120158B2 (en) * | 2009-11-10 | 2012-02-21 | Infineon Technologies Ag | Laminate electronic device |
| US8822281B2 (en) | 2010-02-23 | 2014-09-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming TMV and TSV in WLCSP using same carrier |
| US8810008B2 (en) | 2010-03-18 | 2014-08-19 | Nec Corporation | Semiconductor element-embedded substrate, and method of manufacturing the substrate |
| JP2011222555A (ja) * | 2010-04-02 | 2011-11-04 | Denso Corp | 半導体チップ内蔵配線基板の製造方法 |
| US8531027B2 (en) | 2010-04-30 | 2013-09-10 | General Electric Company | Press-pack module with power overlay interconnection |
| US8310040B2 (en) | 2010-12-08 | 2012-11-13 | General Electric Company | Semiconductor device package having high breakdown voltage and low parasitic inductance and method of manufacturing thereof |
| US8114712B1 (en) | 2010-12-22 | 2012-02-14 | General Electric Company | Method for fabricating a semiconductor device package |
| CN103563498B (zh) * | 2011-05-13 | 2016-07-06 | 揖斐电株式会社 | 电路板及其制造方法 |
| JP5349532B2 (ja) * | 2011-05-20 | 2013-11-20 | パナソニック株式会社 | 部品内蔵モジュールの製造方法 |
| JP5843539B2 (ja) * | 2011-09-16 | 2016-01-13 | 三菱電機株式会社 | 半導体装置及び当該半導体装置の製造方法 |
-
2013
- 2013-09-26 US US14/037,728 patent/US9209151B2/en active Active
-
2014
- 2014-09-15 TW TW103131743A patent/TWI634632B/zh active
- 2014-09-15 TW TW107120988A patent/TWI679737B/zh active
- 2014-09-15 EP EP14184831.7A patent/EP2854168A3/en not_active Ceased
- 2014-09-15 KR KR1020140121788A patent/KR102295990B1/ko active Active
- 2014-09-22 JP JP2014192072A patent/JP6587792B2/ja active Active
- 2014-09-26 CN CN201410848599.4A patent/CN104681520A/zh active Pending
-
2015
- 2015-09-03 US US14/844,515 patent/US9391027B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| TWI679737B (zh) | 2019-12-11 |
| CN104681520A (zh) | 2015-06-03 |
| TW201907530A (zh) | 2019-02-16 |
| TWI634632B (zh) | 2018-09-01 |
| US9391027B2 (en) | 2016-07-12 |
| KR102295990B1 (ko) | 2021-09-02 |
| US9209151B2 (en) | 2015-12-08 |
| EP2854168A3 (en) | 2015-08-05 |
| EP2854168A2 (en) | 2015-04-01 |
| US20150084207A1 (en) | 2015-03-26 |
| JP2015070269A (ja) | 2015-04-13 |
| TW201523821A (zh) | 2015-06-16 |
| KR20150034617A (ko) | 2015-04-03 |
| US20150380356A1 (en) | 2015-12-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6587792B2 (ja) | 埋め込み型半導体デバイスパッケージおよびその製造方法 | |
| JP6496571B2 (ja) | 極薄埋め込み型半導体デバイスパッケージおよびその製造方法 | |
| KR101978512B1 (ko) | 리드프레임 접속을 갖는 pol 구조체 | |
| JP6302184B2 (ja) | 信頼性のある表面実装集積型パワーモジュール | |
| CN104051377B (zh) | 功率覆盖结构及其制作方法 | |
| JP6342120B2 (ja) | 超薄埋設ダイモジュール及びその製造方法 | |
| US9070568B2 (en) | Chip package with embedded passive component | |
| KR100832653B1 (ko) | 부품 내장형 인쇄회로기판 및 그 제조방법 | |
| KR102392414B1 (ko) | 임베디드 반도체 디바이스 패키지를 위한 전기 상호접속 구조물 및 그 제조 방법 | |
| JP2013243345A5 (enExample) | ||
| US20080142951A1 (en) | Circuit board structure with embedded semiconductor chip | |
| US20150041993A1 (en) | Method for manufacturing a chip arrangement, and a chip arrangement | |
| US9105562B2 (en) | Integrated circuit package and packaging methods | |
| JP4694007B2 (ja) | 三次元実装パッケージの製造方法 | |
| CN115442960A (zh) | 部件承载件组件及其制造方法以及铜过孔的用途 | |
| JP5836019B2 (ja) | 部品内蔵基板およびその製造方法 | |
| US9826646B2 (en) | Component built-in board and method of manufacturing the same, and mounting body | |
| JP2005159201A (ja) | 配線基板およびその製造方法 | |
| JP2005244120A (ja) | 配線基板の製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20170911 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20170911 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20180424 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20180427 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20180705 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20181016 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20181220 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20190312 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20190710 |
|
| RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20190710 |
|
| A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20190719 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20190814 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20190911 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 6587792 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |