JP6587792B2 - 埋め込み型半導体デバイスパッケージおよびその製造方法 - Google Patents

埋め込み型半導体デバイスパッケージおよびその製造方法 Download PDF

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JP6587792B2
JP6587792B2 JP2014192072A JP2014192072A JP6587792B2 JP 6587792 B2 JP6587792 B2 JP 6587792B2 JP 2014192072 A JP2014192072 A JP 2014192072A JP 2014192072 A JP2014192072 A JP 2014192072A JP 6587792 B2 JP6587792 B2 JP 6587792B2
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dielectric
semiconductor device
package structure
dielectric layer
layer
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JP2015070269A5 (enExample
JP2015070269A (ja
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シャクティ・シン・チャウハン
ポール・アラン・マックコネリー
アルン・ヴィルパクシャ・ゴウダ
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General Electric Co
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General Electric Co
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    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
    • H05K1/185—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
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    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
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    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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