TW201523821A - 嵌入式半導體裝置封裝及其製造方法 - Google Patents

嵌入式半導體裝置封裝及其製造方法 Download PDF

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Publication number
TW201523821A
TW201523821A TW103131743A TW103131743A TW201523821A TW 201523821 A TW201523821 A TW 201523821A TW 103131743 A TW103131743 A TW 103131743A TW 103131743 A TW103131743 A TW 103131743A TW 201523821 A TW201523821 A TW 201523821A
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dielectric
semiconductor device
package structure
layer
dielectric layer
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TW103131743A
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English (en)
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TWI634632B (zh
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Shakti Singh Chauhan
Paul Alan Mcconnelee
Arun Virupaksha Gowda
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Gen Electric
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Abstract

一種封裝結構，包括一第一介電層、至少一半導體裝置，附接至介電層、一或更多介電薄板，施加至介電層且在半導體裝置附近以將半導體裝置嵌入於其中、及複數個通孔，被形成至半導體裝置，其係形成在介電層和一或更多介電薄板之至少一者中。封裝結構亦包括金屬互連，形成在通孔中且在封裝結構的一或更多面外表面上以形成至半導體裝置的電互連。介電層係由在一層壓程序期間不流動的一材料組成，且一或更多介電薄板之各者係由配置以當在層壓程序期間固化時熔化和流動的一可固化材料組成，以便填充在半導體裝置周圍的任何空氣間隙中。

Description

嵌入式半導體裝置封裝及其製造方法
本發明之實施例一般關於用於封裝半導體裝置的結構及方法，尤其是一種關於具有在封裝中形成所有電和熱互連之功率覆蓋(POL)互連的嵌入式封裝結構。
表面黏著技術係一種用於建構電子電路的方法，其中表面黏著元件或封裝係直接黏著至印刷電路板(PCB)或其他類似外部電路的表面上。在工業中，表面黏著技術已取代將具有導線的元件剛好放入在電路板中之孔洞中的通孔技術建構方法。
用於表面黏著半導體裝置(或多晶片模組)的一種常見技術係用以提供一種裝置/模組係封裝在嵌入化合物內的封裝結構。封裝製造程序開始於藉由黏著劑來將一或更多半導體裝置置放於介電層上，其中介電層覆蓋每個半導體裝置的主動側。接著在介電層上電鍍金屬互連以形成至半導體裝置的直接金屬連線。若需要的話，則可 能透過額外的層壓再分佈層來路由互連，且提供輸入/輸出系統以使封裝能表面黏著至PCB或外部電路上。在半導體裝置附近施加嵌入化合物以將半導體裝置封裝於其中。
在半導體裝置係高電壓功率半導體裝置的實施例中，功率半導體裝置能藉由功率覆蓋(POL)封裝和互連系統來表面黏著至外部電路，其中POL封裝也提出一種方式來移除裝置所產生的熱且保護裝置不受外部環境之害。標準POL封裝製造程序通常開始於藉由黏著劑來將一或更多半導體裝置置放於介電層上且鑽通孔通過介電質至裝置。金屬互連(例如，銅互連)接著電鍍至介電層上且至通孔中以形成至半導體裝置的直接金屬連線，以便形成子模組。金屬互連可能以低輪廓的平面互連結構為形式，其提供至及從半導體裝置的輸入/輸出(I/O)系統之形成。接著使用用於電和熱連接的焊接互連來將POL子模組焊接至陶瓷基板(具有DBC的氧化鋁、具有AMB Cu的AlN、等等)。接著使用毛細管流動(毛細管底部填充)、無流動底部填充或注射成型(模製化合物)使用介電有機材料來填充在介電層與陶瓷基板之間之半導體裝置周圍的間隙以形成POL封裝。
關於以上提出之嵌入半導體裝置、模組、及/或功率裝置的封裝製造程序，認為許多缺點與其關聯。例如由於其斷裂韌性不良和高吸濕性，一般使用的封裝劑和嵌入化合物當需要符合濕度敏感等級(MSL)資格時具有 有限的可靠度。此外，通常使用的封裝劑/嵌入化合物在採購上會是昂貴的以及在應用上是緩慢且費時的。
再者，且尤其是關於封裝功率裝置/模組，通常用於將POL子模組電性和熱性連接至陶瓷基板的焊接操作會是昂貴且費時的，其中焊接所需的額外溫度偏差也不利地影響模組可靠度。此外，將陶瓷基板包含在POL封裝中由於陶瓷基板的尺寸/厚度而限制POL封裝在尺寸和厚度上可實現的減少(即，小型化)。因此，欲提高電、熱和機械效能，同時小型化模組以減少系統重量、成本和尺寸，是受到現有POL封裝結構限制的。
因此，將期望提出一種半導體裝置封裝結構，其係表面黏著相容的，且具有非常低的厚度。將進一步期望這類封裝結構以降低的成本來製造但增加系統級效能。
本發明之實施例藉由提供一種具有在封裝中形成所有電和熱互連之POL互連的POL封裝結構來克服上述缺點。
依照本發明之一種態樣，一種封裝結構包括：一第一介電層；至少一附接至第一介電層的半導體裝置；一或更多介電薄板，施加至第一介電層且在至少一半導體裝置附近以便將至少一半導體裝置嵌入於其中；及複數個通孔，被形成至至少一半導體裝置，複數個通孔係形 成在第一介電層和一或更多介電薄板之至少一者中。封裝結構也包括金屬互連，形成在複數個通孔中且在封裝結構的一或更多面外表面上以形成至至少一半導體裝置的電互連。第一介電層係由在一層壓程序期間不流動的一材料組成，且一或更多介電薄板之各者係由配置以當在層壓程序期間固化時熔化和流動的一可固化材料組成，使得一或更多介電薄板熔化和流動以填充存在於至少一半導體裝置周圍的任何空氣間隙。
依照本發明之另一種態樣，一種製造一半導體裝置封裝結構的方法包括藉由一黏著劑來將至少一半導體裝置附接至一第一介電層，形成配置以當固化時熔化和流動之一可固化材料的一或更多介電薄板，其中每個介電薄板係在一未固化或部分固化狀態下，在第一介電層上施加一或更多介電薄板以便位於至少一半導體裝置附近，在最後介電薄板的外表面上施加一銅箔，及固化一或更多介電薄板以使一或更多介電薄板熔化和流入存在於至少一半導體裝置周圍的任何空氣間隙中，且以便將至少一半導體裝置嵌入於其中，其中第一介電層在固化一或更多介電薄板期間不流動。方法也包括形成至至少一半導體裝置的複數個通孔，複數個通孔係形成在第一層和一或更多介電薄板之至少一者中，及在複數個通孔中且在封裝結構的一或更多外表面之至少一部分上方形成金屬互連，金屬互連形成至至少一半導體裝置的電互連。
依照本發明之又一種態樣，一種POL封裝結 構包括：一第一介電層，具有一黏著劑塗覆於其至少一部分上；一或更多半導體裝置，藉由黏著劑來附接至第一介電層，其中在其上具有接觸墊的一或更多半導體裝置之各者的表面係附接至第一介電層；及一介電封裝劑，位於一或更多半導體裝置附近的第一介電層上以便將一或更多半導體裝置嵌入於其中，介電封裝劑包含配置以當固化時熔化和流動的一或更多未固化或部分固化的介電薄板，以便填充存在於一或更多半導體裝置周圍的任何空氣間隙。POL封裝結構也包括：複數個通孔，被形成至一或更多半導體裝置且在第一介電層和介電封裝劑之至少一者中；及POL互連，形成在複數個通孔中以形成至一或更多半導體裝置的所有電和熱互連且在POL封裝結構中。第一介電質係配置以在固化一或更多介電薄板期間不流動。
將從結合附圖所提出的本發明之較佳實施例的以下詳細說明更容易了解這些及其他優點和特徵。
10‧‧‧封裝結構
12‧‧‧半導體裝置
14‧‧‧第一介電層
16‧‧‧第二介電層
18‧‧‧前表面
20‧‧‧後表面
22‧‧‧黏著劑
24‧‧‧封裝劑
26‧‧‧介電薄板
28‧‧‧開口
30‧‧‧通孔
32‧‧‧前表面
34‧‧‧後表面
36‧‧‧通孔
38‧‧‧金屬互連
40‧‧‧銅層
42‧‧‧剝離層
44‧‧‧銅載體層
46‧‧‧對準標記
50‧‧‧接觸墊
52‧‧‧對準標記
54‧‧‧層
56‧‧‧層
58‧‧‧黏著劑
59‧‧‧通孔
60‧‧‧封裝結構
61‧‧‧銅箔
62‧‧‧介電網路材料
64‧‧‧開口
66‧‧‧封裝結構
70‧‧‧封裝結構
72‧‧‧功率半導體裝置
74‧‧‧閘極驅動器
76‧‧‧被動裝置
78‧‧‧銅墊片
圖式繪示目前所設想用於實現本發明之實施例。
在圖中：第1圖係根據本發明之一實施例之功率覆蓋(POL)封裝結構的示意剖面側視圖。
第2-9圖係根據本發明之一實施例之在製造/建立程序的各種階段期間之POL封裝結構的示意剖面側 視圖。
第10-16圖係根據本發明之一實施例之在另一製造/建立程序的各種階段期間之POL結構的示意剖面側視圖。
第17圖係藉由第2-9圖或第10-16圖之製造/建立程序所形成之POL封裝結構的示意剖面側視圖，繪示根據本發明之另一實施例之在POL封裝結構上所進行的額外製造/建立步驟。
第18圖係第17圖之POL封裝結構的示意剖面側視圖，繪示根據本發明之另一實施例之在POL封裝結構上所進行的額外製造/建立步驟。
第19圖係根據本發明之另一實施例之POL封裝結構的示意剖面側視圖。
第20圖係根據本發明之另一實施例之POL封裝結構的示意剖面側視圖。
第21圖係根據本發明之另一實施例之POL封裝結構的示意剖面側視圖。
第22圖係根據本發明之另一實施例之POL封裝結構的示意剖面側視圖。
第23圖係根據本發明之另一實施例之POL封裝結構的示意剖面側視圖。
本發明之實施例提供一種具有在功率模組中 形成至半導體裝置的所有電和熱互連之功率覆蓋(POL)互連的嵌入式功率模組封裝結構，以及一種形成這類封裝結構的方法。
參考第1圖，根據本發明之一實施例來顯示POL封裝和互連結構10。封裝結構10包括半導體裝置12，其能以通常能被描述為「功率裝置」或「非功率裝置」的形式，且因此能以例如晶粒、二極體、MOSFET、專用積體電路(ASIC)、或處理器的形式。儘管單一半導體裝置12係顯示於第1圖中，但認為額外半導體裝置或電子元件能包括在POL結構10中，如於下將關於本發明之另一實施例所述。半導體裝置12係封裝在封裝結構10內，使得直接金屬互連形成至裝置的所有電及/或熱互連。
如第1圖所示，根據示範實施例，封裝結構10包括在封裝結構10每個相對側上的介電層(其中半導體裝置12位於其間)，其中層泛稱為第一介電層14和第二介電層16。介電層14、16係以層壓或膜的形式來設置且係由選擇可以在使用和框架處理期間對通孔提供機械和溫度穩定性，以及對通孔形成和POL處理提供適當介電特性和電壓擊穿強度和處理能力的材料來形成-且由此介電層14、16能稱為「POL介電質」。此外，選擇可以在封裝結構10上進行的層壓程序期間保持穩定的材料來形成介電層14、16。亦即，介電層14、16係由適當材料形成，使得它們係配置以在封裝結構10上所進行的層壓程 序期間不流動。藉此，根據本發明之實施例，介電層14、16可能由複數個介電材料(如Kapton®、Ultem®、聚四氟乙烯(PTFE)、Upilex®、聚碸材料(例如，Udel®、Radel®)、或另一聚合物膜(如液晶聚合物(LCP)或聚醯亞胺材料))之其一者形成。為了清楚並在封裝結構10中區分介電層14、16與其他介電材料，以下介電層14、16稱為聚醯亞胺層14、16，雖然此術語並不意味著限制從特定介電材料形成層14、16。
如第1圖所示，聚醯亞胺層14、16係設置於封裝結構10的兩側(即，在封裝結構的前和後表面18、20)上，以便提供在兩個表面上形成通孔和圖案化金屬互連的能力，如將於下進一步所說明。半導體裝置12係位於聚醯亞胺層14、16之間，其中裝置12係藉由黏著劑22來附接至聚醯亞胺層14。也包括在封裝結構10中的是介電封裝劑24(即，POL封裝劑)，其係設置於聚醯亞胺層14、16之間。封裝劑24用以填充在封裝結構10內的空間隙，其可能存在於半導體裝置12周圍且在聚醯亞胺層14、16之間，且根據一實施例，可能將聚醯亞胺層14「黏合」至裝置12，且由此可能由一或更多材料形成。
封裝劑24係由以「膜」或「面板」或「薄板」形式設置的一或更多介電層26組成，使得若需要的話，多個介電薄板26能彼此堆疊至填充在半導體裝置12附近且在聚醯亞胺層14、16之間的區域所需的所需高度/ 厚度。介電薄板26係從如預浸漬材料、印刷電路板核心材料、聚合物樹脂的有機材料、或為例如未固化或部分固化的(即，B階段)的其他適當黏著劑形成，使得它們能容易地以其預固化膜形式來堆疊。根據本發明之一實施例，介電薄板26包括形成在裡面的開口/切口28以接收在裡面的半導體裝置12且容納在那附近的薄板26之定位。另外，認為介電薄板26的區段能置放於半導體裝置12附近。
為了填充在封裝結構10內的空間隙，介電薄板26受到層壓程序(通常在真空環境下，在提高的溫度下且在機械壓力下)，其使介電薄板26「熔化」和流動。介電薄板26因此失去其膜形成並流動以填充在半導體裝置12周圍且在聚醯亞胺層14、16之間的任何空的空氣間隙，使得設置介電封裝劑24，這通常保護半導體裝置12不受周圍環境之害。
如第1圖所示，複數個通孔30係形成通過聚醯亞胺層14向下至半導體裝置12的前表面32。在半導體裝置12係功率裝置的實施例中，如在第1圖中，通孔30也形成至半導體裝置12的後表面34以符合電和熱要求(例如，為了製造所需要的電連線且從功率半導體裝置移除熱)。當需要在前與後表面之間的電連線時，通孔36也形成通過聚醯亞胺層14、16和介電薄板26。金屬互連38隨後形成在封裝結構10中以於其中提供電和熱連線/路徑，其中互連38係形成在通孔30、36中且分別向外 至聚醯亞胺層14、16的面外前和後表面18、20上，使得封裝結構10的前和後表面18、20兩者包括互連形成於其上。根據本發明之實施例，金屬互連38包含「POL互連」，其被形成為在裝置12中形成直接電連線之堅固的鍍銅互連。依據在裝置上的金屬化，在一些實施例中，設置濺射黏著層(鈦、鉻等)以及於其上能鍍銅的濺射銅種子層。如第1圖所示，金屬互連38被圖案化和蝕刻為期望形狀，如以便提供至封裝結構10的電和熱連線。根據一實施例，金屬互連38被圖案化和蝕刻以在封裝結構10的後側(即，銅墊)上提供大面積的熱和電連線，例如，其能將封裝結構附接至散熱片。
因此，提供在結構之兩側上具有金屬互連38的封裝結構10。由於其層壓程序，封裝結構10能完全地嵌入半導體裝置12且由此係表面黏著技術(SMT)相容的且可能也提供堆疊其他電子裝置於其上。在半導體裝置12係功率裝置的實施例中，封裝結構10更提供雙面冷卻且消除對額外的多層基板(如DBC基板等)之需求，其通常將用於電和熱功能，由此，基板完全地被熱通孔和大銅墊取代以在裝置後側熱擴散。上述在封裝結構10中封裝功率裝置中消除多層基板消除第二級組合程序(如焊接、底部填充(或二次成型)等)，且致能具有被高度小型化之極小形狀因子的封裝結構10。
現在參考第2-9圖，根據本發明之一實施例，提出用於製造POL封裝結構的技術之程序步驟的詳 細視圖。第2-9圖所示之技術係顯示和說明用於如第1圖所示之封裝結構10(即，僅包括單一半導體裝置)，然而，認為所述之程序可適用於製造嵌入各種配置之多晶片模組的封裝結構。
參考第2圖，封裝結構10的建立程序開始於提供預金屬化介電層。根據本發明之一實施例，預金屬化介電層包括介電壓層或膜14，其係由複數個介電材料(如Kapton®、Ultem®、聚四氟乙烯(PTFE)、Upilex®、聚碸材料(例如，Udel®、Radel®)、或另一聚合物膜(如液晶聚合物(LCP)或聚醯亞胺材料))之其一者形成-且以下稱為聚醯亞胺膜14。銅層40係在聚醯亞胺膜14的一個表面上金屬化，其中銅層40具有施加至其後表面的剝離層42，其將額外的銅載體層44固定至銅層40以在封裝結構10的建立程序期間提供穩定性。剝離層42允許隨後在製造程序的後續步驟中移除銅載體層44。
如第2圖進一步所示，對準標記46係以雷射鑽孔穿過聚醯亞胺膜14且進入銅層40中以使得半導體裝置(例如，晶粒、MOSFET等)12得置放於預金屬化介電層上。如第3圖所示，對聚醯亞胺膜14塗覆黏著劑22以將半導體裝置12固定於其上，如藉由絲網印刷施加、塗佈、或旋塗施加。根據本發明之一實施例，黏著劑22得只塗覆於半導體裝置12欲置放於聚醯亞胺膜14上的位置上。另外，黏著劑22可能塗覆於整個聚醯亞胺膜14 上。當在聚醯亞胺膜14上沉積黏著劑22時，半導體裝置12接著使用對準標記46作為置放引導來置放於聚醯亞胺膜14上。半導體裝置12接著藉由固化黏著劑22來固定至聚醯亞胺膜14。
現在參考第4圖，當在預金屬化介電層14上置放和固定半導體裝置12時，一或更多介電薄板26被製備並接著置放於預金屬化介電層14上且在半導體裝置12附近，其中施用的介電薄板26的數量係基於半導體裝置12的厚度來決定。若需要複數個介電薄板26，則以堆疊佈置方式施加薄板以封裝半導體裝置12。介電薄板26係從如預浸漬材料、PCB核心材料、聚合物樹脂的有機材料、或以其預固化膜為形式(使得它們能容易地被堆疊)的其他適當黏著劑形成，且以下泛稱為預浸漬薄板26。在準備預浸漬薄板26中，設置預浸漬材料的膜或面板且對應於半導體裝置12的位置於其中形成開口28(即，切口)。準備的預浸漬薄板26(具有開口28形成於其中)接著彼此堆疊至期望高度或厚度，使得它們完全地圍繞半導體裝置12。當堆疊預浸漬薄板26時，後側介電層16(例如，聚醯亞胺層)係塗覆於這疊預浸漬薄板26上，其中後側聚醯亞胺膜16包含預金屬化層。根據本發明之一實施例，後側聚醯亞胺膜16能被預金屬化以便為了提供增加的熱功能而具有增加厚度的銅層48。
在製造程序的下一個步驟中，且如第5圖所示，進行層壓程序以使預浸漬薄板26熔化和流動。層壓 程序可能在真空環境下，在提高的溫度下且在機械或空氣壓力下進行，以便使預浸漬薄板26熔化且藉此失去其膜形式。當熔化時，設置於聚醯亞胺膜14、16之間的預浸漬材料流動以填充在半導體裝置12周圍且在封裝結構內之空的空氣間隙，且因此能被描述為形成封裝劑24。當冷卻封裝結構10時，預浸漬材料變得被完全地固化且在半導體裝置12附近能硬化以封裝裝置。
如第6圖所示，當完成層壓程序時，藉由剝離層42來從銅層40移除銅載體層44。然後，清洗在聚醯亞胺膜14上的剩餘銅層40以準備用於隨後的通孔形成和金屬化步驟。形成通過聚醯亞胺膜14和後側聚醯亞胺膜16(即，聚醯亞胺膜和銅層)的複數個通孔30係顯示於第7圖中。根據本發明之實施例，可能藉由雷射剝蝕或雷射鑽孔程序、電漿蝕刻、光界定、或機械鑽孔程序來形成通孔30。通孔30被形成向下至半導體裝置12上的接觸墊50(使用對準鑽孔以看見晶粒)以形成所連接至的電連線，且在半導體裝置12係功率裝置的實施例中(如這裡的情況)，通孔30也被形成至半導體裝置12的後側34。向下至半導體裝置12上之接觸墊50的通孔30係形成通過聚醯亞胺膜14，且由此這些通孔30的特徵和精確能在緊閉約束內被控制。根據一實施例，至半導體裝置12之後側34的通孔30係較粗糙的特徵且由於其形成通過預浸漬封裝劑24(其具有纖維或其他內含物)而不能以與至接觸墊50的通孔30相同的精確度來形成(即，限 制行間距和通孔直徑)，雖然認為在一些實施例中，至裝置12之後側34的通孔30可能僅形成通過聚醯亞胺膜16。除了形成向下至半導體裝置12的通孔30之外，通孔36也鑽孔過整個建立體(即，鑽過聚醯亞胺膜14、16和預浸漬封裝劑24)。
一旦已形成通孔30、36向下至半導體裝置12且通過封裝建立體，且當完成清洗通孔時(如透過反應性離子蝕刻(RIE)去灰(desoot)程序)，若期望的話，則金屬互連38就接著形成在封裝結構中，如第8圖所示。金屬互連38被形成為POL互連，其根據一實施例，係透過無電電鍍或電解電鍍來形成，雖然認為也能使用金屬沉積的其他方法(例如，濺射)。例如，在封裝結構的前和後表面18、20兩者上填充通孔且將銅的厚度增加(即，「鍍上」)至期望程度的電鍍程序之前，可能首先藉由濺射或無電電鍍程序來將鈦或鈀黏著層和銅種子層施加在通孔30、36中。如第9圖所示，接著隨後在所施加的銅上進行圖案化和蝕刻以形成具有期望形狀的POL互連38。儘管於第8和9圖中顯示施加連續銅層且隨後圖案化和蝕刻連續銅層來形成互連38，但認為反而能採用經由半加成法電鍍程序來圖案化和電鍍互連38以形成互連38。
由此形成完成的封裝結構10，其在結構的兩側上提供互連。封裝結構10係SMT相容的且提供MSL能力、機械堅固性、雙面冷卻、及低材料成本，全部具有 極小的形狀因子，以便允許產生高度小型化的封裝結構10。
現在參考第10-16圖，根據本發明之另一實施例，提出用於製造POL封裝結構的另一技術之程序步驟的詳細視圖。第2-9圖所示之技術再次被顯示和說明用於製造如第1圖所示之封裝結構10(即，僅包括單一半導體裝置)，然而，再次認為所述之程序可適用於製造嵌入各種配置之多晶片模組的封裝結構。
參考第10圖，封裝結構的建立程序開始於設置介電層14，如聚醯亞胺壓層或膜。雖然未示出，但聚醯亞胺膜14可能置放於框架或面板結構以在封裝結構的建立程序期間提供穩定性。對準標記52(透過雷射削片或其他方法)被形成至聚醯亞胺膜14中以提供隨後將半導體裝置(例如，晶粒)準確置放於聚醯亞胺膜上。如第11圖所示，對聚醯亞胺膜14塗覆黏著劑22以將半導體裝置12固定於其上，如藉由絲網印刷施加、塗佈、或旋塗施加。根據本發明之一實施例，可能只有在將置放半導體裝置12的位置塗覆黏著劑22於聚醯亞胺膜14上。另外，黏著劑22可能塗覆於整個聚醯亞胺膜14上。當在聚醯亞胺膜14上沉積黏著劑22時，接著使用對準標記52作為置放引導來置放半導體裝置12於聚醯亞胺膜上。接著藉由固化黏著劑22來固定半導體裝置12至聚醯亞胺膜14。
現在參考第12圖，當在聚醯亞胺膜14上置 放和固定半導體裝置12時，一或更多介電薄板26被製備且隨後置放於聚醯亞胺膜14上且在半導體裝置12附近，其中所施用之介電薄板26的數量係基於半導體裝置12的厚度來決定。若需要複數個介電薄板26，則以堆疊佈置方式設置薄板以封裝半導體裝置12。薄板26一般係從如預浸漬材料、PCB核心材料、聚合物樹脂的低吸濕有機材料、或以其預固化膜為形式(使得它們能容易地被堆疊)的其他適當黏著劑形成，且以下泛稱為預浸漬薄板26。在準備預浸漬薄板26中，設置預浸漬材料的膜或面板且對應於半導體裝置12的位置於其中形成開口28(即，切口)。準備的預浸漬薄板26(具有開口28形成於其中)接著彼此堆疊至期望高度或厚度，使得它們完全地圍繞半導體裝置12。當堆疊預浸漬薄板26時，後側介電層16(例如，聚醯亞胺膜)係塗覆於這疊預浸漬薄板26上。聚醯亞胺層/膜14、16能用以在封裝的兩側上提供良好的特徵尺寸控制且也提供結構平衡。在另一實施例中，能施加銅箔或膜來取代介電層16以防止預浸漬薄板26黏附至用以進行層壓步驟/程序的層壓製機，如將於之後進一步所詳細說明。
在製造程序的下一個步驟中，且如第13圖所示，進行層壓程序以使預浸漬材料熔化和流動成連續介電封裝劑24。層壓程序可能在真空環境下，在提高的溫度下且在機械或空氣壓力下進行，以便使預浸漬薄板26熔化且藉此失去其膜形式並流動以填充在半導體裝置12周 圍之任何空的空氣間隙。預浸漬封裝劑被完全地固化且在半導體裝置12附近能硬化以封裝裝置。
如第14圖所示，當完成層壓程序時，複數個通孔30係形成通過聚醯亞胺膜14和後側聚醯亞胺膜16。根據本發明之一實施例，可能藉由雷射剝蝕或雷射鑽孔程序、或機械鑽孔程序來形成通孔30，其中通孔30被對準以便被形成向下至半導體裝置12之前側32上的接觸墊50以便形成所連接至的電連線。在所示之實施例中，通孔30也被形成至半導體裝置12的後側34以從裝置移除熱及/或如對功率裝置製造電連線( )-雖然認為在所有實施例中不需要上述後側通孔且這是取決於該裝置。除了形成向下至半導體裝置12的通孔30之外，通孔36也被鑽孔穿過整個建立堆疊(即，穿過聚醯亞胺膜14、16和預浸漬封裝劑24)。
一旦已形成通孔30、36向下至半導體裝置12且通過封裝劑24，POL金屬互連38就接著形成在封裝結構中，如第15圖所示。根據一實施例，POL金屬互連38可能透過濺射和電鍍應用之組合來形成，雖然認為也能使用金屬沉積的其他方法(例如，無電電鍍)。例如，在POL封裝結構的前和後表面18、20兩者上填充通孔且將銅的厚度增加(即，「鍍上」)至期望程度的電鍍程序之前，可能首先藉由濺射來將鈦或鈀黏著層和銅種子層施加在通孔30、36中。如第16圖所示，接著隨後在所施加的銅上進行圖案化和蝕刻以形成具有期望尺寸/形狀的POL 互連38。儘管於第15和16圖中顯示施加連續銅層且隨後圖案化和蝕刻連續銅層來形成POL互連38，但認為反而能採用經由半加成法電鍍程序來圖案化和電鍍POL互連以形成POL互連38。
在第2-9圖和第10-16圖中所提出的每個製造程序中，能進行額外步驟以形成多層封裝結構。亦即，使用封裝結構10作為「起始堆疊」，能對結構10的兩個外表面施加材料的額外層。於是，參考第17圖，當形成金屬互連38時，對封裝結構10的兩側加上額外層54、56。根據本發明之一實施例，層54、56係由具有銅箔施加於其上的印刷電路板(PCB)預浸漬材料形成，其係疊層於聚醯亞胺層14、16上。根據另一實施例，層54、56係由聚醯亞胺材料形成，其中層54、56係經由黏著劑58(以虛線來顯示)來施加至聚醯亞胺層14、16。接著隨後在附加層54、56中鑽通孔59，如第18圖所示，其中POL金屬互連38係在通孔59中被電鍍且在層54、56的外表面上被圖案化。
儘管未顯示於第18圖中，但認為可能進行製造程序的額外步驟，如在圖案化POL互連38和層54、56上施加焊料最後塗層和焊錫遮罩以提供用於其銅的保護塗層。除了焊料以外，認為焊錫遮罩暴露的銅墊也能與金屬化Ni或Ni/Au或有機可焊性保護(OSP)層一起處於終止的狀態。第二級I/O互連可能接著施加至在焊錫遮罩中之開口所暴露的墊。在一實施例中，I/O互連墊係與可焊 最後加工一起處於終止的狀態以形成地閘陣列(LGA)或與焊料一起凸起以形成球閘陣列(BGA)焊料凸塊t以使封裝結構能表面黏著至外部電路，例如，具有焊料凸塊提供高可靠的第二層互連結構，其具在高應力條件下失效的電阻性。
在以上第2-9圖和第10-16圖中所提出的每個製造程序中，認為能對預浸漬薄板施加銅箔或膜而不是對封裝劑24施加第二聚醯亞胺層16(即，這疊預浸漬薄板26)。亦即，銅箔能取代聚醯亞胺層16，因為銅箔於此同樣地當作關於防止預浸漬層26黏附至黏至層壓機表面的條狀物。在封裝結構中實作銅箔61的實施例係繪示於第19圖中。在實作銅箔61中，認為銅軌線(即，金屬互連38)將形成在預浸漬材料26上的此銅中而不是形成在聚醯亞胺層16上。在如此做時，通孔30將首先形成通過銅箔61，且POL金屬互連38將接著透過濺射和電鍍應用之組合來形成於其上，其中進行連續銅層施加和隨後的圖案化和蝕刻或進行半加成法電鍍程序以形成POL互連38。
現在參考第20-23圖，顯示了用於封裝半導體裝置之POL封裝結構的額外實施例。在第20-23圖所示之每個POL封裝結構實施例具有與第1圖所示和所述之封裝結構10類似的結構，因為它們藉由使用可能堆疊並位於半導體裝置附近且隨後被固化以於此附近熔化/流動的一或更多介電薄板來完全地嵌入半導體裝置，其中互連 係形成在封裝結構的兩側上以在內部提供至半導體裝置的所有電(和熱)連線。
首先參考第20圖，根據本發明之另一實施例來顯示封裝結構60。封裝結構60非常類似於第1圖之封裝結構10，除了封裝結構60包括位於半導體裝置12附近的介電網路材料62(在此稱為「POL網路」)以外。根據本發明之實施例，POL網路62係由印刷電路板(PCB)核心材料、聚醯亞胺膜/層、陶瓷材料、複合介電材料、或顯示低吸濕特性並對POL結構提供機械堅固性(即，介電網路62被建構為相較於介電薄板26具有增加的剛性)且在層壓封裝結構60期間不回流的其他類似/適當有機材料形成。根據一實施例，POL網路62可能也包括在裡面的銅電路。此外，基於形成它的材料，POL網路62在層壓程序期間不流動。POL網路62被形成為包括在裡面的開口/切口64以容納半導體裝置12和通孔36，其中POL網路62具有適當厚度。如第19圖進一步所示，POL網路62結合封裝劑24以完全地將半導體裝置12嵌入於封裝結構60內。如先前針對第1圖所述，介電封裝劑24被提供為未固化介電材料26(例如，預浸漬材料、聚合物樹脂等)的一或更多薄板。薄板26係位於聚醯亞胺層14上的POL網路62與半導體裝置12之間的空間隙中，其中封裝結構60受到層壓程序以使介電薄板26熔化，藉此使薄板失去其膜形式並流動以填充在半導體裝置12和介電網路62周圍之任何空的空氣間隙。
現在參考第21圖，根據本發明之另一實施例來顯示POL封裝結構66。封裝結構66非常類似於第1圖之封裝結構10，除了封裝結構66不包括位於層14對面的一側上之介電封裝劑24上的一層介電材料以外，層14在層壓期間不熔化和流動(例如，聚醯亞胺層)，如在第1圖之封裝結構10中的層16(即，聚醯亞胺層16)。因此，在封裝結構66中，聚醯亞胺層14係設置於封裝結構10的前表面18上，而介電封裝劑24形成封裝結構66的後表面20。半導體裝置12係位於聚醯亞胺層14上且藉由黏著劑22來固定於此，其中介電封裝劑24係沉積於聚醯亞胺層14上以便包含裝置12。如以上詳細所述，封裝劑24係由從為未固化或部分固化(即，B階段)之有機材料(例如，預浸漬材料、PCB核心材料、聚合物樹脂、或其他適當黏著劑)形成的一或更多介電薄板26組成，其中薄板係以「膜」或「面板」形式來施加至聚醯亞胺層14上，使得若需要的話，多個介電薄板26能彼此堆疊至填充在半導體裝置12附近的區域所需的所需高度/高度。介電薄板26受到層壓程序，其使介電薄板26熔化且失去其膜形式以流動且填充在半導體裝置12周圍之任何空的空氣間隙。
如第21圖所示，複數個通孔30係形成通過聚醯亞胺層14向下至半導體裝置12的前表面32。通孔30也形成通過封裝劑24至半導體裝置12的後表面34以符合電和熱要求(例如，當裝置12係功率半導體裝置 時)。通孔36也形成通過聚醯亞胺層14和介電薄板26。POL金屬互連38隨後形成在封裝結構66中以於其中提供電和熱連線/路徑，其中互連38係形成在通孔30、36中且向外至封裝結構66的前和後表面18、20上。
儘管未顯示於第21圖中，但認為封裝結構66能進一步包括在裡面的POL網路結構(例如，在第20圖中的POL網路62)，其係位於半導體裝置12附近且在封裝劑24內以對POL結構提供穩定性。POL網路將由印刷電路板(PCB)核心材料、聚醯亞胺膜/層、陶瓷材料、或複合介電材料形成-使得POL網路結構在封裝結構66的層壓程序期間不流動。
根據一實施例，封裝結構66能當作能對其施加額外層的「起始堆疊」，類似於第17圖所示之封裝結構10。亦即，當在封裝結構66中形成金屬互連38時，對封裝結構64的兩側附加額外層54、56，如第22圖所示。根據本發明之一實施例，層54、56係由具有銅箔形成於上方的印刷電路板(PCB)浸漬材料形成，其係層壓至聚醯亞胺層14、16上。根據另一實施例，層54、56係由聚醯亞胺材料形成，其中層54、56係經由黏著劑58(以虛線來顯示)來施加至聚醯亞胺層14、16。接著，隨後在附加層54、56中鑽通孔60，如第18圖所示，其中金屬互連38係在通孔60中被電鍍且在層54、56的外表面上被圖案化。
現在參考第23圖，根據本發明之另一實施例 來顯示封裝結構70，其中封裝具有多個電子元件的電源模組。封裝結構70包括在裡面之以功率裝置、控制電路、及/或被動裝置為形式的複數個電子元件，其中功率半導體裝置72(例如，晶粒、二極體、MOSFET)、閘極驅動器74、和被動裝置76係顯示於第22圖中，雖然認為較多或較少數量的電子裝置/元件能包括在POL結構70中。此外，根據一實施例，銅墊片78係可選地被包括且(例如，藉由焊料80來)附接至半導體裝置72的後側22，雖然認為不存在墊片78-通孔30反而能延伸至裝置72的後表面(即，鑽較高的通孔)以補足高度差。
如第23圖所示，聚醯亞胺層14、16係設置於封裝結構70的兩側上以便提供在兩個表面上形成POL通孔和圖案化POL金屬互連的能力。電子元件72、74、76係位於聚醯亞胺層14、16之間，其中電子元件72、74、76係藉由黏著劑22來附接至聚醯亞胺層14。介電封裝劑24係設置於聚醯亞胺層14、16之間，其係由以「膜」或「面板」形式所提供的一或更多介電薄板26組成，使得多個介電薄板26能彼此堆疊至填充在半導體裝置72、閘極驅動器74、和被動裝置76附近的區域所需的所需高度/高度。介電薄板26受到層壓程序，其使介電薄板26熔化且失去其膜形式以流動並填充在電子元件72、74、76周圍且在聚醯亞胺層14、16之間之任何空的空氣間隙，如先前所述。雖然未示出，但認為POL網路結構(例如，在第20圖中的網路62)能位於在半導體裝置12 附近的封裝劑24內以對POL結構提供穩定性，其中POL網路結構係由在層壓程序期間不流動的材料形成。
如第23圖所示，複數個通孔30係形成通過聚醯亞胺層14向下至電子元件72、74、76。通孔30也形成通過聚醯亞胺層16至在半導體裝置72之後表面上的墊片78。通孔36也形成通過聚醯亞胺層14、16和介電薄板26。金屬互連38隨後形成在封裝結構70中以於其中提供電和熱連線/路徑。如第23圖所示，POL互連38被圖案化和蝕刻成期望形狀，如以在封裝結構70的前側18上提供電連線且在封裝結構70的後側20上提供大面積的電和熱連線，例如，其使結構能附接至散熱片或系統I/O。
根據本發明之一實施例，且如第23圖中的虛線所示，能進一步處理第22圖之封裝結構70，如藉由將熱介面材料(TIM)82附加至結構的後側20(即，至介電層16上)。亦即，具有熱傳導性的一層相容TIM 82被施加至POL結構70上且在POL互連38上方，其在封裝結構的後側20上形成大銅墊。適當TIM的實例包括，但不限於黏著劑、油脂、凝膠、墊、膜、液態金屬、可壓縮金屬、及相變材料。例如，液態金屬TIM通常是銦-鎵合金，其係處於高於通常在電力電子裝置應用中遇到之溫度的液體狀態。可壓縮金屬足夠軟以製造在散熱片與POL配合表面之間的緊密接觸且可能包括例如銦。以此方式，散熱片(未示出)可能熱黏合至POL結構70而不使用將 散熱片銅焊或冶金直接黏合至POL結構70或無須在將POL結構黏合至散熱片之前平面化POL結構70。
在第23圖中，因此，提供在封裝結構之兩側上具有POL互連38的封裝結構70。由於其層壓程序，封裝結構70能完全地嵌入所有電子元件72、74、76且由此係表面黏著技術(SMT)相容的且提供雙面冷卻。雙面封裝結構70在電源模組中消除對額外的多層基板(如DBC基板等)之需求，其通常將用於電和熱功能，由此，基板完全地被POL通孔和用於在裝置後側之電連線和熱擴散的大銅墊取代。在封裝結構70中消除多層基板消除第二級組合程序，如焊接、底部填充(或二次成型)等。產生之封裝結構70由此具有極小形狀因子且被高度小型化。
因此，根據本發明之一實施例，一種封裝結構包括一第一介電層、附接至第一介電層的至少一半導體裝置、一或更多介電薄板，施加至第一介電層且在至少一半導體裝置附近以便將至少一半導體裝置嵌入於其中、及被形成至至少一半導體裝置的複數個通孔，複數個通孔係形成在第一介電層和一或更多介電薄板之至少一者中。封裝結構亦包括金屬互連，形成在複數個通孔中且在封裝結構的一或更多面外表面上以形成至至少一半導體裝置的電互連。第一介電層係由在一層壓程序期間不流動的一材料組成，且一或更多介電薄板之各者係由配置以當在層壓程序期間固化時熔化和流動的一可固化材料組成，使得一或更多介電薄板熔化和流動以填充存在於至少一半導體裝置 周圍的任何空氣間隙。
根據本發明之另一實施例，一種製造一半導體裝置封裝結構的方法包括藉由一黏著劑來將至少一半導體裝置附接至一第一介電層，形成配置以當固化時熔化和流動之一可固化材料的一或更多介電薄板，其中每個介電薄板係在一未固化或部分固化狀態下，在第一介電層上施加一或更多介電薄板以便位於至少一半導體裝置附近，在最後介電薄板的外表面上施加一銅箔，且固化一或更多介電薄板以使一或更多介電薄板熔化和流入存在於至少一半導體裝置周圍的任何空氣間隙中，且以便將至少一半導體裝置嵌入於其中，其中第一介電層在固化一或更多介電薄板期間不流動。方法也包括形成至至少一半導體裝置的複數個通孔，複數個通孔係形成在第一層和一或更多介電薄板之至少一者中，及在複數個通孔中且在封裝結構的一或更多外表面之至少一部分上方形成金屬互連，金屬互連形成至至少一半導體裝置的電互連。
根據本發明之又一實施例，一種POL封裝結構包括一第一介電層，具有一黏著劑塗覆於其至少一部分上、一或更多半導體裝置，藉由黏著劑來附接至第一介電層，其中在上方具有接觸墊的一或更多半導體裝置之各者的一表面係附接至第一介電層、及一介電封裝劑，位於一或更多半導體裝置附近的第一介電層上以便將一或更多半導體裝置嵌入於其中，介電封裝劑包含配置以當固化時熔化和流動的一或更多未固化或部分固化的介電薄板，以便 填充存在於一或更多半導體裝置周圍的任何空氣間隙。POL封裝結構也包括複數個通孔，被形成至一或更多半導體裝置且在第一介電層和介電封裝劑之至少一者中、及POL互連，形成在複數個通孔中以形成至一或更多半導體裝置的所有電和熱互連且在POL封裝結構中。第一介電質係配置以在固化一或更多介電薄板期間不流動。
儘管已僅結合有限數量的實施例來詳細說明本發明，但應容易地了解本發明並不限於上述所揭露之實施例。反而，能修改本發明以結合迄今未說明，但與本發明之精神和範圍相稱的一些變化、變更、替換或等效佈置。此外，儘管已說明本發明之各種實施例，但將了解本發明之態樣可能僅包括一些所述之實施例。因此，本發明不應被視為限於上述說明，而是僅限於所附之申請專利範圍的範圍。
10‧‧‧封裝結構
12‧‧‧半導體裝置
14‧‧‧第一介電層
16‧‧‧第二介電層
18‧‧‧前表面
20‧‧‧後表面
22‧‧‧黏著劑
24‧‧‧封裝劑
26‧‧‧介電薄板
28‧‧‧開口
30‧‧‧通孔
32‧‧‧前表面
34‧‧‧後表面
36‧‧‧通孔
38‧‧‧金屬互連

Claims (27)

  1. 一種封裝結構，包含：一第一介電層；至少一半導體裝置，附接至該第一介電層；一或更多介電薄板，施加至該第一介電層且在該至少一半導體裝置附近以便將該至少一半導體裝置嵌入於其中；複數個通孔，被形成至該至少一半導體裝置，該複數個通孔係形成在該第一介電層和該一或更多介電薄板之至少一者中；及金屬互連，形成在該複數個通孔中且在該封裝結構的一或更多面外表面上以形成至該至少一半導體裝置的電互連；其中該第一介電層係由在一層壓程序期間不流動的一材料組成；其中該一或更多介電薄板之各者係由配置以當在該層壓程序期間固化時熔化和流動的一可固化材料組成，使得該一或更多介電薄板熔化和流動以填充存在於該至少一半導體裝置周圍的任何空氣間隙。
  2. 如申請專利範圍第1項所述之封裝結構，更包含一介電網路，位於該至少一半導體裝置附近，其中該介電網路包括一或更多開口形成於其中以接收該至少一半導體裝置。
  3. 如申請專利範圍第2項所述之封裝結構，其中該 介電網路被建構為相較於該些介電薄板具有增加的剛性且在一層壓程序期間不流動，其中該介電網路係由一印刷電路板(PCB)核心材料、聚醯亞胺層、一陶瓷材料、及一複合介電材料的其中一者所組成。
  4. 如申請專利範圍第2項所述之封裝結構，其中該介電網路被建構為具有銅電路於其中。
  5. 如申請專利範圍第1項所述之封裝結構，其中該一或更多介電薄板係由在一未固化或部分固化狀態下的一預浸漬材料、一聚合物樹脂、或一黏著劑之其一者組成。
  6. 如申請專利範圍第1項所述之封裝結構，其中該至少一半導體裝置包含一功率半導體裝置。
  7. 如申請專利範圍第6項所述之封裝結構，其中該複數個通孔包含：形成穿過該第一介電層至該功率半導體裝置之一前表面的通孔；及形成穿過該一或更多介電薄板至該功率半導體裝置之一後表面的通孔；其中該些通孔當作在該封裝結構中的熱和電通孔；且其中金屬互連係形成在至該功率半導體裝置之該前和後表面的該些通孔之各者中。
  8. 如申請專利範圍第7項所述之封裝結構，其中該些金屬互連包含形成電連線的鍍銅功率覆蓋(POL)互連及在該封裝結構之該些面外表面上的一熱擴散銅墊，以便提供至該功率半導體裝置的電和熱互連。
  9. 如申請專利範圍第6項所述之封裝結構，更包含一熱介面材料(TIM)，塗覆在該封裝結構的一面外表面上和在該熱擴散銅墊上方，以便使該封裝結構能黏合至一散熱片。
  10. 如申請專利範圍第1項所述之封裝結構，更包含複數個通孔，延伸通過該第一介電層和該一或更多介電薄板，且其中金屬互連係形成在至該功率半導體裝置之該前和後表面的該些通孔之各者中。
  11. 如申請專利範圍第1項所述之封裝結構，更包含一第二介電層，位於該第一介電層對面之該封裝結構的一面外表面上，其中該一或更多介電薄板和該至少一半導體裝置係位於該第一介電層與該第二介電層之間，且其中該第二介電層係由在一層壓程序期間不流動的一材料組成。
  12. 如申請專利範圍第1項所述之封裝結構，更包含一銅箔，位於該第一介電層對面之該封裝結構的一面外表面上，其中該一或更多介電薄板和該至少一半導體裝置係位於該第一介電層與該銅箔之間。
  13. 如申請專利範圍第1項所述之封裝結構，更包含：一層一PCB預浸漬材料或一聚醯亞胺材料之其一者，附接至該封裝結構的該些面外表面，以便形成一多層封裝結構；複數個通孔，形成通過該層該PCB預浸漬材料或聚醯亞胺材料之各者；及 金屬互連，形成在該層該PCB預浸漬材料或聚醯亞胺材料中的該複數個通孔中。
  14. 一種製造一半導體裝置封裝結構的方法，包含：藉由一黏著劑來將至少一半導體裝置附接至一第一介電層；形成配置以當固化時熔化和流動之一可固化材料的一或更多介電薄板，其中該些介電薄板之各者係在一未固化或部分固化狀態下；在該第一介電層上施加該一或更多介電薄板以便位於該至少一半導體裝置附近；在最後該介電薄板的該外表面上施加一銅箔；固化該一或更多介電薄板以使該一或更多介電薄板熔化和流入存在於該至少一半導體裝置周圍的任何空氣間隙中，且以便將該至少一半導體裝置嵌入於其中，其中該第一介電層在固化該一或更多介電薄板期間不流動；形成至該至少一半導體裝置的複數個通孔，該複數個通孔係形成在該第一層和該一或更多介電薄板之至少一者中；及在該複數個通孔中且在該封裝結構的一或更多面外表面之至少一部分上方形成金屬互連，該些金屬互連形成至該至少一半導體裝置的電互連。
  15. 如申請專利範圍第14項所述之方法，更包含藉由一鑽孔程序或一削片程序之其一者來在該第一介電層中形成對準標記，其中將該至少一半導體裝置附接至該第一 介電層係由該些對準標記引導。
  16. 如申請專利範圍第14項所述之方法，其中該第一介電層包含一預金屬化介電層，其中該第一介電層具有被一剝離層分離的第一和第二銅層形成於其上；及其中該方法更包含在固化該一或更多介電薄板之後藉由該剝離層來移除該第二銅層。
  17. 如申請專利範圍第14項所述之方法，更包含：形成一介電網路結構以包括一或更多開口於其中來接收該至少一半導體裝置；及將該介電網路定位於該第一介電層上且在該至少一半導體裝置附近；其中該一或更多介電薄板係位於該至少一半導體裝置與該介電網路結構之間的任何間隙中的該第一介電層上。
  18. 如申請專利範圍第17項所述之方法，其中該介電網路係由一印刷電路板(PCB)核心材料、聚醯亞胺層、一陶瓷材料、及一複合介電材料之其一者組成。
  19. 如申請專利範圍第18項所述之方法，其中介電網路包含銅電路，其係連接至該些金屬互連。
  20. 如申請專利範圍第14項所述之方法，其中該一或更多介電薄板係由在一未固化或部分固化狀態下的一預浸漬材料、一聚合物樹脂、或一黏著劑之其一者組成。
  21. 如申請專利範圍第14項所述之方法，其中該至少一半導體裝置包含一功率半導體裝置；及其中形成該複數個通孔包含形成至該功率半導體裝置 之一後表面的通孔，其中金屬互連係形成在至該功率半導體裝置之該後表面的該些通孔之各者中。
  22. 如申請專利範圍第14項所述之方法，更包含：將一層一PCB預浸漬材料或一聚醯亞胺材料之任一者層壓至該封裝結構的一或更多該些外表面；在該層PCB核心材料或聚醯亞胺材料之各者中形成複數個通孔；及在該層PCB核心材料或聚醯亞胺材料的該複數個通孔中形成金屬互連。
  23. 如申請專利範圍第14項所述之方法，更包含形成通孔，延伸通過該第一介電層和該疊介電薄板；及其中形成金屬互連包含形成延伸通過該封裝結構的金屬互連，其中該些金屬互連係形成在該些通孔中且向外至該封裝結構的該些外表面上。
  24. 一種功率覆蓋(POL)封裝結構，包含：一第一介電層，具有一黏著劑塗覆於其至少一部分上；一或更多半導體裝置，藉由該黏著劑來附接至該第一介電層，其中在上方具有接觸墊的該一或更多半導體裝置之各者的一表面係附接至該第一介電層；一介電封裝劑，位於該一或更多半導體裝置附近的該第一介電層上以便將該一或更多半導體裝置嵌入於其中，該介電封裝劑包含配置以當固化時熔化和流動的一或更多未固化或部分固化的介電薄板，以便填充存在於該一或更 多半導體裝置周圍的任何空氣間隙；複數個通孔，被形成至該一或更多半導體裝置，該複數個通孔係形成在該第一介電層和該介電封裝劑之至少一者中；及POL互連，形成在該複數個通孔中以形成至該一或更多半導體裝置的所有電和熱互連且在該POL封裝結構中；其中該第一介電質係配置以在固化該一或更多介電薄板期間不流動。
  25. 如申請專利範圍第24項所述之功率模組封裝結構，更包含一介電網路，位於該第一介電層上且在該一或更多半導體裝置附近，其中該介電網路包括形成在裡面的開口以接收在裡面的該一或更多半導體裝置；其中該介電網路被建構為相較於該一或更多介電薄板具有增加的剛性且係由當受到一介電封裝劑固化程序時不熔化或流動的一材料組成。
  26. 如申請專利範圍第24項所述之功率模組封裝結構，其中該複數個介電薄板係由一預浸漬材料、一聚合物樹脂、或一黏著劑之其一者組成。
  27. 如申請專利範圍第24項所述之功率模組封裝結構，更包含一第二介電層，位於該第一介電層對面之該封裝結構的一面外表面上，且配置以在固化該一或更多介電薄板期間不流動，其中該介電封裝劑和該至少一半導體裝置係位於該第一介電層與該第二介電層之間。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI766540B (zh) * 2021-01-13 2022-06-01 矽品精密工業股份有限公司 電子封裝件及其製法
TWI785278B (zh) * 2018-10-19 2022-12-01 日月光半導體製造股份有限公司 封裝基板及其製造方法
TWI826537B (zh) * 2019-07-01 2023-12-21 南韓商三星電機股份有限公司 半導體封裝

Families Citing this family (69)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103857210A (zh) * 2012-11-28 2014-06-11 宏启胜精密电子(秦皇岛)有限公司 承载电路板、承载电路板的制作方法及封装结构
TWI474450B (zh) * 2013-09-27 2015-02-21 Subtron Technology Co Ltd 封裝載板及其製作方法
US9704781B2 (en) * 2013-11-19 2017-07-11 Micron Technology, Inc. Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods
KR102042137B1 (ko) 2014-05-30 2019-11-28 한국전자통신연구원 전자장치 및 그 제조 방법
JP2015228455A (ja) * 2014-06-02 2015-12-17 株式会社東芝 半導体装置及びその製造方法
US20150366081A1 (en) * 2014-06-15 2015-12-17 Unimicron Technology Corp. Manufacturing method for circuit structure embedded with electronic device
US10297572B2 (en) * 2014-10-06 2019-05-21 Mc10, Inc. Discrete flexible interconnects for modules of integrated circuits
JP6380548B2 (ja) * 2014-10-16 2018-08-29 株式会社村田製作所 複合デバイス
JP6048481B2 (ja) * 2014-11-27 2016-12-21 株式会社豊田自動織機 電子機器
KR20160084143A (ko) * 2015-01-05 2016-07-13 삼성전기주식회사 전자소자 내장기판 및 그 제조 방법
JP6430883B2 (ja) * 2015-04-10 2018-11-28 株式会社ジェイデバイス 半導体パッケージ及びその製造方法
US10535633B2 (en) 2015-07-02 2020-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package having die structures of different heights and method of forming same
US9806058B2 (en) * 2015-07-02 2017-10-31 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package having die structures of different heights and method of forming same
WO2017039275A1 (ko) 2015-08-31 2017-03-09 한양대학교 산학협력단 반도체 패키지 구조체, 및 그 제조 방법
KR101923659B1 (ko) * 2015-08-31 2019-02-22 삼성전자주식회사 반도체 패키지 구조체, 및 그 제조 방법
JP6862087B2 (ja) * 2015-12-11 2021-04-21 株式会社アムコー・テクノロジー・ジャパン 配線基板、配線基板を有する半導体パッケージ、およびその製造方法
EP3792960A3 (en) * 2016-04-11 2021-06-02 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Batch manufacture of component carriers
US10660208B2 (en) * 2016-07-13 2020-05-19 General Electric Company Embedded dry film battery module and method of manufacturing thereof
US10743422B2 (en) 2016-09-27 2020-08-11 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Embedding a component in a core on conductive foil
SG10201608773PA (en) * 2016-10-19 2018-05-30 Delta Electronics Intl Singapore Pte Ltd Method Of Packaging Semiconductor Device
US9966371B1 (en) 2016-11-04 2018-05-08 General Electric Company Electronics package having a multi-thickness conductor layer and method of manufacturing thereof
US10312194B2 (en) 2016-11-04 2019-06-04 General Electric Company Stacked electronics package and method of manufacturing thereof
US10700035B2 (en) 2016-11-04 2020-06-30 General Electric Company Stacked electronics package and method of manufacturing thereof
US9966361B1 (en) 2016-11-04 2018-05-08 General Electric Company Electronics package having a multi-thickness conductor layer and method of manufacturing thereof
US20180130732A1 (en) * 2016-11-04 2018-05-10 General Electric Company Electronics package having a multi-thickness conductor layer and method of manufacturing thereof
US9953917B1 (en) * 2016-12-12 2018-04-24 General Electric Company Electronics package with embedded through-connect and resistor structure and method of manufacturing thereof
US9953913B1 (en) 2016-12-12 2018-04-24 General Electric Company Electronics package with embedded through-connect structure and method of manufacturing thereof
CN106601701B (zh) * 2017-01-19 2023-03-28 贵州煜立电子科技有限公司 大功率二端表面引出脚电子元器件立体封装方法及结构
DE112017006956B4 (de) * 2017-01-30 2022-09-08 Mitsubishi Electric Corporation Verfahren zur Herstellung einer Leistungshalbleitervorrichtung und Leistungshalbleitervorrichtung
JP6809294B2 (ja) * 2017-03-02 2021-01-06 三菱電機株式会社 パワーモジュール
US11305488B2 (en) 2017-04-03 2022-04-19 Creative Ic3D Ltd. Process for producing three dimensional structures
US10541209B2 (en) 2017-08-03 2020-01-21 General Electric Company Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof
US10541153B2 (en) 2017-08-03 2020-01-21 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10804115B2 (en) 2017-08-03 2020-10-13 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10643919B2 (en) * 2017-11-08 2020-05-05 Samsung Electronics Co., Ltd. Fan-out semiconductor package
US11304313B2 (en) 2017-12-15 2022-04-12 Hewlett-Packard Development Company, L.P. Three-dimensional printing
WO2019171684A1 (ja) * 2018-03-07 2019-09-12 三菱電機株式会社 半導体装置及び電力変換装置
US10497648B2 (en) 2018-04-03 2019-12-03 General Electric Company Embedded electronics package with multi-thickness interconnect structure and method of making same
KR102164795B1 (ko) * 2018-09-06 2020-10-13 삼성전자주식회사 팬-아웃 반도체 패키지
JP6573415B1 (ja) * 2018-11-15 2019-09-11 有限会社アイピーシステムズ ビア配線形成用基板及びビア配線形成用基板の製造方法並びに半導体装置実装部品の製造方法
US20200161206A1 (en) * 2018-11-20 2020-05-21 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor manufacturing process
CN109727969A (zh) * 2018-12-29 2019-05-07 华进半导体封装先导技术研发中心有限公司 一种基板埋入式功率器件封装结构及其制造方法
US11342256B2 (en) 2019-01-24 2022-05-24 Applied Materials, Inc. Method of fine redistribution interconnect formation for advanced packaging applications
EP3716326A1 (en) * 2019-03-25 2020-09-30 Mitsubishi Electric R&D Centre Europe B.V. Electrically power assembly with thick electrically conductive layers
EP3716321A1 (en) * 2019-03-29 2020-09-30 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier with embedded semiconductor component and embedded highly conductive block which are mutually coupled
IT201900006740A1 (it) 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di strutturazione di substrati
IT201900006736A1 (it) * 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di fabbricazione di package
CN110600440B (zh) * 2019-05-13 2021-12-14 华为技术有限公司 一种埋入式封装结构及其制备方法、终端
US11931855B2 (en) 2019-06-17 2024-03-19 Applied Materials, Inc. Planarization methods for packaging substrates
CN112447777A (zh) * 2019-08-30 2021-03-05 旭景科技股份有限公司 集成电路封装结构及其形成方法
US11632860B2 (en) 2019-10-25 2023-04-18 Infineon Technologies Ag Power electronic assembly and method of producing thereof
EP3836208A1 (en) * 2019-11-19 2021-06-16 Mitsubishi Electric R & D Centre Europe B.V. Method and system for interconnecting a power device embedded in a substrate using conducting paste into cavities
US11862546B2 (en) 2019-11-27 2024-01-02 Applied Materials, Inc. Package core assembly and fabrication methods
CN111564414B (zh) * 2019-12-12 2021-09-24 奥特斯(中国)有限公司 部件承载件及制造部件承载件的方法
WO2021156958A1 (ja) * 2020-02-05 2021-08-12 太陽誘電株式会社 半導体モジュールおよび電源モジュール
EP3869923A1 (en) 2020-02-20 2021-08-25 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Cooling profile integration for embedded power systems
US11257790B2 (en) * 2020-03-10 2022-02-22 Applied Materials, Inc. High connectivity device stacking
US11454884B2 (en) 2020-04-15 2022-09-27 Applied Materials, Inc. Fluoropolymer stamp fabrication method
US11400545B2 (en) 2020-05-11 2022-08-02 Applied Materials, Inc. Laser ablation for package fabrication
US11398445B2 (en) 2020-05-29 2022-07-26 General Electric Company Mechanical punched via formation in electronics package and electronics package formed thereby
TWI753468B (zh) * 2020-06-24 2022-01-21 欣興電子股份有限公司 具散熱結構之基板結構及其製造方法
US11232951B1 (en) 2020-07-14 2022-01-25 Applied Materials, Inc. Method and apparatus for laser drilling blind vias
US11342248B2 (en) * 2020-07-14 2022-05-24 Gan Systems Inc. Embedded die packaging for power semiconductor devices
US11676832B2 (en) 2020-07-24 2023-06-13 Applied Materials, Inc. Laser ablation system for package fabrication
CN217035634U (zh) * 2020-10-24 2022-07-22 Pep创新私人有限公司 芯片封装结构及芯片结构
US11521937B2 (en) 2020-11-16 2022-12-06 Applied Materials, Inc. Package structures with built-in EMI shielding
US11404318B2 (en) 2020-11-20 2022-08-02 Applied Materials, Inc. Methods of forming through-silicon vias in substrates for advanced packaging
US11705365B2 (en) 2021-05-18 2023-07-18 Applied Materials, Inc. Methods of micro-via formation for advanced packaging
US11950394B2 (en) 2021-10-12 2024-04-02 Ge Aviation Systems Llc Liquid-cooled assembly and method

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5353498A (en) 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US6306680B1 (en) 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
US6232151B1 (en) 1999-11-01 2001-05-15 General Electric Company Power electronic module packaging
JP3815239B2 (ja) * 2001-03-13 2006-08-30 日本電気株式会社 半導体素子の実装構造及びプリント配線基板
US6706563B2 (en) * 2002-04-10 2004-03-16 St Assembly Test Services Pte Ltd Heat spreader interconnect methodology for thermally enhanced PBGA packages
WO2004014114A1 (ja) * 2002-07-31 2004-02-12 Sony Corporation 素子内蔵基板の製造方法および素子内蔵基板、ならびに、プリント配線板の製造方法およびプリント配線板
EP1589797A3 (en) * 2004-04-19 2008-07-30 Matsushita Electric Industrial Co., Ltd. Manufacturing method of laminated substrate, and manufacturing apparatus of semiconductor device for module and laminated substrate for use therein
JP4800606B2 (ja) * 2004-11-19 2011-10-26 Ｏｋｉセミコンダクタ株式会社 素子内蔵基板の製造方法
US7518236B2 (en) 2005-10-26 2009-04-14 General Electric Company Power circuit package and fabrication method
US20080190748A1 (en) 2007-02-13 2008-08-14 Stephen Daley Arthur Power overlay structure for mems devices and method for making power overlay structure for mems devices
DE102007009521B4 (de) * 2007-02-27 2011-12-15 Infineon Technologies Ag Bauteil und Verfahren zu dessen Herstellung
JP5042762B2 (ja) * 2007-09-27 2012-10-03 株式会社テラミクロス 半導体装置
WO2009020240A2 (en) * 2007-08-08 2009-02-12 Casio Computer Co., Ltd. Semiconductor device and method for manufacturing the same
US7935893B2 (en) * 2008-02-14 2011-05-03 Ibiden Co., Ltd. Method of manufacturing printed wiring board with built-in electronic component
US8507320B2 (en) * 2008-03-18 2013-08-13 Infineon Technologies Ag Electronic device including a carrier and a semiconductor chip attached to the carrier and manufacturing thereof
TWI443789B (zh) * 2008-07-04 2014-07-01 Unimicron Technology Corp 嵌埋有半導體晶片之電路板及其製法
KR101486420B1 (ko) * 2008-07-25 2015-01-26 삼성전자주식회사 칩 패키지, 이를 이용한 적층형 패키지 및 그 제조 방법
TWI417993B (zh) * 2009-02-04 2013-12-01 Unimicron Technology Corp 具凹穴結構的封裝基板、半導體封裝體及其製作方法
US8358000B2 (en) 2009-03-13 2013-01-22 General Electric Company Double side cooled power module with power overlay
JP2010251688A (ja) 2009-03-25 2010-11-04 Nec Toppan Circuit Solutions Inc 部品内蔵印刷配線板及びその製造方法
JPWO2011016555A1 (ja) * 2009-08-07 2013-01-17 日本電気株式会社 半導体装置とその製造方法
US8120158B2 (en) * 2009-11-10 2012-02-21 Infineon Technologies Ag Laminate electronic device
US8822281B2 (en) 2010-02-23 2014-09-02 Stats Chippac, Ltd. Semiconductor device and method of forming TMV and TSV in WLCSP using same carrier
WO2011114774A1 (ja) * 2010-03-18 2011-09-22 日本電気株式会社 半導体素子内蔵基板およびその製造方法
JP2011222555A (ja) * 2010-04-02 2011-11-04 Denso Corp 半導体チップ内蔵配線基板の製造方法
US8531027B2 (en) 2010-04-30 2013-09-10 General Electric Company Press-pack module with power overlay interconnection
US8310040B2 (en) 2010-12-08 2012-11-13 General Electric Company Semiconductor device package having high breakdown voltage and low parasitic inductance and method of manufacturing thereof
US8114712B1 (en) 2010-12-22 2012-02-14 General Electric Company Method for fabricating a semiconductor device package
JP5349532B2 (ja) * 2011-05-20 2013-11-20 パナソニック株式会社 部品内蔵モジュールの製造方法
JP5843539B2 (ja) * 2011-09-16 2016-01-13 三菱電機株式会社 半導体装置及び当該半導体装置の製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI785278B (zh) * 2018-10-19 2022-12-01 日月光半導體製造股份有限公司 封裝基板及其製造方法
TWI826537B (zh) * 2019-07-01 2023-12-21 南韓商三星電機股份有限公司 半導體封裝
TWI766540B (zh) * 2021-01-13 2022-06-01 矽品精密工業股份有限公司 電子封裝件及其製法

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