CN104681520A - 嵌入式半导体装置封装及其制造方法 - Google Patents

嵌入式半导体装置封装及其制造方法 Download PDF

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Publication number
CN104681520A
CN104681520A CN201410848599.4A CN201410848599A CN104681520A CN 104681520 A CN104681520 A CN 104681520A CN 201410848599 A CN201410848599 A CN 201410848599A CN 104681520 A CN104681520 A CN 104681520A
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China
Prior art keywords
semiconductor device
encapsulating structure
dielectric
sheet material
dielectric layer
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CN201410848599.4A
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English (en)
Inventor
S·S·乔罕
P·A·麦康奈利
A·V·高达
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General Electric Co
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General Electric Co
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Publication of CN104681520A publication Critical patent/CN104681520A/zh
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Abstract

本发明涉及嵌入式半导体装置封装及其制造方法。一种封装结构包括介电层，至少一个附接到介电层的半导体装置，施加到介电层且在半导体装置周围以使半导体装置嵌入其中的一个或多个介电片材，和多个形成到半导体装置的通路，多个通路形成在介电层和一个或多个介电片材中的至少一者。封装结构还包括形成在通路中且在封装结构的一个或多个朝外表面上的金属互连件，以形成到半导体装置的电互连。介电层由层压工艺期间不流动的材料组成且一个或多个介电片材的每一个由可固化材料组成，固化材料被配置成在层压工艺期间当固化时熔化并流动，从而填充半导体装置周围的任何空气间隙。

Description

嵌入式半导体装置封装及其制造方法
技术领域
本发明的实施例通常涉及封装半导体装置的结构和方法，更特别地，涉及具有形成封装中的所有电互连和热互连的功率覆盖(POL)互连件的嵌入式封装结构。
表面安装技术是一种构造电子电路的方法，其中表面安装构件或封装被直接安装在印刷电路板(PCB)或其它类似外部电路的表面。工业中，表面安装技术已经取代了使用引线穿过电路板中的孔而匹配构件的穿孔技术构造方法。
对于表面安装半导体装置(或多芯片模块)的一个普遍的技术问题是提供封装结构，其中装置/模块被密封在嵌入组合物内。封装制造工艺以通过粘接的方式在介电层上定位一个或多个半导体装置开始，介电层覆盖每一个半导体装置的活性侧。然后，金属互连件被电镀在介电层上，以形成与半导体装置的直接金属连接。互连可以通过额外的层压再分布层分路，如果期望，提供输入/输出系统，以实现表面安装封装件在PCB或外部电路上。嵌入组合物被施加在半导体装置周围以密封其中的半导体装置。
在一个实施例中，半导体装置是高压功率半导体装置，功率半导体装置能通过功率覆盖(POL)封装的方式和互连系统被表面安装到外部电路上，POL封装也提供通过装置移除热量并保护装置免受外部环境影响。标准的POL封装制造工艺典型地以通过粘结剂以及钻出穿过电介质到装置的通孔来将一个或多个半导体装置定位在介电层上开始。然后金属互连件(例如，铜互连件)电镀在介电层上并进入通路以形成到半导体装置的直接金属连接，从而形成子模块。金属互连件可以是以低形貌、平坦互连结构，其提供为通向或来自半导体装置的输入/输出(I/O)系统的形成。然后，POL子模块使用电和热连接的焊接互连被焊接到陶瓷衬底(如带DBC的氧化铝，带AMB Cu的AIN等)。然后，介电层和陶瓷衬底之间的半导体装置周围的间隙利用介电有机材料使用毛细流动(毛细底层填充)、非流动底层填充或注塑成型(模塑组合物)以形成POL封装。
关于上面陈述的使半导体装置、模块和/或功率装置嵌入的封装制造工艺，公认的是，有许多缺点与此相关。例如，当要求湿度敏感性水平(MSL)条件时，通常使用的密封和嵌入组合物具有有限的可靠性，由于它们的不好的断裂韧性和高的湿气吸收。另外，通常使用的密封/嵌入组合物可能采购昂贵且应用缓慢而耗时。
此外，特别地关于封装功率装置/模块，通常负责电和热连接POL子模块到陶瓷衬底的焊接操作可能费钱并费时，由焊接引起的额外的温度的剧增也严重地影响了模块的可靠性。更进一步，由于陶瓷衬底的尺寸/厚度，在POL封装位置陶瓷衬底的包含物限制了POL封装尺寸/厚度可能的减少(即小型化)。因此，在增加电、热和机械性能时期望使模块小型化以减小系统重量、花费和尺寸，这被目前的POL封装结构所限制。
因此，期望提供能与表面安装兼容的半导体装置封装结构，并具有非常小的厚度。更进一步期望这样的封装结构以降低的成本制造但增加系统水平性能。
发明内容
本发明的实施例通过提供具有在封装中形成所有电和热互连的POL互连件的POL封装结构来克服上述缺陷。
根据本发明的一个方面，封装结构包括第一介电层，附接于第一介电层的至少一个半导体装置，施加于第一介电层且在至少一个半导体装置周围以使至少一个半导体装置嵌入其中的一个或多个介电片材，以及形成在至少一个半导体装置的多个通路，多个通路形成在第一介电层和一个或多个介电片材中的至少一者。封装结构还包括形成在多个通路中和在封装结构的一个或多个朝外表面的金属互连件，以形成到至少一个半导体装置的电互联。第一介电层由在层压工艺期间不流动的材料组成，并且一个或多个介电片材中的每一个由可固化材料组成，该材料被构造成在层压工艺期间当固化时熔化并流动，使得一个或多个介电片材熔化并流动以填充于至少一个半导体装置周围的任何空气间隙。
根据本发明的另一个方面，制造半导体装置封装结构的方法包括，通过粘接剂附接至少一个半导体装置到第一介电层，形成一个或多个构造为当固化时熔化并流动的可固化材料的介电片材，其中介电片材的每一个在未固化或部分固化状态，施加一个或多个介电片材在第一介电层上，以被定位在至少一个半导体装置周围，施加铜箔在最后介电片材的外表面上，和固化一个或多个介电片材，以使得一个或多个介电片材熔化并流入存在于至少一个半导体装置周围的任何空气间隙中，并且使得至少一个半导体装置嵌入其中，其中第一介电层在一个或多个介电片材固化期间不流动。方法还包括形成多个通路到至少一个半导体装置，多个通路形成在第一层和一个或多个介电片材中的至少一者，和在多个通路中且在封装结构的一个或多个外表面的至少一部分上形成金属互连件，金属互连形成到至少一个半导体装置的电互连。
根据本发明的又一个方面，POL封装结构包括第一介电层，第一介电层具有施加到其至少一部分上的粘接剂，通过粘接剂附接到第一介电层的一个或多个半导体装置，其中一个或多个半导体装置的每一个的表面具有附接到第一介电层的接触垫，和被定位在一个或多个半导体装置周围的第一介电层上的介电密封剂，使得一个或多个半导体装置被嵌入其中，介电密封剂包括一个或多个未固化或部分固化的介电片材，其被构造成在固化时熔化并流动从而填充存在于一个或多个半导体装置周围的任何空气间隙。POL封装结构还包括形成在一个或多个半导体装置和在第一介电层和介电密封剂中的至少一者的多个通路，以及POL互连件，其形成在多个通路中以形成到一个或多个半导体装置和在POL封装结构中的所有电和热互连。第一电介质被构造成在一个或多个介电片材固化期间不流动。
方案1：一种封装结构，包括：
第一介电层；
附接到第一介电层的至少一个半导体装置；
一个或多个介电片材，其施加到第一介电层上和至少一个半导体装置周围，使得至少一个半导体装置嵌入其中；
形成到至少一个半导体装置的多个通路，多个通路形成在第一介电层和一个或多个介电片材中的至少一者；以及
金属互连件，其形成在多个通路中和在封装结构的一个或多个朝外表面上，以形成到至少一个半导体装置的电互连；
其中，第一介电层由在层压工艺期间不流动的材料组成；
其中，一个或多个介电片材中的每一个由可固化材料组成，该可固化材料被配置成在层压工艺期间当固化时熔化并流动，使得一个或多个介电片材熔化并流动以填充存在于至少一个半导体装置周围的任何空气间隙。
方案2：根据方案1的封装结构，其中，还包括设置在至少一个半导体装置周围的介电腹板，其中介电腹板包括一个或多个形成在其中以接收至少一个半导体装置的开口。
方案3：根据方案2的封装结构，其中，介电腹板相比于介电片材被构造为具有增加的刚性且在层压工艺期间不流动，其中介电腹板由印刷电路板(PCB)芯材、聚酰亚胺层、陶瓷材料和复合介电材料中的一者组成。
方案4：根据方案2的封装结构，其中，介电腹板被构造为其中具有铜电路。
方案5：根据方案1的封装结构，其中，一个或多个介电片材由处于未固化或部分固化状态的预浸材料、聚合树脂、或粘接剂中的一者组成。
方案6：根据方案1的封装结构，其中，至少一个半导体装置包括功率半导体装置。
方案7：根据方案6的封装结构，其中，多个通路包括：
穿过第一介电层到达功率半导体装置的正面而形成的通路；和
穿过一个或多个介电片材到达功率半导体装置的背面而形成的通路；
其中通路功能作为封装结构中的电和热通路；以及
其中金属互连件形成在通路的每一个中，并到达功率半导体装置的正面和背面。
方案8：根据方案7的封装结构，其中，金属互连件包括形成电连接的镀铜功率覆盖(POL)互连件和在封装结构的朝外表面上的热扩散铜垫，从而提供到功率半导体装置的电和热互连。
方案9：根据方案6的封装结构，其中，还包括施加在封装结构的朝外表面上和热扩散铜垫上的热界面材料(TIM)，从而使得封装结构结合到散热部。
方案10：根据方案1的封装结构，其中，还包括多个延伸穿过第一介电层和一个或多个介电片材的贯通路，且其中金属互连件形成在贯通路的每一个中，并到达功率半导体装置的正面和背面。
方案11：根据方案1的封装结构，其中，还包括与第一介电层相对的封装结构的朝外表面上的第二介电层，其中一个或多个介电片材和至少一个半导体装置定位在第一介电层和第二介电层之间，且其中第二介电层由层压工艺期间不流动的材料组成。
方案12：根据方案1的封装结构，其中，还包括定位在与第一介电层相对的封装结构的朝外表面上的铜箔，其中一个或多个介电片材和至少一个半导体装置定位在第一介电层和铜箔之间。
方案13：根据方案1的封装结构，其中，还包括：
PCB预浸材料或聚酰亚胺材料中的一者的层，其附接到封装结构的朝外表面，从而形成多层封装结构；
穿过PCB预浸材料或聚酰亚胺材料的层的每一个而形成的多个通路；和
形成在PCB预浸材料或聚酰亚胺材料的层中的多个通路中的金属互连件。
方案14：一种制造半导体装置封装结构的方法，包括：
通过粘接剂将至少一个半导体装置附接到第一介电层；
形成一个或多个配置成在固化时熔化并流动的可固化材料的介电片材，其中每一个介电片材处于未固化或部分固化的状态；
将一个或多个介电片材施加在第一介电层上以被定位在至少一个半导体装置周围；
将铜箔施加在最后介电片材的外表面上；
固化一个或多个介电片材以导致一个或多个介电片材熔化并流入存在于至少一个半导体装置周围的任何空气间隙，且使得至少一个半导体装置被嵌入其中，其中第一介电层在一个或多个介电片材的固化期间不流动；
形成多个通路到至少一个半导体装置，多个通路被形成在第一层和一个或多个介电片材中的至少一者；和
在多个通路中和封装结构的一个或多个外表面的至少一部分上形成金属互连件，金属互连件形成到至少一个半导体装置的电互连。
方案15：根据方案14的方法，其中，还包括通过钻孔工艺或切割工艺的一个在第一介电层中形成对准标记，其中至少一个半导体装置到第一介电层的附接由对准标记引导。
方案16：根据方案14的方法，其中，第一介电层包括预金属化的介电层，其中第一介电层具有形成在其上的被释放层分开的第一和第二铜层；和
其中该方法还包括在一个或多个介电片材固化后以释放层的方式移除第二铜层。
方案17：根据方案14的方法，其中，还包括：
形成介电腹板结构以在其中包括一个或多个开口以接收至少一个半导体装置；和
将介电腹板定位在第一介电层上和至少一个半导体装置周围；
其中一个或多个介电片材定位在第一介电层上在至少一个半导体装置和介电腹板结构之间的任何间隙中。
方案18：根据方案17的方法，其中，介电腹板由印刷电路板(PCB)芯材、聚酰亚胺层、陶瓷材料和复合介电材料中的一者组成。
方案19：根据方案18的方法，其中，介电腹板包括连接到金属互连件的铜电路。
方案20：根据方案14的方法，其中，一个或多个介电片材由在未固化或部分固化状态下的预浸材料、聚酰亚胺树脂或粘接剂之一组成。
方案21：根据方案14的方法，其中，至少一个半导体装置包括功率半导体装置；和
其中，形成多个通路包括形成通路到功率半导体装置的背面，其中金属互连件形成在到达功率半导体装置的背面的每一个通路中。
方案22：根据方案14的方法，其中，还包括：
将PCB预浸材料或聚酰亚胺材料之一的层层压到封装结构的一个或多个外表面；
在每一个PCB芯材或聚酰亚胺材料的层中形成多个通路；和
在PCB芯材或聚酰亚胺材料的层的多个通路中形成金属互连件。
方案23：根据方案14的方法，其中，还包括形成延伸穿过第一介电层和介电片材堆叠的贯通路；和
其中形成金属互连件包括形成延伸穿过封装结构的金属互连件，其中金属互连件形成在贯通路中并延伸出封装结构的外表面。
方案24：一种功率覆盖(POL)封装结构，包括：
第一介电层，其具有施加在其至少一部分上的粘接剂；
一个或多个半导体装置，其通过粘接剂附接到第一介电层，其中一个或多个半导体装置的每一个的表面具有附接到第一介电层的接触垫；
介电密封剂，其定位在第一介电层上并在一个或多个半导体装置周围，使得一个或多个半导体装置被嵌入其中，介电密封剂包括一个或多个未固化或部分固化的介电片材，其被配置成在固化时熔化并流动从而填充存在于一个或多个半导体装置周围的任何空气间隙；
形成到一个或多个半导体装置的多个通路，多个通路形成在第一介电层和介电密封剂中的至少一者；和
POL互连件，其形成在多个通路中以形成到一个或多个半导体装置和在POL封装结构中的所有电和热互连；
其中第一电介质被配置成在一个或多个介电片材固化期间不流动。
方案25：根据方案24的功率模块封装结构，其中，还包括定位在第一介电层上和一个或多个半导体装置周围的介电腹板，其中介电腹板包括形成在其中以接收其中的一个或多个半导体装置的开口；
其中介电腹板被构造成相比一个或多个介电片材具有增加的刚性，并且由在受到介电密封剂固化工艺期间不熔化或流动的材料组成。
方案26：根据方案24的功率模块封装结构，其中，多个介电片材由预浸材料、聚酰亚胺树脂或粘接剂中的一者组成。
方案27：根据方案24的功率模块封装结构，其中，还包括第二介电层，其定位在与第一介电层相对的封装结构的朝外表面上且被配置成在一个或多个介电片材的固化期间不流动，其中介电密封剂和至少一个半导体装置定位在第一介电层和第二介电层之间。
根据提供为与附图结合的本发明的优选实施例的以下详细描述，这些和其它的优点和特征将会更容易理解。
附图简要说明
附图示出了现在实施用于执行本发明的实施例。
在附图中：
附图1是根据本发明实施例的功率覆盖(POL)封装结构的截面侧视图。
附图2-9是根据本发明的实施例的POL封装结构在制造/构建工艺的各个阶段的截面侧视图。
附图10-16是根据本发明的实施例的POL结构在另一个制造/构建工艺的各个阶段的截面侧视图。
附图17是通过附图2-9或附图10-16的制造/构建工艺形成的POL封装结构的截面侧视图，示出根据本发明的另一个实施例而在POL封装结构上执行的额外制造/构建步骤。
附图18是附图17的POL封装结构的截面侧视图，示出根据本发明的另一个实施例而在POL封装结构上执行的额外制造/构建步骤。
附图19是根据本发明的另一实施例的POL封装结构的截面侧视图；
附图20是根据本发明的另一实施例的POL封装结构的截面侧视图；
附图21是根据本发明的另一实施例的POL封装结构的截面侧视图。
附图22是根据本发明的另一实施例的POL封装结构的截面侧视图；
附图23是根据本发明的另一实施例的POL封装结构的截面侧视图；
具体实施方式
本发明的实施例供提供具有功率覆盖(POL)互连件的嵌入式功率模块封装结构，POL互连件形成到在功率模块中的半导体装置的所有电和热互连，以及形成这种封装结构的方法。
参考图1示出了根据本发明的实施例的POL封装和互连结构10。封装结构10包括半导体装置12，半导体装置12可以是通常被描述为“功率装置”或“非功率装置”两者之一的形式，且因此例如可以是管芯、二极管、MOSFET、专用集成电路(ASIC)或处理器的形式。虽然在附图1中示出单个半导体装置12，但是应认识到额外的半导体装置或电子构件可包括在POL结构10中，这将要在下面的关于本发明的另一个实施例中描述。半导体装置12被封装在封装结构10内，使得直接金属互连件形成到装置的所有电和/或热互连。
如附图1所示，根据示例性实施例，封装结构10包括在封装结构10的相对侧的每一个上的介电层(半导体装置12位于其中)，层通常指的是第一介电层14和第二介电层16。介电层14、16以层压件或膜的形式提供，并且被选择以在使用和框架处理期间向通路提供机械和温度稳定性的材料形成，以及为通路形成和POL处理提供合适的介电特性和电压击穿强度和加工性，因此介电层14、16可以被称为“POL电介质”。另外，形成介电层14、16的材料被选择以在封装结构10上执行层压工艺期间保持稳定。即，介电层14、16由合适的材料形成，以使它们被配置成在封装结构10上执行层压工艺期间不流动。因此，根据本发明的实施例，介电层14、16可以由多个介电材料中的一个形成，例如聚四氟乙烯(PTFE)、聚枫材料(例如)或另一种聚合物膜，如液晶聚合物(LCP)或聚酰亚胺材料。为了清晰起见以及将介电层14、16区别于封装结构10中的其他介电材料，介电层14、16此后被称为聚酰亚胺层14、16，然而这个词语并不意味着将层14、16限制为由特定介电材料形成。
如图1所示，聚酰亚胺层14、16被提供在封装结构10的两侧，即在封装结构的正面和背面18、20上，从而提供在两表面上形成通路和图案化金属互连件的能力，下面将进一步解释。半导体装置12位于聚酰亚胺层14、16之间，装置12通过粘接剂22被附接到聚酰亚胺层14。封装结构10还包括提供在聚酰亚胺层14、16之间的介电密封剂24(即POL密封剂)。密封剂24用于填充封装结构10内的可能存在于半导体装置12周围和聚酰亚胺层14、16之间的空的间隙，并根据一个实施例，密封剂24可将聚酰亚胺层14粘合到装置12，且因此它可以是一种或多种材料形成的。
密封剂24由一个或多个以“膜”或“面板”或“片材”形式提供的介电层26组成，以使，如果需要，多个介电片材26可以彼此堆叠以达到填充半导体装置12和聚酰亚胺层14、16之间的区域的所需的期望高度/厚度。介电片材26由有机材料形成，例如预浸材料(prepregmaterial)、印刷电路板芯材、聚合树脂或其它合适的粘接剂，例如它们是未固化的或部分固化的(即B-级)，从而它们能以它们的预固化膜形式被容易地堆叠。根据本发明的一个实施例，介电片材26包括形成在其中的以在其中接收半导体装置12和适应片材26周围的定位的开口/切口28。可选择地，认识到介电片材26的节段可以位于半导体装置12的周围。
为了填充封装结构10内的空的间隙，介电片材26经受使介电片材26“熔化”和流动的层压工艺(特别在真空环境中，在升温和机械压力之下)。因此介电片材26失去它们的膜形式并流动以填充半导体装置12周围和聚酰亚胺层14、16之间的任何空的空气间隙，这样提供的介电密封剂24总体上保护半导体装置12而免受周围环境影响。
如图1所示，多个通路30穿过聚酰亚胺层14到达半导体装置12的正面32而形成。在一个实施例中，半导体装置12是功率装置，如在图1，通路30也形成为到达半导体装置12的背面34，以满足电和热的需求(例如制作需要的电连接并从功率半导体装置移除热量)。当正面和背面之间需要电连接时，贯通路36也穿过聚酰亚胺层14、16和介电片材26而形成。随后金属互连件38形成在封装结构10中，以在其中提供电和热连接/路径，互连件38分别形成在通路30、36中，并伸出到聚酰亚胺层14、16的相对正面和背面18、20的外面，使得封装结构10的正面和背面18、20都包括形成在其上的互连件。根据本发明的实施例，金属互连件38包括“POL互连件”，其形成为坚固的电镀铜互连件，形成装置12中的直接电互连。依赖在装置上的金属化，在一些实施例中，溅射黏附层(钛，铬等)与铜可被镀层在其上的溅射铜晶种层一起提供。如图1所示，金属互连件38被图案化并蚀刻成期望的形状，从而为封装结构10提供电和热连接。根据一个实施例，例如，金属互连件38被图案化并被蚀刻以在封装结构10的背侧上(即铜垫)提供大区域热和电连接，使得封装结构到散热部的附接成为可能。
因此提供在结构的两侧上具有金属互连件38的封装结构10。由于其层压工艺，封装结构10能完全使半导体装置12嵌入并因此与表面安装技术(SMT)是兼容的，且还可以在其上提供其它电子件的堆叠。在一个实施例中，半导体装置12是功率装置，封装结构10进一步提供双侧冷却并且不需要对典型地用于电和热功能性的额外的多层衬底(像DBC衬底等)，因为这种衬底完全由在装置背侧热扩散的热通路和大的铜垫替代。这样在封装中的多层衬底的排除，在封装结构10中的功率装置排除了第二级组装工艺，像焊接、底部填充(或上部模塑)等，并使得封装结构10具有非常小的形式因数，是高度小型化的。
现在参考图2-9，根据本发明的实施例，提供了制造POL封装结构技术的工艺步骤的细节图。在附图2-9中描述的技术被示出并描述了制造如附图1示出的封装结构10(即，仅包括单个半导体装置)，但是公认的是描述的工艺应用于制造使多种结构的多芯片模块嵌入的封装结构。
参考图2，封装结构10的构建工艺从提供预金属化介电层开始。根据本发明的实施例，预金属介电层包括由多个介电材料之一形成的介电层压件或膜14，诸如聚四氟乙烯(PTFE)、聚砜材料(如)或另一种聚合物膜，如液晶聚合物(LCP)或聚酰亚胺材料，且其后面被称为聚酰亚胺膜14。铜层40被金属化在聚酰亚胺膜14的一个表面上，铜层40具有施加在它的背面上的释放层42，释放层42将额外的铜载体层44附到铜层40，以在封装结构10的构建工艺期间提供稳定性。释放层42允许在随后的制造工艺步骤中铜载体层44随后的移除。
如图2进一步所示，对准标记46被激光钻孔，穿过聚酰亚胺膜14，并进入铜层40，以提供半导体装置(如管芯、MOSFET等)12在预金属化介电层上的定位。如图3所示，粘接剂22被施加于聚酰亚胺膜14，以确保半导体装置12在其上，诸如通过丝网印刷的应用、滴涂或旋涂应用。根据本发明的一个实施例，粘接剂22可以仅在半导体装置12定位的位置处被施加在聚酰亚胺膜14上。可选地，粘接剂22可以施加在整个聚酰亚胺膜14上。基于粘接剂22沉积在聚酰亚胺膜14上，然后半导体装置12使用作为定位引导件的对准标记46定位在聚酰亚胺膜14上。然后通过固化粘接剂22而使半导体装置12固定在聚酰亚胺膜14上。
参考图4，基于半导体装置12在预金属化介电层14上的定位和固定，一个或多个介电片材26被准备并随后定位在预金属化介电层14上和半导体装置12周围，应用的介电片材26的数量基于半导体装置12的厚度决定。如果需要多个介电片材26，为了密封半导体装置12，片材以堆叠布置来施加。介电片材26由有机材料形成，如预浸材料、PCB芯材、聚合树脂或以预固化膜的形式的其它合适的粘接剂(以使它们能被容易堆叠)，且后面通常被称为预浸片材26。在准备预浸片材26中，提供预浸材料的膜或面板，且在其中形成对应于半导体装置12位置的开口28(即切口)。准备的预浸片材26(其中形成有开口28)然后彼此堆叠到期望的高度和厚度，使得它们完全围绕半导体装置12。一旦堆叠预浸片材26，背侧介电层16(如聚酰亚胺层)被施加在预浸片材26的堆叠上，背侧聚酰亚胺膜16包括预金属化层。根据本发明的一个实施例，背侧聚酰亚胺膜16可被预金属化，以便具有为提供增加的热功能性为目的的增加厚度的铜层48。
在制造工艺的下个步骤，如图5所示，为了引起预浸片材26的熔化和流动而执行层压工艺。层压工艺可在真空环境中、在升温和机械压力或气压下执行，从而引起预浸片材26熔化，并因此失去它们的膜形式。一旦熔化，在聚酰亚胺膜14、16之间提供的预浸材料流动以填充半导体装置12周围和在封装结构内的空的空气间隙，并且因此可被描述成形成密封剂24。基于封装结构10的冷却，预浸材料被完全固化，并使半导体装置12周围变得坚硬以密封装置。
如图6所示，一旦层压工艺完成，铜载体层44通过释放层42从铜层40上移除。在聚酰亚胺膜14上留下的铜层40然后被清洁而为随后的通路形成和金属化步骤做准备。穿过聚酰亚胺膜14和背侧聚酰亚胺膜16(即聚酰亚胺膜和铜层)的多个通路30的形成在附图7中示出。根据本发明的实施例，通路30可通过激光烧灼或激光钻孔工艺、等离子蚀刻、光照限定、或机械钻孔工艺形成。通路30形成直到半导体装置12上的接触垫50(使用对准钻孔看到冲模)，以形成到它的电连接，在实施例中，半导体装置12是功率装置(如在此的情况)，通路30也形成到半导体装置12的背侧34。下到半导体装置12上的接触垫50的通路30穿过聚酰亚胺膜14形成，且因此这些通路30的特征和精度能被控制在紧密约束之内。根据一个实施例，由于它们的形成穿过预浸密封剂24，到半导体装置12的背侧34的通路30是粗糙的特征，并不能用与到接触垫50的通路30相同的精度形成(即限制了行距和孔径)，预浸密封剂24具有纤维或其它包含物，尽管公认的是在一些实施例中，到装置12的背侧34的通路30可仅仅穿过聚酰亚胺膜16而形成。除了下到半导体装置12形成的通路30，贯通路36被钻通而穿过整个构建(即穿过聚酰亚胺膜14、16和预浸密封剂24)。
一旦通路30、36形成下到半导体装置12并穿过封装构建，且在完成通路的清洁(诸如通过反应离子蚀刻(RIE)desoot工艺)时，如果期望，如图8所示，然后金属互连件38被形成在封装结构中。根据一个实施例，金属互连件38被形成为POL互连件，POL互连件通过无电镀层或电镀形成，尽管公认的是其它金属沉积方法(如溅射)也可以使用。例如，钛或钯粘接层和铜晶种层可以首先通过溅射或无电镀层工艺被形成在通路30、36中，随后在封装结构的正面和背面18、20上都通过电镀工艺填充通路和增加铜的厚度(即“构建”)到期望的水平。如图9所示，然后接着在施加的铜上依次执行图案化和蚀刻，以形成具有期望形状的POL互连件38。虽然应用连续铜层并随后为形成互连件38的连续铜层的图案化和蚀刻被示出在图8和9中，但公认的是，可代替为执行互连件38的图案化和镀层经由半增加镀层工艺以形成互连件38。
因此，形成了在结构的两侧都提供互连的完整封装结构10。封装结构10是SMT兼容的且提供MSL性能、机械强度、双侧冷却和低材料成本，全部具有非常小的形式因数，从而允许产生高度小型化的封装结构10。
现在参考图10-16，根据本发明的另一个实施例，提供制造POL封装结构的另一种技术的工艺步骤的细节图。为了制造图1中所示的封装结构10(即包括仅单个半导体装置)，图2-9描述的技术再次示出且描述，然而，再一次认为，所描述的工艺可应用于制造嵌入各种配置的多芯片模块的封装结构。
参考图10，封装结构的构建工艺以介电层14的提供开始，诸如聚酰亚胺层压件或膜。尽管没有示出，聚酰亚胺膜14可定位在框架或面板结构上，以在封装结构的构建工艺期间提供稳定性。对准标记52被形成(通过激光切割或其他方法)在聚酰亚胺膜14内，以提供半导体装置(例如管芯)在聚酰亚胺膜上顺序的精确定位。如图11所示，粘接剂22施加在聚酰亚胺膜14上，以固定其上的半导体装置，如通过丝网印刷应用、滴涂或旋涂应用。根据本发明的一个实施例，粘接剂22可被施加在聚酰亚胺膜14上仅仅半导体装置12设置的位置。可选地，粘接剂22可施加到整个聚酰亚胺膜14上。一旦在聚酰亚胺膜14上沉积粘接剂22，半导体装置12然后使用作为定位引导件的对准标记52定位在聚酰亚胺膜上。半导体装置12然后通过固化粘接剂22而固定到聚酰亚胺膜14上。
现在参考图12，半导体装置12在聚酰亚胺膜14上一旦定位和固定，准备一个或多个介电片材26，并随后设置在聚酰亚胺膜14上和半导体装置12周围，所应用的介电片材26的数量根据半导体装置12的厚度决定。如果需要多个介电片材26，为了密封半导体装置12，片材被提供在堆叠布置中。片材26典型地由处于其预固化形式(如它们可易于堆叠)的低湿气吸收有机材料形成，诸如预浸材料、PCB芯材、聚合树脂或其它合适的粘接剂，且此后通常称为预浸片材26。在准备预浸片材26中，提供预浸材料的膜或面板且对应于半导体装置12的位置的开口28(即切口)形成在其中。准备的预浸片材26(其中形成有开口28)然后被彼此堆叠到期望的高度或厚度，从而它们完全围绕半导体装置12。在预浸片材26堆叠时，背侧介电层16(例如聚酰亚胺膜)被施加到预浸片材26的堆叠上。聚酰亚胺层/膜14、16能被用于在封装的两侧上提供好的特征尺寸控制并也提供结构平衡。在另一个实施例中，取代介电层16，可以施加铜箔或膜以阻止预浸片材26粘住用于执行层压步骤/工艺的层压按压，后面将进一步进行详细的解释。
在制造工艺的下个步骤中，且如图13中示出，执行层压工艺，以使得预浸材料熔化和流动成为连续的介电密封剂24。层压工艺可在真空环境、升温和机械压力或气压下执行，从而使得预浸片材26熔化而因此失去它们的膜形式并流动以填充半导体装置12周围的任何空的空气间隙。预浸密封剂被完全固化并能在半导体装置12周围变硬以密封装置。
如图14所示，在层压工艺完成时，多个通路30穿过聚酰亚胺膜14和背侧聚酰亚胺膜16而形成。根据本发明的实施例，通路30可通过激光烧灼或激光钻孔或机械钻孔工艺的方式形成，通路30被对准，从而被形成下到半导体装置12的正侧32上的接触垫50，从而形成到其的电连接。在实施例中示出，通路30也被形成到半导体装置12的背侧34，以从装置移除热量和/或进行用于功率装置的电连接，尽管公认的是这样的背侧通路在所有实施例中并不需要且依赖于装置。除了向下形成到半导体装置12的通路30之外，贯通路36穿过整个构建堆叠(即，穿过聚酰亚胺膜14、16和预浸密封剂24)而被钻孔。
一旦通路30、36形成下到半导体装置12并穿过密封剂24，POL金属互连件38然后被形成在封装结构中，如图15所示。根据一个实施例，POL金属互连件38可以通过溅射和电镀应用的组合而形成，尽管公认的是，其它金属沉积方法(例如无电镀层)也可以使用。例如，钛或钯粘接层和铜晶种层可以首先通过溅射的方式形成在通路30、36中，随后通过电镀工艺填充通路并在POL封装结构的正面和背面18、20两者上增加铜的厚度(即“镀层”)到需要的水平。如图16所示，随后在施加的铜上进行图案化和蚀刻，以形成具有期望尺寸/形状的POL互连件38。虽然在图15和16中示出了施加连续的铜层和连续的铜层的随后图案化和蚀刻以形成POL互连件38，公认的是，可以取替为执行经由半增加镀层工艺的POL互连件的图案化和电镀以形成POL互连件38。
在上面附图2-9和10-16中描述的制造工艺的每一个中，额外步骤可以被执行以形成多层封装结构。即，使用封装结构10作为“开始堆叠”，额外材料层可以被施加到结构10的两个外表面。因此，参考图17，一旦形成金属互连件38，其它层54、56被增加到封装结构10的两侧。根据本发明的一个实施例，层54、56由其上施加铜箔的印刷电路板(PCB)预浸材料形成，其被层压到聚酰亚胺层14、16上。根据另一个实施例，层54、56由聚酰亚胺材料形成，层54、56通过粘接剂58(虚线示出)施加到聚酰亚胺层14、16。然后在额外层54、56中钻孔成通路59，如图18示出，POL金属互连件38在通路59中镀层并在层54、56的外表面图案化。
虽然图18未示出，公认的是可以执行制造工艺的额外步骤，诸如在图案化POL互连件38和层54、56上施加焊接修整层和焊接掩膜，用于为铜提供保护层。替代焊料，公认的是暴露铜垫的焊接掩膜可被留下，直到Ni或Ni/Au或有机可焊保护(OSP)层的金属化。第二级I/O互连然后可以被施加到由焊接掩膜中的通路暴露的垫。在一个实施例中，I/O互连垫留下直到可焊接修整层以形成栅格阵列(LGA)或突起焊料以形成球栅阵列(BGA)焊料突起t，允许表面安装封装结构到外部电路，例如用焊料突起提供高度可靠的在高压力条件下抵抗失效的第二级互连结构。
根据上述描述的在图2-9和10-16中的每一个制造工艺，公认的是代替施加第二聚酰亚胺层16到密封剂24，即预浸片材26的堆叠，铜箔或膜可以施加到预浸片材。即，铜箔可以取代聚酰亚胺层16，因为关于阻止预浸层26粘住层压机表面，铜箔的功能是类似的。在图19中描述了在封装结构中实施铜箔61的实施例。在实施铜箔61中，公认的是铜线路(即金属互连件38)将形成在预浸材料26上的该铜中，而不是形成在聚酰亚胺层16上。这样做，通路30首先将形成穿过铜箔61，且POL金属互连件38然后将通过溅射和电镀应用形成在其上，连续的铜层应用和随后的图案化和蚀刻之一被执行或半增加镀层工艺被执行，以形成POL互连件38。
现在参考图20-23，示出了用于封装半导体装置的额外POL封装结构的实施例。在图20-23示出的POL封装结构实施例的每一个具有与附图1示出和描述的封装结构10类似的结构，其中它们通过使用一个或多个介电片材使得半导体装置完全嵌入，介电片材可被堆叠并定位在半导体装置周围，且随后被固化以在周围熔化/流动，以及互连件被形成在封装结构的两侧以提供到半导体装置中的所有的电(和热)连接。
首先参考图20，根据本发明的另一个实施例的封装结构60被示出。封装结构60与附图1中的封装结构10非常相似，除了封装结构60包括介电腹板材料62，此处叫“POL腹板”，其定位在半导体装置12周围。根据本发明的实施例，POL腹板62由印刷电路板(PCB)芯材、聚酰亚胺膜/层、陶瓷材料、复合介电材料或其它类似的/合适的有机材料组成，这些材料展现低湿气吸收性能并对POL提供机械刚性(即介电腹板62相比介电片材26而被构造成具有增加的硬度)，且在封装结构60层压期间不回流。根据一个实施例，POL腹板62中也可包括铜电路。另外，基于其形成材料，POL腹板62在层压工艺期间并不流动。POL腹板62被形成为其中包括开口/切口64，以适应半导体装置12和贯通路36，且POL腹板62具有合适的厚度。如图19进一步示出的，POL腹板62与密封剂24组合，以完全使得半导体装置12嵌入在封装结构60内。如先前关于图1所描述的，介电密封剂24被作为一个或多个未固化的介电材料26(如预浸材料，聚合树脂等)的片材而提供。片材26在聚酰亚胺膜14上被定位在POL腹板62和半导体装置12之间的空的间隙内，为了引起介电片材26的熔化，封装结构60受到层压工艺，因此导致片材失去它们的膜形式并流动以填充半导体装置12和介电腹板62周围任何空的空气间隙。
参考图21，根据本发明的另一实施例的POL封装结构66被示出。封装结构66与图1中的封装结构10非常相似，除了封装结构66不包括定位在介电密封剂24上在层14相对侧的介电材料层，其在层压(如聚酰亚胺层)期间不熔化和流动，如在图1中的封装结构10中的层16(即聚酰亚胺层16)。因此，在封装结构66中，聚酰亚胺层14提供在封装结构10的正面18上，同时介电密封剂24形成封装结构66的背面20。半导体装置12设置在聚酰亚胺层14上并通过粘接剂22附接在其上，以及介电密封剂24沉积在聚酰亚胺层14上，从而包围装置12。如上面详细描述的，密封剂24由一个或多个固化或部分固化(即B阶段)的有机材料(例如预浸材料，PCB芯材，聚合树脂，或其它合适的粘接剂)形成的介电片材26组成，片材以“膜”或“面板”的形式被施加在聚酰亚胺层14上，如果期望的话，以使多个介电片材26可以被彼此堆叠以达到填充半导体装置12周围的区域所需的期望高度/厚度。介电片材26受到层压工艺，其引起介电片材26熔化并失去它们的膜形式以流动并填充半导体装置12周围的任何空的空气间隙。
如图21所示，多个通路30穿过聚酰亚胺层14而下到半导体装置12的正面32而形成。通路30还穿过密封剂24到达半导体装置12的背面34而形成，从而满足电和热的要求(例如，当装置12是功率半导体装置时)。贯通路36也穿过聚酰亚胺层14和介电片材26而形成。POL金属互连件38随后形成在封装结构66中，以提供其中的电和热连接/路径，互连件38被形成在通路30、36中并伸出到封装结构66的正面和背面18、20上。
虽然图21中示出，公认的是，封装结构66还可在其中包括POL腹板结构(例如在图20中的POL腹板62)，其定位在半导体装置12周围和密封剂24之内，以提供POL结构的稳定性。POL腹板可以由印刷电路板(PCB)芯材、聚酰亚胺膜/层、陶瓷材料、或复合介电层形成一从而POL腹板结构在封装结构66的层压工艺期间不流动。
根据一个实施例，类似于图17中示出的封装结构10，封装结构66可作为“开始堆叠”，额外材料层可施加到“开始堆叠”。即，当在封装结构66中形成金属互连件38时，额外层54、56被增加到封装结构64的两侧，如图22描述。根据本发明的另一个实施例，层54、56由电路印刷板(PCB)预浸材料形成，带有其上的铜箔，其被层压到聚酰亚胺层14、16上。根据本发明的一个实施例，层54、56由聚酰亚胺材料形成，层54、56通过粘接剂58(虚线示出)施加到聚酰亚胺层14、16。通路60然后在额外层54、56中钻孔形成，如图18所示，其中金属互连件38被镀层在通路60中并图案化在层54、56的外表面上。
现在参考图23，根据本发明的另一实施例的封装结构70被示出，其中具有多个电子构件的功率模块被封装。封装结构70包括在其中的以功率装置、控制电路、和/或被动装置形式存在的多个电子构件，以及功率半导体装置72(例如管芯、二极管、MOSFET)，门驱动器74，和被动装置76在图22中示出，尽管公认的是更多或更少数量的电子装置/构件可包括在POL结构70中。另外，根据一个实施例，铜垫片78可选择地被包括和附接到半导体装置72的背侧22(例如通过焊料80)，尽管公认的是-不存在垫片78-通路30可替代被延伸到装置72(即，钻更高的通路)的背面以形成高度差。
如图23所示，聚酰亚胺层14、16提供在封装结构70的两侧上，从而提供在两侧上形成POL通路和图案化POL金属互连件的能力。电子构件72、74、76定位在聚酰亚胺层14、16之间，以及电子构件72、74、76通过粘接剂22被附接到聚酰亚胺层14。介电密封剂24提供在聚酰亚胺层14、16之间，介电密封剂24由一个或多个以“膜”或“面板”的形式提供的介电片材26组成，从而多个介电片材26能彼此堆叠以达到填充半导体装置72、门驱动器74和被动装置76周围的区域所需的期望高度/厚度。如上面描述，介电片材26受到层压工艺，其导致介电片材26熔化并失去它们的膜的形式以流动并填充电子构件72、74、76的周围和聚酰亚胺层14、16之间的任何空的空气间隙。尽管没有示出，公认的是，POL腹板结构(如图20中的腹板62)可与密封剂24定位在半导体装置12的周围以给POL结构提供稳定性，其中POL腹板结构由在层压工艺期间不流动的材料形成。
如图23所示，多个通路30穿过聚酰亚胺层14下到电子构件72、74、76形成。通路30也穿过聚酰亚胺层16到达半导体装置72的背面上的垫片78而形成。贯通路36也穿过聚酰亚胺层14、16和介电片材26而形成。金属互连件38随后形成在封装结构70中以提供其中的电和热连接/路径。如图23中所示，例如，POL互连件38被图案化和蚀刻以达到期望的形状，从而提供封装结构70的正侧18上的电连接和提供在封装结构70的背侧20上的大区域的电和热连接，其允许结构附接到例如散热部或系统I/O。
根据本发明的一个实施例，并如在附图23中的虚线所示，图22中的封装结构70可进一步被处理，例如通过增加热界面材料(TIM)82到结构的背侧20(即在介电层16上)。即，具有热导性的兼容TIM 82层被施加在POL结构70上并在POL互连件38上，互连件38在封装结构的背侧20上形成大区域的铜垫。合适的TIM的示例无限制地包括粘接剂、润滑脂、凝胶剂、衬垫、膜、液体金属、可压缩金属和相变材料。液体金属TIM，例如特别的是铟镓合金，合金特别地在功率电子应用中遭遇过温时处在液态。可压缩金属足够柔软以在散热部和POL匹配表面之间产生紧密接触且例如可包括铟。以这种方式，散热部(未示出)可被热结合到POL结构70，而未使用钎焊或冶金直接结合散热部到POL结构70，或在结合POL结构到散热部之前并不需要平整POL结构70。
在图23中，封装结构70因此被提供具有在封装结构两侧上的POL互连件38。由于其层压工艺，封装结构70能完全使所有的电子构件72、74、76嵌入，以及因此与表明安装技术是可兼容的并提供双侧冷却。双侧封装结构70在功率模块中排除了额外多层衬底(像DBC衬底等)的需要，功率模块将特别地用于电和热功能，因为这种衬底完全由POL通路和在装置背侧用于电连接和热扩散的大铜垫取代。在封装结构70中多层衬底的排除，消除了第二级组装工艺，如焊接、底部填充(或上部模塑)等。因此最终的封装结构70具有非常小的形式因数并高度小型化。
因此，根据本发明的一个实施例，封装结构包括第一介电层，附接于第一介电层的至少一个半导体装置，施加于第一介电层且在至少一个半导体装置周围以使至少一个半导体装置嵌入其中的一个或多个介电片材，以及形成在至少一个半导体装置的多个通路，多个通路形成在第一介电层和一个或多个介电片材中的至少一者。封装结构还包括形成在多个通路中和在封装结构的一个或多个朝外表面的金属互连件，以形成到至少一个半导体装置的电互联。第一介电层由在层压工艺期间不流动的材料组成，并且一个或多个介电片材中的每一个由可固化材料组成，该材料被构造成在层压工艺期间当固化时熔化并流动，使得一个或多个介电片材熔化并流动以填充于至少一个半导体装置周围的任何空气间隙。
根据本发明的另一个实施例，制造半导体装置封装结构的方法包括，通过粘接剂附接至少一个半导体装置到第一介电层，形成一个或多个构造为当固化时熔化并流动的可固化材料的介电片材，其中介电片材的每一个在未固化或部分固化状态，施加一个或多个介电片材在第一介电层上，以被定位在至少一个半导体装置周围，施加铜箔在最后介电片材的外表面上，和固化一个或多个介电片材，以使得一个或多个介电片材熔化并流入存在于至少一个半导体装置周围的任何空气间隙中，并且使得至少一个半导体装置嵌入其中，其中第一介电层在一个或多个介电片材固化期间不流动。方法还包括形成多个通路到至少一个半导体装置，多个通路形成在第一层和一个或多个介电片材中的至少一者，和在多个通路中且在封装结构的一个或多个外表面的至少一部分上形成金属互连件，金属互连形成到至少一个半导体装置的电互连。
根据本发明的又一个实施例，POL封装结构包括第一介电层，第一介电层具有施加到其至少一部分上的粘接剂，通过粘接剂附接到第一介电层的一个或多个半导体装置，其中一个或多个半导体装置的每一个的表面具有附接到第一介电层的接触垫，和被定位在一个或多个半导体装置周围的第一介电层上的介电密封剂，使得一个或多个半导体装置被嵌入其中，介电密封剂包括一个或多个未固化或部分固化的介电片材，其被构造成在固化时熔化并流动从而填充存在于一个或多个半导体装置周围的任何空气间隙。POL封装结构还包括形成在一个或多个半导体装置和在第一介电层和介电密封剂中的至少一者的多个通路，以及POL互连件，其形成在多个通路中以形成到一个或多个半导体装置和在POL封装结构中的所有电和热互连。第一电介质被构造成在一个或多个介电片材固化期间不流动。
虽然本发明仅与有限数目的实施例结合而详细描述，但应理解的是，本发明并与限于这些已经公开实施例。相反，本发明能被修改以包含此处未描述的任何数量的变型、变化、替代或等同布置，但是这些是与本发明的精神和范围是一致的。另外，虽然本发明的各种实施例已被描述，但应当理解的是，本发明的方面可仅包括所描述的实施例的一些。因此，本发明并不被先前的描述所限制，但仅被所附权利要求的范围限制。

Claims (10)

1.一种封装结构，包括：
第一介电层；
附接到所述第一介电层的至少一个半导体装置；
一个或多个介电片材，其施加到所述第一介电层上和所述至少一个半导体装置周围，使得所述至少一个半导体装置嵌入其中；
形成到所述至少一个半导体装置的多个通路，所述多个通路形成在所述第一介电层和所述一个或多个介电片材中的至少一者；以及
金属互连件，其形成在所述多个通路中和在所述封装结构的一个或多个朝外表面上，以形成到所述至少一个半导体装置的电互连；
其中，所述第一介电层由在层压工艺期间不流动的材料组成；
其中，所述一个或多个介电片材中的每一个由可固化材料组成，该可固化材料被配置成在所述层压工艺期间当固化时熔化并流动，使得所述一个或多个介电片材熔化并流动以填充存在于所述至少一个半导体装置周围的任何空气间隙。
2.根据权利要求1所述的封装结构，其特征在于，还包括设置在至少一个半导体装置周围的介电腹板，其中介电腹板包括一个或多个形成在其中以接收至少一个半导体装置的开口。
3.根据权利要求2所述的封装结构，其特征在于，介电腹板相比于介电片材被构造为具有增加的刚性且在层压工艺期间不流动，其中介电腹板由印刷电路板(PCB)芯材、聚酰亚胺层、陶瓷材料和复合介电材料中的一者组成。
4.根据权利要求2所述的封装结构，其特征在于，介电腹板被构造为其中具有铜电路。
5.根据权利要求1所述的封装结构，其特征在于，一个或多个介电片材由处于未固化或部分固化状态的预浸材料、聚合树脂、或粘接剂中的一者组成。
6.根据权利要求1所述的封装结构，其特征在于，至少一个半导体装置包括功率半导体装置。
7.根据权利要求6所述的封装结构，其特征在于，多个通路包括：
穿过第一介电层到达功率半导体装置的正面而形成的通路；和
穿过一个或多个介电片材到达功率半导体装置的背面而形成的通路；
其中通路功能作为封装结构中的电和热通路；以及
其中金属互连件形成在通路的每一个中，并到达功率半导体装置的正面和背面。
8.根据权利要求7所述的封装结构，其特征在于，金属互连件包括形成电连接的镀铜功率覆盖(POL)互连件和在封装结构的朝外表面上的热扩散铜垫，从而提供到功率半导体装置的电和热互连。
9.根据权利要求6所述的封装结构，其特征在于，还包括施加在封装结构的朝外表面上和热扩散铜垫上的热界面材料(TIM)，从而使得封装结构结合到散热部。
10.根据权利要求1所述的封装结构，其特征在于，还包括多个延伸穿过第一介电层和一个或多个介电片材的贯通路，且其中金属互连件形成在贯通路的每一个中，并到达功率半导体装置的正面和背面。
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EP2854168A3 (en) 2015-08-05
JP2015070269A (ja) 2015-04-13
KR20150034617A (ko) 2015-04-03
US20150380356A1 (en) 2015-12-31
KR102295990B1 (ko) 2021-09-02
TWI679737B (zh) 2019-12-11
TW201907530A (zh) 2019-02-16
TWI634632B (zh) 2018-09-01
EP2854168A2 (en) 2015-04-01
TW201523821A (zh) 2015-06-16

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