JP6125757B2 - 半導体装置、ランダム・アクセス・メモリ、及びメモリ - Google Patents
半導体装置、ランダム・アクセス・メモリ、及びメモリ Download PDFInfo
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- JP6125757B2 JP6125757B2 JP2012067049A JP2012067049A JP6125757B2 JP 6125757 B2 JP6125757 B2 JP 6125757B2 JP 2012067049 A JP2012067049 A JP 2012067049A JP 2012067049 A JP2012067049 A JP 2012067049A JP 6125757 B2 JP6125757 B2 JP 6125757B2
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- oxide semiconductor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/056—Making the transistor the transistor being a FinFET
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/36—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being a FinFET
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
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Description
図1乃至図4に本実施の形態のFETの形状の概念図を示す。図1はFETの斜視図であり、図2は面Xでの断面図、図3は面Yでの断面図、図4は面Zでの断面図である。図1乃至図4に示すFETは絶縁表面100に接して、厚さtが1nm以上30nm以下、好ましくは3nm以上5nm以下、高さhが、5nm以上100nm以下、好ましくは10nm以上50nm以下の薄片状の酸化物半導体101を有する。
図5に本実施の形態のFETを示す。図5(A)は図2に相当するX面での断面図であり、図5(B)は図3に相当するY面での断面図である。なお、本実施の形態のFETの図4に相当するZ面での断面図は図4と同じである。
図6に本実施の形態のFETを示す。図6(A)は図2に相当するX面での断面図であり、図6(B)は図3に相当するY面での断面図である。なお、本実施の形態のFETの図4に相当するZ面での断面図は図4と同じである。本実施の形態のFETは絶縁表面100に接する酸化物半導体101を有する。
図7に本実施の形態のFETを示す。図7(A)は図2に相当するX面での断面図であり、図7(B)は図3に相当するY面での断面図である。なお、本実施の形態のFETの図4に相当するZ面での断面図は図4と同じである。本実施の形態のFETは絶縁表面100に接する酸化物半導体101を有する。
図8および図9を用いて本実施の形態のFETの作製方法を説明する。図8および図9は、FETの各作製工程における3つの断面を表記したものであり、非特許文献1のFig.1に相当する。なお、以下の説明では、公知の半導体作製技術あるいは特許文献1、特許文献2を参照できる。
以上の実施の形態では、FETを絶縁表面上に形成する例を示したが、一部が導電性である表面の上にFETを形成してもよい。その場合には、下層と電気的な接続が可能となる。図11にそのようなFETとそれを利用した半導体回路(メモリセル)の例を示す。
本実施の形態では、実施の形態2のFETをいわゆるゲインセル型メモリに適用した例について説明する。なお、使用するFETは、実施の形態2のものに限らず、実施の形態1、実施の形態3乃至5のものを用いてもよい。
以下では、実施の形態6あるいは実施の形態7で説明したメモリの利用例について図14を参照して説明する。図14は、マイクロプロセッサの構成例を示すブロック図である。図14に示すマイクロプロセッサは、CPU301、メインメモリ302、クロックコントローラ303、キャッシュコントローラ304、シリアルインターフェース305、I/Oポート306、端子307、インターフェース308、キャッシュメモリ309等が形成されている。勿論、図14に示すマイクロプロセッサは、その構成を簡略化して示した一例にすぎず、実際のマイクロプロセッサはその用途によって多種多様な構成を有している。
本実施の形態では、実施の形態6あるいは実施の形態7で説明したメモリを有する半導体装置の例について説明する。当該半導体装置は、本発明の一態様に係るメモリを用いることで、小型化を実現することが可能である。特に、携帯用の半導体装置の場合、本発明の一態様に係るメモリを用いることで小型化が実現されれば、使用者の使い勝手が向上するというメリットが得られる。
101 酸化物半導体
102 ゲート絶縁膜
103 ゲート
104 ソース
105 ドレイン
106 空乏化領域
107 N型領域
108 N型領域
109 側壁絶縁物
110 側壁絶縁物
111 バリア絶縁物
112 層間絶縁物
113 ビット線
113a 導電性領域
114 ドライバ回路部
115 セルトランジスタ
116 キャパシタ
117 接続電極
118 下部電極
119 キャパシタ絶縁膜
120 上部電極
121 ゲート
122 ドレイン
123 ソース
124 読み出しワード線
125 ビット線
126 キャパシタ
127 書き込みトランジスタ
128 読み出しトランジスタ
201a 酸化物半導体
201b 酸化物半導体
201c 酸化物半導体
202a ゲート絶縁膜
202b ゲート絶縁膜
202c ゲート絶縁膜
203a ゲート
203b ゲート
203c ゲート
204a ソース
204b ソース
204c ソース
205a ドレイン
205b ドレイン
205c ドレイン
206a 空乏化領域
206b 空乏化領域
207 N型領域
208 N型領域
301 CPU
302 メインメモリ
303 クロックコントローラ
304 キャッシュコントローラ
305 シリアルインターフェース
306 I/Oポート
307 端子
308 インターフェース
309 キャッシュメモリ
401 筐体
402 筐体
403 表示部
404 表示部
405 マイクロホン
406 スピーカー
407 操作キー
408 スタイラス
411 筐体
412 表示部
413 音声入力部
414 音声出力部
415 操作キー
416 受光部
421 筐体
422 表示部
423 操作キー
Claims (8)
- トランジスタを含む回路を有し、
前記トランジスタは、
絶縁表面に略垂直に設けられた酸化物半導体と、
前記酸化物半導体と電気的に接続するソース及びドレインと、
前記酸化物半導体を覆って設けられたゲート絶縁膜と、
前記ゲート絶縁膜を覆って設けられたゲートと、
を有し、
前記酸化物半導体の高さ方向と、前記トランジスタのチャネル長方向とが交わる方向における前記酸化物半導体の厚さは、前記酸化物半導体の高さより小さく、
前記酸化物半導体は、前記絶縁表面と接しない第1の面を有し、
前記ソースは、前記第1の面と接して重なる領域を有し、
前記ドレインは、前記第1の面と接して重なる領域を有し、
前記ゲートは、前記ソース又は前記ドレインと重なる領域を有し、
前記ゲートは、前記酸化物半導体の少なくとも3つの面と面することを特徴とする半導体装置。 - 請求項1において、
前記ゲートは、ストライプ状であり、幅が10nm以上100nm以下であることを特徴とする半導体装置。 - 請求項1又は2において、
前記酸化物半導体が、酸化インジウム、酸化亜鉛、酸化錫、In−Zn系酸化物、Sn−Zn系酸化物、Al−Zn系酸化物、Zn−Mg系酸化物、Sn−Mg系酸化物、In−Mg系酸化物、In−Sn系酸化物、In−Ga系酸化物、In−Ga−Zn系酸化物、In−Sn−Zn系酸化物、In−Al−Zn系酸化物、Sn−Ga−Zn系酸化物、Al−Ga−Zn系酸化物、Sn−Al−Zn系酸化物、In−Sn−Ga−Zn系酸化物より選ばれた1つであることを特徴とする半導体装置。 - 請求項1乃至3のいずれか一項において、
前記酸化物半導体は結晶性を有することを特徴とする半導体装置。 - 請求項1乃至4のいずれか一項において、
前記酸化物半導体の一部は、窒素、硼素あるいはリンを含む領域を有することを特徴とする半導体装置。 - 請求項1乃至請求項5のいずれか一項において、
前記酸化物半導体は、前記高さ方向を有する表面と、前記厚さ方向を有する表面の交わる角が丸みを帯びていることを特徴とする半導体装置。 - 請求項1乃至請求項6のいずれか一項に記載のトランジスタをセルトランジスタとして有するランダム・アクセス・メモリ。
- 請求項1乃至請求項6のいずれか一項に記載のトランジスタを書き込みトランジスタとして有するメモリ。
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