TW201236160A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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TW201236160A
TW201236160A TW101102257A TW101102257A TW201236160A TW 201236160 A TW201236160 A TW 201236160A TW 101102257 A TW101102257 A TW 101102257A TW 101102257 A TW101102257 A TW 101102257A TW 201236160 A TW201236160 A TW 201236160A
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trench
insulating layer
oxide semiconductor
layer
semiconductor device
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TW101102257A
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Chinese (zh)
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TWI570921B (en
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Shunpei Yamazaki
Hiromichi Godo
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Semiconductor Energy Lab
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    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
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Abstract

A conventional DRAM needs to be refreshed at an interval of several tens of milliseconds to hold data, which results in large power consumption. In addition, a transistor therein is frequently turned on and off; thus, deterioration of the transistor is also a problem. These problems become significant as the memory capacity increases and transistor miniaturization advances. A transistor is provided which includes an oxide semiconductor and has a trench structure including a trench for a gate electrode and a trench for element isolation. Even when the distance between a source electrode and a drain electrode is decreased, the occurrence of a short-channel effect can be suppressed by setting the depth of the trench for the gate electrode as appropriate.

Description

201236160 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體積體電路的微型化技術。在 本說明書所公開的發明中，作爲構成半導體積體電路的構 ' 件，包括由矽半導體以外的化合物半導體構成的元件。作 爲其一例公開有使用氧化物半導體的元件。 【先前技術】 動態 RAM ( DRAM : Dynamic Random Access Memory :動態隨機存取記憶體）是公知的半導體儲存裝置的產品 ，至今仍被使用於各種電子裝置中。構成DRAM的核心部 分的記憶單元由用來寫入及讀出的電晶體和電容器構成。 DRAM與其他半導體積體電路同樣，根據比例定律電 路圖案的微型化得到了推進，但是以前一般認爲將設計規 則設定爲lOOnm以下是很難的。其原因之一是，當將電晶 體的通道長度設定爲100nm以下時，由於短通道效應，穿 透電流容易流過，從而使電晶體失去作爲切換元件的功能 。當然，爲了防止穿透電流流過，可以對矽基板摻雜高純 度的雜質。但是，如果進行該處理，則在源極與基板之間 或在汲極與基板之間容易流過接面漏電，結果會使記憶體 的保持特性降低。因此，上述處理作爲該問題的解決辦法 是不合適的。 鑒於上述問題，提出了如下方法··藉由形成三維電晶 體作爲構成記憶單元的電晶體，在縮小一個記憶單元所佔 -5- 201236160 的面積的同時，將電晶體的有效的通道長度維持爲不產生 短通道效應的程度。例如有如下結構：在電晶體的形成通 道部分的區域中形成U字狀的縱長溝槽，沿著該溝槽的壁 面形成閘極絕緣膜，並且將閘極電極埋入該溝槽中（參照 非專利文獻1 )。 在將這種結構用於其通道部分的電晶體中，由於流過 源極區與汲極區之間的電流沿著溝槽部分流過，因此有效 的通道長度變長。因而，可以縮小在記憶單元中電晶體所 佔的面積，同時可以抑制短通道效應。 [非專利文獻1]201236160 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a miniaturization technique of a semiconductor integrated circuit. In the invention disclosed in the present specification, an element constituting a semiconductor integrated circuit includes an element composed of a compound semiconductor other than a germanium semiconductor. An element using an oxide semiconductor is disclosed as an example thereof. [Prior Art] Dynamic RAM (DRAM) is a well-known product of semiconductor storage devices and has been used in various electronic devices. The memory cells constituting the core portion of the DRAM are composed of a transistor and a capacitor for writing and reading. Like other semiconductor integrated circuits, DRAM has been advanced in accordance with the proportional law circuit pattern, but it has been generally considered difficult to set the design rule to 100 nm or less. One of the reasons is that when the channel length of the electromorph is set to 100 nm or less, the permeation current easily flows due to the short channel effect, so that the transistor loses its function as a switching element. Of course, in order to prevent the penetration current from flowing, the germanium substrate may be doped with impurities of high purity. However, if this treatment is performed, leakage of the junction surface easily occurs between the source and the substrate or between the drain and the substrate, and as a result, the retention characteristics of the memory are lowered. Therefore, the above processing is not suitable as a solution to this problem. In view of the above problems, the following method has been proposed: By forming a three-dimensional transistor as a transistor constituting a memory cell, while reducing the area of a memory cell -5 to 201236160, the effective channel length of the transistor is maintained as The extent to which the short channel effect is not produced. For example, there is a structure in which a U-shaped elongated trench is formed in a region where the channel portion of the transistor is formed, a gate insulating film is formed along a wall surface of the trench, and a gate electrode is buried in the trench (refer to Non-patent document 1). In the transistor in which such a structure is used for its channel portion, since the current flowing between the source region and the drain region flows along the groove portion, the effective channel length becomes long. Therefore, the area occupied by the transistor in the memory cell can be reduced, and the short channel effect can be suppressed. [Non-Patent Document 1]

Kinam Kim， Technology for sub-50nm DRAM and NAND Flash Manufacturing” （亞 50nmDRAM 和 NAND 快 快閃記憶體的生產技術），International Electron Devices Meeting，2005. IEDM Technical Digest，2005 年 12 月’ p. 333-336 另一方面，習知的dram爲了保持資料而需要每隔幾 十毫秒進行更新工作’因此導致耗電量的增大。此外’由 於頻繁地切換電晶體的導通狀態和截止狀態’電晶體的劣 化成爲問題。上述問題隨著儲存容量增大和電晶體微型化 的進展而變得明顯。 【發明內容】 因此，本發明的目的之—在於提供能夠改善半導體儲 存裝置中的資料保持特性的技術。另外’本發明的目的之 -6 - 201236160 一在於提供能夠在改善半導體儲存裝置中的資料保 的同時降低耗電量的技術。 爲了解決上述問題，藉由使用具有氧化物半導 :Oxide Semiconductor)的電晶體，尤其使用具有 半導體的MOS電晶體來構成電路，明確而言，構 體儲存裝置。這種氧化物半導體是實際上本質的半 因此，這種半導體具有截止電流極低的優點。 從而，藉由使用具有氧化物半導體的電晶體， 更新工作的間隔長於習知的DRAM，而可以實現耗 降低。此外，每單位時間的電晶體的導通狀態和截 的切換次數被降低，所以可以使這種電晶體的使用 於習知的DRAM。 另外，在使用氧化物半導體層的電晶體中，如 電晶體的微型化，則有可能發生短通道效應。於是 使用氧化物半導體層的新穎的電晶體結構。 本說明書所公開的實施方式的一個方式的半導 ，包括：在絕緣層中的第一溝槽及第二溝槽；接觸 溝槽的底面及內壁面的氧化物半導體層；氧化物半 上的閘極絕緣層；閘極絕緣層上的閘極電極；以及 二溝槽的絕緣層’其中，閘極絕緣層位於第二溝槽 及內壁面上，閘極電極塡充第一溝槽。第一溝槽爲 極用溝槽’而第二溝槽爲元件隔離用溝槽。另外， 槽的頂面形狀爲條紋形狀或棒狀，而第二溝槽的頂 爲格子形狀、條紋形狀或棒狀。 持特性 體（OS 氧化物 成半導 導體。 可以使 電量的 止狀態 壽命長 果推進 ，提出 體裝置 於第一 導體層 塡充第 的底面 閘極電 第一溝 面形狀 201236160 在上述結構中’還具有接觸於氧化物半導體層的源極 電極或汲極電極。 另外’在上述結構中，爲了提高電晶體的可靠性，閘 極絕緣層具有接觸並覆蓋氧化物半導體層的側面的結構。 另外，較佳的是’將上述氧化物半導體層的厚度設定 爲lnm以上且100nm以下，上述氧化物半導體層可以使 用結晶氧化物半導體層。藉由使用結晶氧化物半導體層， 可以抑制因可見光或紫外光的照射引起的電晶體的電特性 變化’從而可以製造可靠性高的半導體裝置。並且，該結 晶氧化物半導體層既不是單晶結構，又不是非晶結構，而 是具有c軸配向的結晶氧化物半導體（C Axis Aiigned Crystalline Oxide Semiconductor;也稱爲 CAAC-OS)膜 。CAAC-OS膜不是完全的單晶，也不是完全的非晶。 CAAC-OS膜是在非晶相中具有結晶部及非晶部的結晶-非 晶混合相結構的氧化物半導體膜。另外，在很多情況下， 該結晶部的尺寸爲能夠容納在一邊短於l〇〇nm的立方體內 的尺寸。另外，在使用穿透式電子顯微鏡（Transmission Electron Microscope, TEM )觀察時的影像中，包括在 CAAC-OS膜中的非晶部與結晶部的邊界不明確。另外， 不能利用 TEM在CAAC-OS膜中觀察到晶界（grain boundary)。因此，在CAAC-OS膜中，起因於晶界的電 子遷移率降低被抑制。 包括在CAAC-OS膜中的結晶部的c軸在平行於 CAAC-OS膜的被形成面的法線向量或表面的法線向量的 201236160 方向上一致，在從垂直於ab面的方向看時具有三角 六角形的原子排列，且在從垂直於c軸的方向看時， 原子排列爲層狀或者金屬原子和氧原子排列爲層狀。 ，不同結晶部的a軸及b軸的方向也可以彼此不同。 ' 說明書中，在只記載“垂直”時，也包括85°以上且 ' 以下的範圍。另外，在只記載“平行”時，也包括- 上且5°以下的範圍。 另外，在CAAC-OS膜中，結晶部的分佈也可以 勻。例如，在CAAC-OS膜的形成過程中，在從氧化 導體膜的表面一側進行結晶生長時，與被形成面近旁 ，有時在表面近旁結晶部所佔的比例高。另外，藉 CAAC-OS膜添加雜質，有時在該雜質添加區中結晶 晶化。因爲包括在CAAC-OS膜中的結晶部的c軸在 於CAAC-OS膜的被形成面的法線向量或表面的法線 的方向上一致，所以有時根據CAAC-OS膜的形狀（ 成面的剖面形狀或表面的剖面形狀）朝向彼此不同的 。另外，結晶部的c軸方向是平行於形成CAAC-OS 的被形成面的法線方向或表面的法線方向的方向。藉 行成膜或藉由在成膜之後進行加熱處理等晶化處理來 結晶部。 使用CAAC-OS膜的電晶體可以降低因照射可見 紫外光而產生的電特性變動。因此，該電晶體的可靠 〇 另外，上述氧化物半導體層的通道長度方向的剖 形或 金屬 另外 在本 95° 5。以 不均 物半 相比 由對 部非 平行 向量 被形 方向 膜時 由進 形成 光或 性高 面形 -9 * 201236160 狀爲沿著第一溝槽的剖面形狀彎曲的形狀，即U字形狀， 並且第一溝槽的深度越深電晶體的通道長度越長。當作爲 氧化物半導體層使用結晶氧化物半導體層時，其包含如下 結晶，該結晶具有大致垂直於U字形狀的氧化物半導體層 的表面的C軸。 另外，本說明書中公開的溝槽結構的電晶體，即使將 源極電極與汲極電極之間的距離設定得較窄，藉由適當地 設定第一溝槽的深度，可以抑制短通道效應。 藉由本發明能夠改善半導體儲存裝置中的資料保持特 性。另外，藉由本發明能夠改善半導體儲存裝置中的資料 保持特性，同時能夠降低耗電量。 【實施方式】 下面，參照圖式對本發明的實施方式進行詳細說明。 但是，本發明不侷限於以下說明，所屬技術領域的普通技 術人員可以很容易地理解一個事實就是其方式和詳細內容 可以被變換爲各種形式。另外，本發明不應該被解釋爲僅 限於以下所示的實施方式的記載內容。 實施方式1 在本實施方式中，參照圖1A至圖2C對本發明的一個 方式的電晶體的結構及其製造方法進行說明。圖1A示出 電晶體162的通道長度方向的剖面圖的一例。另外，圖 1B示出電晶體162和電晶體163的元件隔離區165的剖 -10- 201236160 面圖的一例。另外，圖1C示出電晶體162和電晶體163 的俯視圖的一例。注意，圖1B是電晶體162的通道寬度 方向的剖面圖的一部分，相當於沿著圖1 C中的虛線D 1 -D2切割的剖面。另外，圖1A相當於沿著圖1 C中的虛線 A1-A2切割的剖面。 ‘首先，在半導體基板上形成由氧化膜構成的絕緣層 130。並且，在該絕緣層130中形成多個溝槽（也稱爲槽） 。然後，以覆蓋該溝槽的方式形成氧化物半導體層M4。溝 槽可以使用公知的技術來形成，在本實施方式中形成深度 大約爲0.4μιη的溝槽。另外，在本實施方式中，藉由進行一 次或多次蝕刻來形成閘極電極用溝槽。 半導體基板可以使用SOI基板、形成有包括MOSFET 結構的電晶體的驅動電路的半導體基板、形成有電容的半 導體基板等。 由於絕緣層130與氧化物半導體層144接觸，因此較 佳的是在絕緣層130的膜中（塊（bulk )中）至少有超過 化學計量比的量的氧。例如，當將氧化矽膜用於絕緣層 130時，使用 Si02 + a (注意，α>0)的膜。藉由使用這種 絕緣層130，可以對氧化物半導體層144供應氧，從而可 以提高特性。 將氧化物半導體層144的厚度設定爲lnm以上lOOnm 以下，並可以適當地使用濺射法、MB E ( Molecular Beam Epitaxy :分子束外延）法、CVD法、脈衝雷射堆積法、 ALD ( Atomic Layer Deposition :原子層堆積）法、塗敷 -11 - 201236160 法、印刷法等。另外，還可以使用在大致垂直於濺射靶材 表面設置多個基板表面的狀態下進行成膜的濺射裝置，即 所謂的 CP 灘射裝置（Columnar Plasma Sputtering system :柱形電漿濺射系統）形成氧化物半導體層144。 作爲氧化物半導體層144的材料，至少含有選自In、 Ga、Sn及Zn中的一種以上的元素。例如，可以使用··四 元金屬氧化物的In-Sn-Ga-Zn-Ο類氧化物半導體；三元金 屬氧化物的In-Ga-Ζη-Ο類氧化物半導體、in-Sn-Zn-Ο類 氧化物半導體、In-Al-Ζη-Ο類氧化物半導體、Sn-Ga-Zn-0 類氧化物半導體、Al-Ga-Ζη-Ο類氧化物半導體、Sn-Al_ Zn-Ο類氧化物半導體；二元金屬氧化物的ΐη-Ζη-0類氧化 物半導體、Sn-Zn-Ο類氧化物半導體、Ai-zn-o類氧化物 半導體、Zn-Mg-Ο類氧化物半導體、Sn-Mg-O類氧化物半 導體、In-Mg-Ο類氧化物半導體、In-Ga-Ο類氧化物半導 體；以及單元金屬氧化物的In-Ο類氧化物半導體、Sn-0 類氧化物半導體、Zn-Ο類氧化物半導體等。另外，也可 以使上述氧化物半導體包含In、Ga、Sn、Zn以外的元素 ，例如Si02。另外，作爲穩定劑具有鋁（A1 )較佳。 另外’作爲其他穩定劑’可以具有鑭系元素的鑭（La )、姉（Ce)、鐯（Pr)、鈸（Nd)、釤（Sm)、銪.（ Eu ) 、I ( Gd )、鉞（Tb )、鏑（Dy)、鈥（Ho )、餌 (Er)、錢（Tm)、鏡（Yb)、鑰（Lu)中的一種或多 種。 例如In-Ga-Zn-Ο類氧化物半導體是指具有銦（In )、 -12- 201236160 鎵（Ga)和鋅（Zn)的氧化物半導體，對In' Ga、Zn的 比率沒有限制。另外，也可以包含In、Ga、Ζη以外的金 屬元素。 另外，氧化物半導體層可以使用由化學式ΙπΜ03 ( ZnO) m(m>0)表示的薄膜。這裏，Μ表示選自Zn、Ga 、A1、Μη和Co中的一種或多種金屬元素。例如，作爲μ ，有Ga、Ga及Al、Ga及Μη或Ga及Co等。 另外’當作爲氧化物半導體使用Ιη-Ζη-0類材料時， 將所使用的靶材的組成比設定爲使原子數比爲In:Zn = 5〇:1 至1:2(換算爲莫耳數比則爲ιη2〇3:Ζη〇 = 25:1至1:4)， 較佳爲Ιη:Ζη = 20:1至1 : 1 (換算爲莫耳數比則爲Kinam Kim, Technology for sub-50nm DRAM and NAND Flash Manufacturing", International Electron Devices Meeting, 2005. IEDM Technical Digest, December 2005' p. 333-336 On the other hand, the conventional dram needs to perform update work every few tens of milliseconds in order to maintain data. This results in an increase in power consumption. In addition, 'the switching state and the off state of the transistor are frequently switched due to the deterioration of the transistor. The above problems become apparent as the storage capacity increases and the miniaturization of the transistor progresses. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a technique capable of improving data retention characteristics in a semiconductor storage device. OBJECT OF THE INVENTION-6 - 201236160 One is to provide a technology capable of reducing power consumption while improving data storage in a semiconductor storage device. To solve the above problem, by using an oxide semiconductor: Oxide Semiconductor a transistor, in particular using a MOS transistor having a semiconductor to form a circuit In particular, a structure storage device. This oxide semiconductor is actually a substantial half. Therefore, such a semiconductor has an advantage of extremely low off current. Thus, by using a transistor having an oxide semiconductor, the update operation is performed. The interval is longer than the conventional DRAM, and the power consumption can be reduced. In addition, the conduction state of the transistor per unit time and the number of times of switching of the cutoff are reduced, so that the transistor can be used in a conventional DRAM. In a transistor using an oxide semiconductor layer, such as miniaturization of a transistor, a short channel effect may occur. Thus, a novel transistor structure using an oxide semiconductor layer is used. Half of one mode of the embodiment disclosed in the present specification The first trench and the second trench in the insulating layer; the oxide semiconductor layer contacting the bottom surface and the inner wall surface of the trench; the gate insulating layer on the oxide half; and the gate on the gate insulating layer a pole electrode; and an insulating layer of the two trenches, wherein the gate insulating layer is located on the second trench and the inner wall surface, and the gate electrode is filled with the first trench. The groove is a groove for the extreme use and the second groove is a groove for element isolation. Further, the top surface of the groove has a stripe shape or a rod shape, and the top of the second groove has a lattice shape, a stripe shape or a rod shape. Holding the characteristic body (the OS oxide is a semiconducting conductor. The life of the electric quantity can be promoted for a long time, and the body device is applied to the first conductor layer to fill the bottom surface of the first electric gate surface shape 201236160 in the above structure' There is also a source electrode or a drain electrode that is in contact with the oxide semiconductor layer. Further, in the above structure, in order to improve the reliability of the transistor, the gate insulating layer has a structure in which it contacts and covers the side surface of the oxide semiconductor layer. Further, it is preferable that the thickness of the oxide semiconductor layer is set to be 1 nm or more and 100 nm or less, and the oxide semiconductor layer can be a crystalline oxide semiconductor layer. By using the crystalline oxide semiconductor layer, it is possible to suppress the change in the electrical characteristics of the transistor due to the irradiation of visible light or ultraviolet light, whereby a highly reliable semiconductor device can be manufactured. Further, the crystalline oxide semiconductor layer is neither a single crystal structure nor an amorphous structure, but is a C Axis Aiigned Crystalline Oxide Semiconductor (also referred to as CAAC-OS) film having a c-axis alignment. The CAAC-OS film is not a complete single crystal, nor is it completely amorphous. The CAAC-OS film is an oxide semiconductor film having a crystal-amorphous mixed phase structure of a crystal portion and an amorphous portion in an amorphous phase. Further, in many cases, the size of the crystal portion is such that it can be accommodated in a cube having a side shorter than 10 nm. Further, in the image observed by a transmission electron microscope (TEM), the boundary between the amorphous portion and the crystal portion included in the CAAC-OS film is not clear. In addition, the grain boundary cannot be observed in the CAAC-OS film by TEM. Therefore, in the CAAC-OS film, the decrease in electron mobility due to the grain boundary is suppressed. The c-axis of the crystal portion included in the CAAC-OS film is uniform in a direction parallel to the normal vector of the formed face of the CAAC-OS film or the normal vector of the surface in the direction of 201236160, when viewed from a direction perpendicular to the ab plane An atomic arrangement having a triangular hexagon, and when viewed from a direction perpendicular to the c-axis, the atoms are arranged in a layer or the metal atoms and oxygen atoms are arranged in a layer. The directions of the a-axis and the b-axis of the different crystal portions may be different from each other. In the specification, when only "vertical" is described, the range of 85° or more and 'the following is also included. In addition, when only "parallel" is described, the range of -upper and 5 degrees or less is also included. In addition, in the CAAC-OS film, the distribution of the crystal portion can be uniform. For example, in the formation of the CAAC-OS film, when crystal growth is performed from the surface side of the oxide conductor film, the ratio of the crystal portion in the vicinity of the surface to be formed may be high. Further, impurities are added by the CAAC-OS film, and sometimes crystallized in the impurity addition region. Since the c-axis of the crystal portion included in the CAAC-OS film is identical in the direction of the normal vector of the surface to be formed or the normal of the surface of the CAAC-OS film, it is sometimes shaped according to the shape of the CAAC-OS film. The cross-sectional shape or the cross-sectional shape of the surface) is different toward each other. Further, the c-axis direction of the crystal portion is a direction parallel to the normal direction of the formed surface of the CAAC-OS or the normal direction of the surface. The crystal portion is formed by film formation or by crystallization treatment such as heat treatment after film formation. A transistor using a CAAC-OS film can reduce variations in electrical characteristics caused by exposure to visible ultraviolet light. Therefore, the transistor is reliable. In addition, the above-mentioned oxide semiconductor layer has a channel lengthwise cross-section or a metal of another 95°. A shape that is curved along a cross-sectional shape of the first groove, that is, a U-shape, when the film is formed by a non-parallel vector of a non-parallel vector, and is formed by a light-forming or high-surface shape -9 * 201236160. And the deeper the depth of the first trench, the longer the channel length of the transistor. When a crystalline oxide semiconductor layer is used as the oxide semiconductor layer, it contains a crystal having a C-axis substantially perpendicular to the surface of the U-shaped oxide semiconductor layer. Further, in the transistor of the trench structure disclosed in the present specification, even if the distance between the source electrode and the drain electrode is set to be narrow, the short channel effect can be suppressed by appropriately setting the depth of the first trench. The data retention characteristics in the semiconductor memory device can be improved by the present invention. Further, according to the present invention, it is possible to improve the data retention characteristics in the semiconductor storage device while reducing the power consumption. [Embodiment] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and one of ordinary skill in the art can easily understand the fact that the manner and details can be changed into various forms. Further, the present invention should not be construed as being limited to the description of the embodiments shown below. (Embodiment 1) In this embodiment, a structure of a transistor of one embodiment of the present invention and a method of manufacturing the same will be described with reference to Figs. 1A to 2C. Fig. 1A shows an example of a cross-sectional view of the transistor 162 in the channel length direction. In addition, FIG. 1B shows an example of a cross-sectional view of the element isolation region 165 of the transistor 162 and the transistor 163. In addition, FIG. 1C shows an example of a plan view of the transistor 162 and the transistor 163. Note that Fig. 1B is a part of a cross-sectional view in the channel width direction of the transistor 162, which corresponds to a section cut along the broken line D 1 - D2 in Fig. 1C. In addition, Fig. 1A corresponds to a section cut along the broken line A1-A2 in Fig. 1C. 'First, an insulating layer 130 composed of an oxide film is formed on a semiconductor substrate. Further, a plurality of grooves (also referred to as grooves) are formed in the insulating layer 130. Then, the oxide semiconductor layer M4 is formed in such a manner as to cover the trench. The groove can be formed using a known technique, and in the present embodiment, a groove having a depth of about 0.4 μm is formed. Further, in the present embodiment, the gate electrode trench is formed by performing one or more etchings. As the semiconductor substrate, an SOI substrate, a semiconductor substrate on which a drive circuit including a transistor of a MOSFET structure is formed, a semiconductor substrate on which a capacitor is formed, or the like can be used. Since the insulating layer 130 is in contact with the oxide semiconductor layer 144, it is preferable that at least a stoichiometric amount of oxygen is present in the film (bulk) of the insulating layer 130. For example, when a hafnium oxide film is used for the insulating layer 130, a film of SiO 2 + a (note, α > 0) is used. By using such an insulating layer 130, oxygen can be supplied to the oxide semiconductor layer 144, so that characteristics can be improved. The thickness of the oxide semiconductor layer 144 is set to be 1 nm or more and 100 nm or less, and a sputtering method, an MB E (Molecular Beam Epitaxy) method, a CVD method, a pulsed laser deposition method, or an ALD (Atomic Layer) can be suitably used. Deposition: atomic layer deposition method, coating -11 - 201236160 method, printing method, etc. Further, it is also possible to use a sputtering apparatus which performs film formation in a state in which a plurality of substrate surfaces are disposed substantially perpendicular to the surface of the sputtering target, that is, a so-called CP blasting system (Columnar Plasma Sputtering system) The oxide semiconductor layer 144 is formed. The material of the oxide semiconductor layer 144 contains at least one element selected from the group consisting of In, Ga, Sn, and Zn. For example, an In-Sn-Ga-Zn-antimony-based oxide semiconductor of a quaternary metal oxide; an In-Ga-Ζη-antimony-based oxide semiconductor of a ternary metal oxide, and an in-Sn-Zn- may be used. Cerium-based oxide semiconductor, In-Al-Ζη-Ο-based oxide semiconductor, Sn-Ga-Zn-0-based oxide semiconductor, Al-Ga-Ζη-Ο-based oxide semiconductor, Sn-Al_Zn-Ο-type oxidation Semiconductors; ΐη-Ζη-0-type oxide semiconductors of binary metal oxides, Sn-Zn-germanium-based oxide semiconductors, Ai-zn-o-based oxide semiconductors, Zn-Mg-germanium-based oxide semiconductors, Sn -Mg-O-based oxide semiconductor, In-Mg-germanium-based oxide semiconductor, In-Ga-antimony-based oxide semiconductor; and In-cerium-based oxide semiconductor of unit metal oxide, Sn-0-based oxide semiconductor , Zn-germanium-based oxide semiconductors, and the like. Further, the oxide semiconductor may contain an element other than In, Ga, Sn, or Zn, for example, SiO 2 . Further, it is preferable to have aluminum (A1) as a stabilizer. In addition, 'as another stabilizer' may have lanthanide lanthanum (La), cerium (Ce), praseodymium (Pr), yttrium (Nd), yttrium (Sm), yttrium (Eu), I (Gd), yttrium One or more of (Tb), 镝 (Dy), 鈥 (Ho), bait (Er), money (Tm), mirror (Yb), and key (Lu). For example, an In-Ga-Zn-antimony-based oxide semiconductor refers to an oxide semiconductor having indium (In ), -12 to 201236160 gallium (Ga), and zinc (Zn), and the ratio of In' Ga and Zn is not limited. Further, a metal element other than In, Ga, or Ζη may be contained. Further, as the oxide semiconductor layer, a film represented by a chemical formula of ΙπΜ03 (ZnO) m (m > 0) can be used. Here, Μ represents one or more metal elements selected from the group consisting of Zn, Ga, A1, Μη, and Co. For example, as μ, there are Ga, Ga and Al, Ga and Μη, Ga and Co, and the like. In addition, when a material of Ιη-Ζη-0 is used as an oxide semiconductor, the composition ratio of the target used is set such that the atomic ratio is In:Zn = 5〇:1 to 1:2 (converted to moir The ratio is ιη2〇3: Ζη〇 = 25:1 to 1:4), preferably Ιη: Ζη = 20:1 to 1: 1 (converted to the molar ratio is

In203:ZnO=l〇:l 至 1:2)，更佳爲 ΐη:Ζη=15:1 至 1.5:1 (換 算爲旲耳數比則爲Iri2〇3:ZnO=15:2至3:4)。例如，作爲 用來形成Ιη-Ζη-Ο類氧化物半導體的靶材，當原子數比爲 I η: Ζ η : Ο = X: Y : Ζ 時，Ζ > 1 .5 X + Υ。 作爲氧化物半導體層144的材料，使用包含in且具 有c軸配向的結晶氧化物半導體較佳。作爲得到具有^軸 配向的結晶氧化物半導體的方法，可以舉出三個方法：第 一個方法是藉由將成膜溫度設定爲400°C以上且45(TC以 下形成氧化物半導體層1 44 ’並沿著圖2 A所示的箭頭的 方向進行c軸配向；第二個方法是在形成薄的膜之後，進 行200C以上且700C以下的加熱處理，並沿著圖2B所示 的箭頭的方向進行c軸配向；第三個方法是在形成第一層 薄的膜之後’進行200 °C以上且700。(：以下的加熱處理， -13- 201236160 然後形成第二層，並沿著圖2C所示的箭頭的方向進行c 軸配向。 如圖2A、圖2B以及圖2C所示，不管採用上述哪一 種方法，都可以使結晶在垂直於氧化物半導體層144的表 面的凹凸的方向上生長，從而可以得到實現了 c軸向的結 晶氧化物半導體。 接著，以與氧化物半導體層144上接觸的方式形成用 作源極電極或汲極電極的電極142a、142b。電極142a、 電極14 2b可以使用金屬材料諸如鉬、鈦、钽、鎢、鋁、 銅、鉻、鈸、銃等或以上述金屬材料爲主要成分的合金材 料形成。 另外，爲了保護電極142a、142b，形成絕緣層143a 、143b。接著，使用 CMP ( Chemical Mechanical Polishing :化學機械拋光）等進行平坦化處理。當進行該 平坦化處理時，絕緣層143a、143b用作緩衝層而防止電 極142a、142b被削掉。 接著，形成通道長度方向的元件隔離用溝槽和通道寬 度方向的元件隔離用溝槽。這些元件隔離用溝槽既可以採 用相連的頂面圖案形狀，又可以採用彼此獨立的頂面圖案 形狀。在本實施方式中，藉由形成溝槽來分離氧化物半導 體層，所以在圖1C中採用相連的頂面圖案形狀（格子狀 )作爲這些的溝槽圖案。當形成通道寬度方向的元件隔離 用溝槽時，還可以分離電極142a和電極142b。另外，對 形成元件隔離用溝槽的時序沒有特別的限制。另外，只要 •14- 201236160 可以充分地分離元件，元件隔離用溝槽的深度就不限定爲 與閘極電極用溝槽的底面的水平位置相同的深度。藉由使 元件隔離用溝槽的底面的水平位置深於閘極電極用溝槽的 底面的水平位置，可以確實地分離元件。 接著，形成覆蓋氧化物半導體層144的一部分、用作 源極電極或汲極電極的電極142a及l42b、絕緣層143a及 143b的閘極絕緣層146。另外，在通道長度方向的元件隔 離用溝槽的內壁及底面、在通道寬度方向的元件隔離用溝 槽的內壁及底面也形成閘極絕緣層146。 將閘極絕緣層146的厚度設定爲lnm以上100nm以 下，並可以適當地利用濺射法、Μ B E法、C V D法、脈衝 雷射沉積法、ALD法、塗敷法、印刷法等。另外，還可以 使用在大致垂直於濺射靶材表面設置多個基板表面的狀態 下進行成膜的濺射裝置，即所謂的CP濺射裝置形成閘極 絕緣層1 46。 閘極絕緣層1 46可以使用如下材料形成：氧化矽膜： 氧化鎵膜；氧化鋁膜；氮化矽膜；氧氮化矽膜；氧氮化鋁 膜；氮氧化矽膜。較佳的是，閘極絕緣層146在接觸於氧 化物半導體層144的部分含有氧。尤其是，與氧化物半導 體層144接觸的絕緣膜較佳爲在其膜中（塊中）至少有超 過化學計量比的量的氧。例如，當將氧化矽膜用於閘極絕 緣層146時，使用Si02 + «(注意，α>〇)。在本實施方式 中，將Si02 + a (注意，α>0 )的氧化矽膜用於閘極絕緣層 146»藉由將這種氧化矽膜用於閘極絕緣層146，可以對氧 -15- 201236160 化物半導體層1 44供應氧，從而可以提高特性。並且，較In203: ZnO=l〇:l to 1:2), more preferably ΐη:Ζη=15:1 to 1.5:1 (Iri2〇3: ZnO=15:2 to 3:4 in terms of the ratio of the ears to the ear) ). For example, as a target for forming a Ιη-Ζη-Ο-type oxide semiconductor, when the atomic ratio is I η: Ζ η : Ο = X: Y : Ζ, Ζ > 1.5×x Υ. As the material of the oxide semiconductor layer 144, a crystalline oxide semiconductor containing in and having a c-axis alignment is preferably used. As a method of obtaining a crystalline oxide semiconductor having an axial alignment, there are three methods: the first method is to form an oxide semiconductor layer 1 44 by setting a film formation temperature to 400 ° C or more and 45 (TC or less). 'and performs c-axis alignment along the direction of the arrow shown in FIG. 2A; the second method is to perform heat treatment of 200 C or more and 700 C or less after forming a thin film, and along the arrow shown in FIG. 2B The direction is c-axis alignment; the third method is to perform 200 ° C or more and 700 after forming the first thin film. (: The following heat treatment, -13 - 201236160 and then form the second layer, and along the figure The c-axis alignment is performed in the direction of the arrow indicated by 2C. As shown in Figs. 2A, 2B, and 2C, regardless of which of the above methods is employed, the crystal can be made in the direction perpendicular to the unevenness of the surface of the oxide semiconductor layer 144. Growth, thereby obtaining a crystalline oxide semiconductor in which c-axis is realized. Next, electrodes 142a and 142b serving as source or drain electrodes are formed in contact with the oxide semiconductor layer 144. Electrode 142a, electrode 14 2b may be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, niobium, tantalum, or the like, or an alloy material containing the above metal material as a main component. Further, in order to protect the electrodes 142a, 142b, an insulating layer is formed. 143a and 143b. Next, planarization treatment is performed using CMP (Chemical Mechanical Polishing) or the like. When the planarization treatment is performed, the insulating layers 143a and 143b function as a buffer layer to prevent the electrodes 142a and 142b from being scraped off. Next, trenches for element isolation in the channel length direction and trenches for element isolation in the channel width direction are formed. These trenches for element isolation may have either a connected top pattern shape or a top pattern shape independent of each other. In the present embodiment, since the oxide semiconductor layer is separated by forming the trenches, the connected top surface pattern shape (lattice shape) is used as the groove pattern in FIG. 1C. When the element width in the channel width direction is formed In the case of the trench, the electrode 142a and the electrode 142b may be separated. In addition, there is no special timing for forming the trench for element isolation. In addition, as long as the device can sufficiently separate the components, the depth of the trench for element isolation is not limited to the same depth as the horizontal position of the bottom surface of the trench for the gate electrode. The horizontal position of the bottom surface is deeper than the horizontal position of the bottom surface of the gate electrode trench, and the element can be reliably separated. Next, a portion of the oxide semiconductor layer 144 is covered, and the electrode 142a serving as a source electrode or a drain electrode is formed. L42b, the gate insulating layer 146 of the insulating layers 143a and 143b. The inner wall and the bottom surface of the trench for element isolation in the channel length direction, and the inner and bottom surfaces of the trench for element isolation in the channel width direction also form a gate. A pole insulating layer 146. The thickness of the gate insulating layer 146 is set to be 1 nm or more and 100 nm or less, and a sputtering method, a Μ B E method, a C V D method, a pulsed laser deposition method, an ALD method, a coating method, a printing method, or the like can be suitably used. Further, it is also possible to use a sputtering apparatus which performs film formation in a state where a plurality of substrate surfaces are provided substantially perpendicularly to the surface of the sputtering target, that is, a so-called CP sputtering apparatus forms the gate insulating layer 146. The gate insulating layer 1 46 may be formed using a yttrium oxide film: a gallium oxide film; an aluminum oxide film; a tantalum nitride film; a yttrium oxynitride film; an aluminum oxynitride film; Preferably, the gate insulating layer 146 contains oxygen in a portion contacting the oxide semiconductor layer 144. In particular, the insulating film in contact with the oxide semiconductor layer 144 preferably has at least a stoichiometric amount of oxygen in its film (in the block). For example, when a hafnium oxide film is used for the gate insulating layer 146, SiO 2 + « (note, α > 〇) is used. In the present embodiment, a yttria film of SiO 2 + a (note, α > 0 ) is used for the gate insulating layer 146 » by using this yttrium oxide film for the gate insulating layer 146, it is possible to treat the oxygen-15 - 201236160 The compound semiconductor layer 1 44 supplies oxygen, so that characteristics can be improved. And, more

I 佳的是，閘極絕緣層1 46考慮到所製造的電晶體的尺寸或 閘極絕緣層146的臺階覆蓋性來形成。 另外，藉由作爲閘極絕緣層146的材料使用如下 hi gh-k材料可以降低閘極洩漏電流：氧化給；氧化釔；矽 酸鈴（HfSixOy(x>0、y>〇)):添加有氮的矽酸铪（ HfSixOyNz ( x>0、y>0、z>0));鋁酸給（HfAlxOy ( x>〇 、y>〇))等。另外，閘極i絕緣層146既可以採用單層結 構，又可以採用疊層結構。 然後，以塡充閘極電極用溝槽的方式在閘極絕緣層 146上形成閘極電極148a。閘極電極148a可以使用鉬、 鈦、钽、鎢、鋁、銅、鉻、鈸、銃等金屬材料或以上述金 屬材料爲主要成分的合金材料形成。閘極電極148a既可 以採用單層結構，又可以採用疊層結構。 作爲接觸於閘極絕緣層146的閘極電極148a的一層 ，使用含有氮的金屬氧化物。明確而言，使用含有氮的 In-Ga-Zn-Ο膜、含有氮的In-Sn-Ο膜、含有氮的In-Ga-0 膜、含有氮的Ιη-Ζπ-0膜、含有氮的Sn-0膜、含有氮的 In-Ο膜、金屬氮化膜（InN、SnN等）。這些膜具有5電 子伏特的功函數，較佳爲具有5.5電子伏特以上的功函數 。當將這些膜用於閘極電極時，可以使電晶體的臨界電壓 向正方向漂移，從而可以實現所謂的常截止的切換元件。 當完成在閘極電極用溝槽中形成閘極電極1 48a的步 驟時，溝槽結構的電晶體1 62也就形成了。 -16- 201236160 接著，形成覆蓋閘極電極148a、148b的絕緣層149。 絕緣層M9使用臺階覆蓋性良好的絕緣膜較佳。絕緣層 1 49可以使用如下材料形成：氧化矽膜；氧化鎵膜；氧化 鋁膜；氮化矽膜；氧氮化矽膜；氧氮化鋁膜；氮氧化矽膜 。在本實施方式中，將氧化鋁膜用作絕緣層I49的材料。 在圖1A及圖1B中，以與氧化物半導體層ΙΟ的側面接觸 的方式形成閘極絕緣層146，而且形成絕緣層149。從而 ，在本實施方式中，藉由使用Si02 + a(注意，α>0)的氧 化矽膜覆蓋氧化物半導體層1 4 4的側面並使用氧化鋁膜覆 蓋氧化矽膜，來防止在氧化矽膜中的氧擴散且穿過絕緣層 149 ° 在形成絕緣層149之後，藉由CVD法等形成用來塡 充元件隔離用溝槽的絕緣層150。藉由在元件隔離用溝槽 中塡充絕緣層150，來形成元件隔離區161、165。另外， 藉由在形成絕緣層150之前在元件隔離用溝槽中層疊閘極 絕緣層146、絕緣層149，可以使由絕緣層150塡充的區 域變小，而可以順利地將絕緣層1 5 0塡充到元件隔離用溝 槽中。然後，使用CMP等進行平坦化處理來得到圖1 Α及 圖1 B所示的結構。 此外，如圖1 B所示，在電晶體1 62的閘極電極1 4 8 a 與相鄰的電晶體163的閘極電極148b之間也塡充有絕緣 層1 50，來實現防止在閘極電極之間產生短路。另外，如 圖1 A所示，在用作電晶體1 62的源極電極或汲極電極的 電極與用作在通道長度方向上相鄰的電晶體的源極電極或 -17- 201236160 汲極電極的電極之間也塡充有絕緣層1 50，以防止源極電 極或汲極電極產生短路。 由於沿著溝槽的內壁而形成有電晶體的通道，因此即 使通道形成區不平坦也可以使載子沿著結晶氧化物半導體 層（C A A C )的I η - Ο -1 η - Ο順利地流過。在本實施方式中， 以接觸於深度爲〇.4μιη的溝槽的內壁的方式形成氧化物半 導體層144，因此通道長度大約爲0.8 μπι以上。藉由使通 道長度爲0.8 μιη以上，可以實現常截止的電晶體，也可以 防止產生短通道效應。另外，藉由採用溝槽結構，可以縮 小電晶體的平面面積，從而可以實現高整合化。 實施方式2 圖3Α和圖3Β示出使用圖1Α至圖1C所示的電晶體 162的半導體裝置的一例，該半導體裝置即使在沒有電力 供應的情況下也能夠保持儲存內容，並且對寫入次數也沒 有限制。 電晶體1 62的截止電流小，所以藉由使用這種電晶體 能夠長期保持儲存內容。換言之，可以使更新工作的頻率 極低，所以可以充分降低耗電量。 圖3Α示出半導體裝置的剖面的一例。 圖3Α所示的半導體裝置在其下部具有使用第一半導 體材料的電晶體160，並且在其上部具有使用第二半導體 材料的電晶體1 62。注意，電晶體1 62與實施方式1所說 明的電晶體1 62爲同一電晶體，所以在圖3 Α和圖3Β中， -18- 201236160 對與圖1A相同的部分使用相同的元件济 這裏’第一半導體材料和第二半導 的材料。例如，可以將氧化物半導體以 矽等）用作第一半導體的材料，而將氧 二半導體的材料。使用氧化物半導體以 谷易進彳了闻速工作。另一方面，使用氧 體由於其特性而能夠長期保持電荷。 另外，雖然是以上述電晶體都是η 況來進行說明，但是當然也可以使用ρ 外，由於所公開的發明的技術本質在於 用於電晶體1 62以保持資訊，因此不需 具體結構如用於半導體裝置的材料或半 限定於在此所示的結構。 圖3Α所示的電晶體160具有：設 料（例如，矽等）的基板1〇〇中的通道 持通道形成區116的方式設置的雜質區 區120的金屬化合物區124 ;設置在通 閘極絕緣層1 08 ;以及設置在閘極絕緣) 極 1 1 0。 電晶體160的金屬化合物區124的 126。在此，電極126用作電晶體160 電極。另外，在基板1〇〇上以圍繞電晶 有元件隔離絕緣層’並且以覆蓋電晶體 絕緣層130。另外，爲了實現高整合化 ί號而進行說明。 體材料較佳爲不同 外的半導體材料（ 化物半導體用作第 外的材料的電晶體 化物半導體的電晶 通道型電晶體的情 通道型電晶體。此 =將氧化物半導體 要將半導體裝置的 導體裝置的結構等 置在包含半導體材 形成區1 1 6 ;以夾 120 ;接觸於雜質 道形成區1 1 6上的 罾1 0 8上的閘極電 一部分連接著電極 的源極電極或汲極 體160的方式設置 1 60的方式設置有 ，較佳的是，如圖 -19* 201236160 3 A所示電晶體丨60不具有側壁絕緣層。然而，在重視電 晶體1 60的特性的情況下，也可以在閘極電極1 1 〇的側面 設置側壁絕緣層，並設置包含雜質濃度不同的區域的雜質 12 0 ° 如圖3A所示，電晶體162是具有氧化物半導體層 144的溝槽結構的電晶體》 在此，較佳的是，氧化物半導體層144藉由被充分地 去除氫等雜質或被供應足夠的氧而被高純度化。明確而言 ，例如，將氧化物半導體層144的氫濃度設定爲5xl019原 子/cm3以下，較佳的是，設定爲5xl018原子/cm3以下， 更佳的是，選設定爲5xl017原子/cm3以下。另外，上述 氧化物半導體層144中的氫濃度是利用二次離子質譜分析 法（Secondary Ion Mass Spectroscopy, SIMS)測量的。如 此，在氫濃度被充分降低而被高純度化，並藉由被供給足 夠的氧來降低起因於氧缺乏的能隙中的缺陷能階的氧化物 半導體層144中，載子濃度低於1x1012/cm3，較佳爲低於 lxiou/cm3，更佳爲低於1.45xl01Q/cm3。另外，例如，室 溫（25 °C )下的截止電流（在此，每單位通道寬度（1 μπι )的値）爲ΙΟΟζΑ ( ΙζΑ (仄普托安培）爲1χ10·21Α )以 下，較佳爲1 〇ζΑ以下。如此，藉由採用i型化（本質化 )或實質上i型化的氧化物半導體，可以得到截止電流特 性極爲優越的電晶體162。 另外，在圖3 A所示的電晶體162中，爲了抑制由於 微型化而產生的元件之間的洩漏，設置元件隔離區161。 -20- 201236160 而且，雖然使用被加工爲小於由元件隔離區161圍繞的區 域的島狀的氧化物半導體層144，但是如實施方式1所說 明’也可以採用在形成元件隔離用溝槽之前氧化物半導體 層144沒有被加工爲島狀的結構。在不將氧化物半導體層 1 4 4加工爲島狀的情況下，可以防止由於加工時的蝕刻氧 化物半導體層144受到污染。當然，當不將氧化物半導體 層加工爲島狀時，可以減少製程數。另外，當使用被加工 爲小於由元件隔離區161圍繞的區域的島狀的氧化物半導 體層144時，不需要藉由形成元件隔離用溝槽來分離氧化 物半導體層，所以可以使元件隔離用溝槽的底面的水平位 置淺於閘極電極用溝槽。或者，可以減小用於形成元件隔 離用溝槽的總面積。 在電晶體1 62上設置有絕緣層1 5 1，在絕緣層1 5 1上 設置有電連接於閘極電極148a的電極153。並且，電極 153上設置有絕緣層152。並且，在設置在閘極絕緣層146 、絕緣層150、絕緣層Ml、絕緣層152等中的開口中設 置有電極154，在絕緣層152上形成有連接於電極154的 佈線156。另外，在圖3A中，雖然使用電極126及電極 154連接金屬化合物區124、電極142b和佈線156，但是 所公開的發明不侷限於此。例如，也可以使電極1 42b直 接接觸於金屬化合物區124。或者，也可以使佈線156直 接接觸於電極142b。 接著，圖3B示出對應於圖3A的電路結構的一例。注 意，在電路圖中，爲了表示使用氧化物半導體的電晶體， -21 - 201236160 有時附上“ os”的符號。 在圖3B中，第一佈線（1st Line )與電晶體160的源 極電極電連接，第二佈線（2nd Line)與電晶體160的汲 極電極電連接。另外，第三佈線（3rd Line )與電晶體 162的源極電極和汲極電極中的一方電連接，第四佈線（ 4th Line )與電晶體162的閘極電極電連接。並且，電晶 體160的閘極電極以及電晶體162的源極電極和汲極電極 中的另一方與電容器164的一方的電極電連接，第五佈線 (5th Line)與電容器164的另一方的電極電連接》 電容器164可以藉由與電晶體160或電晶體162相同 的製程形成一對電極和夾持在該一對電極之間的成爲介電 質的絕緣層來形成。另外，電容器164不侷限於藉由與電 晶體1 60或電晶體1 62相同的製程形成，也可以將電容器 164的層另行設置在電晶體162的上方，。例如，也可以將 溝槽型電容器或疊層型電容器另行形成在電晶體162的上 方或電晶體1 60的下方，以進行三維層疊而實現高整合化 〇 在圖3B所示的半導體裝置中，藉由發揮能夠保持電 晶體1 60的閘極電極的電位的特點，可以如下所示那樣進 行資訊的寫入、保持以及讀出。 對資訊的寫入及保持進行說明。首先，將第四佈線的 電位設定爲使電晶體1 62成爲導通狀態的電位，來使電晶 體1 62成爲導通狀態。由此，對電晶體1 60的閘極電極及 電容器1 64施加第三佈線的電位。也就是說，對電晶體 -22- 201236160 加igh 施HI 將、 ,荷 此電 在平 。 電 )W 人L0 寫 ( 爲 荷稱 電下 的以 定C 指荷 加電 施種 極兩 電的 極位 閘電 的的 ο 同 16不 電平電荷）中的任一方施加到電晶體1 6 0的閘極電極。然 後，藉由將第四佈線的電位設定爲使電晶體162成爲截止 狀態的電位，來使電晶體1 62成爲截止狀態，而保持施加 到電晶體1 6 0的閘極電極的電荷（保持）。 另外，也可以設置背閘極電極，較佳的是，藉由對背 閘極電極施加電壓來確實地實現電晶體162的常截止化。 本實施方式可以與實施方式1適當地組合。 實施方式3 在本實施方式中’關於使用圖1Α和圖1Β所示的電晶 體162的半導體裝置’參照圖4對與實施方式2所示的結 構不同的結構進行說明。該半導體裝置即使在沒有電力供 應的情況下也能夠保持儲存內容，並且對寫入次數也沒有 限制。 圖4所示的半導體裝置在其下部具有使用第一半導體 材料的電晶體350’並且在其上部具有使用第二半導體材 料的電晶體162。注意，雖然在上部及下部的半導體材料 上設置有多個電晶體’但是以電晶體350及電晶體〗62爲 代表而進行說明。另外’沿著線Β 1 - Β 2被切割的圖4相當 於垂直於電晶體的通道長度方向的剖面圖。 這裏’第一半導體材料和第二半導體材料較佳爲不同 的材料。例如，可以將氧化物半導體以外的半導體材料（ -23- 201236160 矽等）用作第一半導體材料，並將氧化物半導體用作第二 半導體材料。使用氧化物半導體以外的材料的電晶體容易 進行高速工作。另一方面，使用氧化物半導體的電晶體由 於其特性而能夠長期保持電荷。 另外’上部的使用第二半導體材料的電晶體162與實 施方式1及實施方式2所記載的電晶體162是同一電晶體 ’所以在圖4中，對與圖1 A相同的部分使用相同的元件 符號而省略詳細說明。 這裏，對下部的使用第一半導體材料的電晶體350進 行說明。 電晶體350具有：半導體基板310;閘極絕緣層314 :半導體層3 16 ;導電層3 1 8 ;保護絕緣層320 ;側壁絕緣 層322;雜質區324;以及絕緣層326。另外，半導體層 316及導電層318用作閘極電極，並且雜質區324用作源 極區或汲極區。 另外，與電晶體 3 50鄰接有 STI ( Shallow Trench Isolation:淺溝槽隔離）區312。 作爲STI區312，首先，在半導體基板310上的所希 望的區域形成保護絕緣膜並進行蝕刻來形成溝槽（也成爲 槽）。在形成溝槽之後，藉由將絕緣介電薄膜塡埋於溝槽 中來形成STI區312。絕緣介電薄膜可以使用氧化矽膜、 氮化矽膜等。 接著，進行電晶體3 5 0的詳細說明。作爲電晶體3 5 0 的閘極絕緣層3 1 4，在將絕緣膜形成在形成有STI區3 1 2 -24 - 201236160 的半導體基板310上之後，對所希望的位置進行構圖和蝕 刻，從而在半導體基板310上形成與STI區312不同深度 的溝槽。然後，在氧氣分下進行加熱處理來將溝槽中的半 導體基板3 1 0氧化，而可以形成閘極絕緣層3 1 4。 在形成閘極絕緣層314之後，使用LPCVD法等形成 矽膜。另外，對該矽膜進行n+、p +的摻雜處理或加熱處理 等來形成作爲所謂的多晶矽的具有高導電性的半導體層。 然後，在該半導體層上藉由濺射法等來形成金屬膜。金屬 膜可以適當地使用：鎢；鈦；鈷；鎳；含有鎢、鈦、鈷、 鎳的合金膜；金屬氮化膜；矽化物膜等。然後，藉由對該 金屬膜上的所希望的區域進行構圖和蝕刻來形成導電層 318。另外，藉由將導電層318用作遮罩而對半導體層進 行蝕刻，可以形成半導體層3 1 6。另外，導電層3 1 8和半 導體層3 1 6用作電晶體3 5 0的閘極電極。 接著，在導電層318上形成保護絕緣層320。保護絕 緣層3 20可以藉由使用電漿CVD法等形成氧化矽膜、氮 化矽膜等，並且對所希望的區域進行構圖和蝕刻處理來形 成。 接著’藉由以覆蓋半導體基板310及保護絕緣層320 的方式藉由電漿CVD法等形成氮化矽膜並進行回蝕來可 以形成側壁絕緣層3 2 2。 接著’將保護絕緣層3 20及側壁絕緣層3 22用作遮罩 而進行摻雜處理來形成雜質區324。另外，作爲摻雜物可 以使用硼或磷等，並且作爲雜質區324，可以藉由所使用 -25- 201236160 的摻雜物適當地形成n +區、p +區等。另外，雜質區324用 作電晶體3 50的源極區或汲極區。 接著，以覆蓋雜質區3 24、保護絕緣層320以及側壁 絕緣層322的方式形成絕緣層3 26。絕緣層326可以使用 藉由電漿CVD法等來形成的氧化矽膜等。 接著，在絕緣層3 26的所希望的區域中設置開口部並 形成電連接於雜質區324的連接電極325及連接電極331 。另外，在形成連接電極325及連接電極331之後，可以 進行使絕緣層326、連接電極325以及連接電極331的表 面平坦化的CMP處理等。 接著，在絕緣層326、連接電極325以及連接電極 331上使用濺射法等形成導電膜並對所希望的區域進行構 圖和蝕刻來形成電極328及電極332。電極328及電極 332的材料可以適當地使用鎢、銅、鈦等^ 接著，在絕緣層326、電極328以及電極332上形成 絕緣層3 2 9 »絕緣層3 2 9可以使用與絕緣層3 2 6同樣的材 料及方法形成。 藉由如上製程可以形成設置有使用第一半導體材料的 電晶體3 50的半導體基板310。 在此，對下部的使用第一半導體材料的電晶體3 50與 上部的使用第二半導體材料的電晶體162的連接關係進行 說明。 電晶體350藉由雜質區324、連接電極325、電極328 、連接電極330電連接到電晶體162。另一方面，電晶體 -26- 201236160 350藉由雜質區324、連接電極331、電極332'連接電極 334、電極336、連接電極338電連接到佈線156。 另外，電晶體3 50的閘極電極（即半導體層3 1 6及導 電層318)電連接到電晶體162的源極電極。注意，在圖 4中，電晶體3 50的閘極電極與電晶體162的源極電極的 連接未圖示但在三維方向上是連接著的。 如上所述，形成在上部的多個記憶單元由使用氧化物 半導體的電晶體形成。由於使用氧化物半導體的電晶體的 截止電流小，因此藉由使用這種電晶體，能夠長期保持儲 存內容。換言之，可以使更新工作的頻率極低，所以可以 充分降低耗電量。另一方面，在週邊電路中使用氧化物半 導體以外的半導體材料。作爲氧化物半導體以外的半導體 材料例如可以使用矽、鍺、矽鍺、碳化矽或砷化鎵等，使 用單晶半導體是較佳的。使用這種半導體材料的電晶體能 夠進行充分高速的工作。從而，藉由利用使用氧化物半導 體以外的材料的電晶體，能夠順利實現被要求高速工作的 各種電路（邏輯電路、驅動電路等）。 如上所述，藉由將具備使用氧化物半導體以外的材料 的電晶體（換言之，能夠進行充分高速的工作的電晶體） 的週邊電路以及具備使用氧化物半導體的電晶體（作更廣 義解釋，其截止電流十分小的電晶體）的儲存電路設置爲 一體，能夠實現具有新穎特徵的半導體裝置。另外，藉由 採用週邊電路和儲存電路的疊層結構，可以實現半導體裝 置的整合化。 -27- 201236160 本實施方式可以與其他實施方式所記載的結構適胃丈 也 組合而實施。 實施方式4 在本實施方式中，關於使用圖1A和圖1B所示的電晶 體162的半導體裝置，參照圖5A至圖6對與實施方式2 及實施方式3所示的結構不同的結構進行說明。該半導體 裝置即使在沒有電力供應的情況下也能夠保持儲存內容’ 並且對寫入次數也沒有限制。 圖5A示出半導體裝置的電路結構的一例，圖5B是示 出半導體裝置的一例的示意圖。首先對圖5A所示的半導 體裝置進行說明，接著對圖5B所示的半導體裝置進行說 明。 在圖5A所示的半導體裝置中，位元線BL與電晶體 162的源極電極或汲極電極電連接，字線 WL與電晶體 162的閘極電極電連接，並且電晶體162的源極電極或汲 極電極與電容器254的第一端子電連接。 使用氧化物半導體的電晶體1 62具有截止電流極小的 特徵。因此，藉由使電晶體162成爲截止狀態，可以在極 長時間儲存電容器2 54的第一端子的電位（或累積在電容 器254中的電荷）》另外’使用氧化物半導體的電晶體 162還具有不容易呈現短通道效應的優點。 接著，說明對圖5所示的半導體裝置（記憶單元25〇 )進行資訊的寫入及保持的情況。 -28- 201236160 首先，藉由將字線WL的電位設定爲使電晶體162成 爲導通狀態的電位，來使電晶體1 62成爲導通狀態。由此 ，將位元線BL的電位施加到電容器254的第一端子（寫 入）。然後，藉由將字線WL的電位設定爲使電晶體1 62 成爲截止狀態的電位，來使電晶體1 62成爲截止狀態，由 此儲存電容器254的第一端子的電位（保持）。 由於電晶體1 62的截止電流極小，所以能夠長期儲存 電容器2 54的第一端子的電位（或累積在電容器中的電荷 )° 接著，對資訊的讀出進行說明。當電晶體1 62成爲導 通狀態時，處於浮動狀態的位元線BL與電容器254導通 ，於是，在位元線BL與電容器254之間電荷被再次分配 。其結果，位元線BL的電位發生變化。位元線BL的電 位的變化量根據電容器254的第一端子的電位（或累積在 電容器2 54中的電荷）而取不同的値。 例如，在以V爲電容器254的第一端子的電位，以C 爲電容器254的電容，以CB爲位元線BL所具有的電容 成分（以下也稱爲位元線電容），並且以VB0爲電荷被再 次分配之前的位元線BL的電位的條件下，電荷被再次分 配之後的位元線BL的電位成爲（CB*VB0 + C*V)/(CB + C)。 因此，作爲記憶單元2 50的狀態，當電容器254的第一端 子的電位爲VI和 V0 ( VI > V0 )的兩個狀態時，保持電 位VI時的位元線BL的電位（ = (CB*VB0 + C*V1)/(CB + C) )高於保持電位 V0時的位元線 BL的電位（=( -29- 201236160 CB * VBO + C* V0)/(CB + C))。 並且，藉由比較位元線BL的電位與指定的電位，可 以讀出資訊。 如此，圖5A所示的半導體裝置可以利用電晶體1 62 的截止電流極小的特徵長期保持累積在電容器254中的電 荷。換言之，因爲不需要進行更新工作，或者，可以使更 新工作的頻率極低，所以可以充分降低耗電量。另外，即 使在沒有電力供給的情況下也可以長期保持儲存內容。 接著對圖5B所示的半導體裝置進行說明。 圖5B所示的半導體裝置在其上部具備具有多個圖5A 所示的記億單元250的記憶單元陣列25 1作爲記憶元件， 在其下部具備用作使記憶單元陣列251工作的週邊電路 25 3 ° 藉由採用圖5B所示的結構，可以將週邊電路2 53設 置在記憶單元陣列251的正下方，從而可以實現半導體裝 置的微型化。 接著，參照圖6對圖5B所示的半導體裝置的具體結 構進行說明。 圖6所示的半導體裝置在其上部具有記憶單元45 2， 並且在其下部具有週邊電路400。下部的週邊電路400具 有使用第一半導體材料的電晶體450，並且在上部形成的 記憶單元452具有使用第二半導體材料的電晶體162。另 外，沿著線C 1-C2被切割的圖6相當於垂直於電晶體的通 道長度方向的剖面圖。 -30- 201236160 這裏，第一半導體材料和第二半導體材料較佳爲 的材料。例如，可以將氧化物半導體以外的半導體材 矽等）用作第一半導體材料，而將氧化物半導體作用 —半導體材料。使用氧化物半導體以外的材料的電晶 易進行高速工作。另一方面，使用氧化物半導體的電 由於其特性而能夠長期保持電荷。 另外，上部的使用第二半導體材料的電晶體162 施方式1至實施方式3所記載的電晶體162是同一電 ’所以在圖6中，對與圖1A相同的部分使用相同的 符號而省略詳細說明。這裏，對下部的使用第一半導 料的電晶體450進行說明》 圖6中的電晶體450具有：形成在包括半導體材 例如，矽等）的基板402中的通道形成區404 ;以夾 道形成區404的方式設置的雜質區406及高濃度雜 4〇8(將這些區域統稱爲雜質區）；接觸於高濃度雜 408的金屬化合物區410 ;形成在通道形成區404上 極絕緣層411;以接觸於閘極絕緣層411的方式設置 極電極412;電連接於雜質區的源極電極或汲極電極 以及源極電極或汲極電極418b。 在此，在閘極電極4 1 2的側面設置有側壁絕緣層 。此外，在基板402上以圍繞電晶體450的方式設置 件隔離絕緣層403，並且以覆蓋電晶體450的方式設 層間絕緣層420及層間絕緣層422。源極電極或汲極 418a以及源極電極或汲極電極418b藉由形成在層間 不同 料（ 作第 體容 晶體 與實 晶體 元件 體材 料（ 持通 質區 質區 的閘 的閘 418a 414 有元 置有 電極 絕緣 31 - 201236160 層420及層間絕緣層422中的開口電連接到金 41〇。換言之，源極電極或汲極電極418a以及 汲極電極418b藉由金屬化合物區410電連接 質區408及雜質區406。另外，爲了實現電晶1 合化等，有時不形成側壁絕緣層4 1 4。另外， 層422上設置有連接電極層424a、連接電極層 連接電極層424c。該連接電極層424a、連接獨 以及連接電極層424c電連接到電晶體450的 汲極電極418a以及源極電極或汲極電極418b 絕緣層425覆蓋層間絕緣層422、連接電極層 電極層424b以及連接電極層424c來實現平坦{-連接電極層424c利用連接電極426電連接 。另外，電極42 8由與電晶體162的源極電極 同一個層形成。另外，佈線1 56利用連接電極 到電極428。藉由利用連接電極層424c、連接 電極428、連接電極43 0以及佈線1 56，可以 路400與記憶單元452之間的電連接等。 此外，圖6所示的半導體裝置例示藉由利 層424c、電極42 8連接記憶單元452和週邊電 構，但是不侷限於該結構。也可以在記憶單元 電路400之間設置兩個以上的佈線層及電極。 如上所述，在上部形成的記憶單元由使用 體的電晶體形成。由於使用氧化物半導體的電 電流小，因此藉由使用這種電晶體’能夠長期 屬化合物區 源極電極或 到高濃度雜 體45 0的整 在層間絕緣 424b以及 重極層424b 源極電極或 ，藉由使用 424a 、連接 匕。 到電極4 2 8 及汲極電極 430電連接 電極426、 實現週邊電 用連接電極 路400的結 4 5 2和週邊 氧化物半導 晶體的截止 保持儲存內 -32- 201236160 容。換言之，可以使更新工作的頻率極低， 降低耗電量。另一方面，在週邊電路中使用 以外的半導體材料。作爲氧化物半導體以外 例如可以使用矽、鍺、矽鍺、碳化矽或砷化 晶半導體是較佳的。使用這種半導體材料的 行充分高速的工作。從而，藉由利用使用氧 外的材料的電晶體，能夠順利實現被要求高 電路（邏輯電路、驅動電路等）。 如上所述，藉由將具有使用氧化物半導 的電晶體（換言之，能夠進行充分高速的工 的週邊電路以及具有使用氧化物半導體的電 義解釋，其截止電流十分小的電晶體）的儲 一體，能夠實現具有新穎特徵的半導體裝置 採用週邊電路和儲存電路的疊層結構，可以 置的整合化。 本實施方式可以與其他實施方式所記載 組合而實施。 實施方式5 在本實施方式中，參照圖10A至圖13 方式所說明的半導體裝置應用於行動電話、 電子書閱讀器等移動設備的例子進行說明。 在行動電話、智慧型手機、電子書閱讀 中’爲了暫時儲存影像資料而使用S rAM或 所以可以充分 氧化物半導體 的半導體材料 鎵等，使用單 電晶體能夠進 化物半導體以 速工作的各種 體以外的材料 作的電晶體） 晶體（作更廣 存電路設置爲 。另外，藉由 實現半導體裝 的結構適當地 對將上述實施 智慧型手機、 器等移動設備 DRAM。使用 -33- 201236160 SRAM或DRAM是因爲快閃記憶體應答速度慢而不適於處 理影像。另一方面，當將SRAM或DRAM用於影像資料的 暫時儲存時，有如下特徵。 如圖1 0A所示，在一般的SRAM中’一個記憶單元由 電晶體801至電晶體806的六個電晶體構成’並且由X解 碼器807和Y解碼器8 08驅動這些電晶體。電晶體803和 電晶體805以及電晶體804和電晶體806構成反相器，該 反相器能夠實現高速驅動。然而，由於一個電晶體由六個 電晶體構成，所以有記憶單元面積大的缺點。在將設計規 則的最小尺寸設定爲F的情況下，SRAM的記憶單元面積 —般爲100至150F2。因此，SRAM是各種記憶體中每個 位元的單價最高的。 另一方面，在DRAM中，如圖10B所示，記億單元 由電晶體811和儲存電容器812構成，並且由X解碼器 813和Y解碼器814驅動這些元件。由於一個單元由一個 電晶體和一個電容構成，所以所佔的面積小。DRAM的儲 存面積一般爲1 OF2以下。但是，DRAM需要一直進行更 新工作，因此即使在不進行改寫的情況下也消耗電力。 相對於此，上述實施方式所說明的半導體裝置的記憶 單元面積爲1 OF2左右，並且不需要頻繁的更新工作。從 而，能夠縮小記憶單元面積，還能夠降低耗電量。 另外’圖11是移動設備的方塊圖。圖11所示的移動 設備具有：RF電路901 ;模擬基帶電路9 02;數位基帶電 路903 :電池904 ;電源電路905 ;應用處理器906 ;快閃 -34- 201236160 記億體910;顯示器控制器911;儲存電路912; 913;觸控感應器919;聲頻電路917;以及鍵盤9: 顯示器913具有：顯示部914;源極驅動器915; 極驅動器 916。應用處理器 906具有：CPU ( Processing Unit:中央處理器）907; DSP (Digital Processor :數位信號處理器）908 ;以及介面 909 )。儲存電路912 —般由SRAM或DRAM構成，藉 述實施方式所說明的半導體裝置用於該部分，能夠 進行資訊的寫入和讀出，能夠長期保持儲存內容， 充分降低耗電量。 另外，圖12是將上述實施方式所說明的半導 用於顯示器的儲存電路950的例子。圖12所示的 路950具有：記憶體952;記憶體953;開關954 95 5 ;以及記憶體控制器951。另外，儲存電路950 :用來讀出及控制從信號線輸入的影像資料（輸入 料）、儲存在記憶體9 52及記憶體953中的資料（ 像資料）的顯示器控制器956;以及根據來自顯示 器956的信號來進行顯示的顯示器957。 首先，藉由應用處理器（未圖示）形成一個影 (輸入影像資料A)。該輸入影像資料A藉由開關 儲存在記億體952中。然後’將儲存在記憶體952 像資料（儲存影像資料A )藉由開關95 5及顯示器 956發送到顯示器957而進行顯示。 在輸入影像資料A沒有變化時，儲存影像資料 顯示器 18等。 以及閘 Central Signal (IF909 由將上 以高速 還能夠 體裝置 儲存電 ;開關 連接於 影像資 儲存影 器控制 像資料 954被 中的影 控制器 A —般 -35- 201236160 以30至6 OHz左右的週期從記憶體952藉由開關955由顯 示器控制器9 5 6讀出。 另外，例如在使用者進行了改寫畫面的操作時（即在輸 入影像資料A有變化時），應用處理器形成新的影像資料（輸 入影像資料B)。該輸入影像資料B藉由開關954被儲存 在記憶體953中。在該期間儲存影像資料A也繼續定期性 地藉由開關95 5從記憶體952被讀出。當在記憶體953中 儲存完新的影像（儲存影像資料B)時，由顯示器95 7的 下一個圖幀開始讀出儲存影像資料B，並且將該儲存影像 資料B藉由開關95 5及顯示器控制器956發送到顯示器 95 7而進行顯示。該讀出一直持續直到下一個新的影像資 料儲存到記憶體952中。 如上所述，藉由由記億體952及記憶體95 3交替進行 影像資料的寫入和影像資料的讀出，來進行顯示器95 7的 顯示。另外，記億體952、記億體953不侷限於兩個不同的 記憶體，也可以將一個記憶體分割而使用。藉由將上述實 施方式所說明的半導體裝置用於記憶體95 2及記憶體953 ，能夠以高速進行資訊的寫入和讀出，能夠長期保持儲存 內容，還能夠充分降低耗電量。 另外，圖13是電子書閱讀器的方塊圖。圖13所示的 電子書閱讀器具有：電池1001 ;電源電路1 002 ;微處理 器1 003 ;快閃記億體1 004 ;聲頻電路1 005 ;鍵盤1 006 ; 儲存電路1 007;觸控面板1 008;顯示器1 009;以及顯示 器控制器1 0 1 0。 -36- 201236160 在此，可以將上述實施方式所說明的半導體裝置用於 圖13的儲存電路1007»儲存電路1 00 7具有暫時保持書籍 內容的功能。作爲該功能的例子，例如有使用者使用強調 功能的情況。使用者在看電子書閱讀器時，有時需要對某 個部分做標記》該標記功能被稱爲強調功能，即藉由改變 顯示顏色；劃下劃線；將文字改爲粗體字；改變文字的字 體等，來使該部分與周圍不一樣而突出表示。強調功能就 是將使用者所指定的部分的資訊儲存而保持的功能。當將 該資訊長期保持時，也可以將該資訊複製到快閃記憶體 1 0 04。即使在此情況下，也藉由採用上述實施方式所說明 的半導體裝置，而能夠以高速進行資訊的寫入和讀出，能 夠長期保持儲存內容，還能夠充分降低耗電量。 如上所述，本實施方式所示的移動設備安裝有根據上 述實施方式的半導體裝置。因此，能夠實現以高速進行資 訊的讀出、長期保持儲存內容且充分降低耗電量的移動設 備。 本實施方式所示的結構及方法等可以與其他實施方式 所記載的結構及方法等適當地組合而實施。 實施例1 本實施例中，爲了確認實施方式1所示的溝槽結構的 電晶體是否呈現短通道效應而進行計算。 另外，在計算中使用syn〇psys公司製造的裝置模擬 軟體 Sentaurus Device。 -37- 201236160 圖7A示出用來計算的結構及各個尺寸。閘極絕緣層 的厚度爲5ηηι，氧化物半導體層的厚度爲5nm，並且閘極 電極用的溝槽的深度爲〇·4μηι。圖7A示出溝槽的底部的 長度（通道長度方向的長度）爲90nm，且源極電極和汲 極電極之間的間隔（通道長度方向的長度）爲ll〇nm的溝 槽結構的電晶體。氧化物半導體層的材料使用In-Ga-Zn-0 類氧化物半導體（能隙爲3.15eV，電子親和力爲4.6eV， 電子遷移率爲l〇cm2/Vs)，接觸於氧化物半導體層的電極 (源極電極及汲極電極）的功函數爲4.6eV，並且閘極電 極的功函數爲5.5eV。圖7B示出對該溝槽結構的電晶體 的Vg-Id特性（Vds=l V，溫度爲27°C )進行計算的結果 另外，圖8A示出溝槽的底部的長度（通道長度方向 的長度）爲60nm，源極電極和汲極電極之間的間隔（通 道長度方向的長度）爲80nm的溝槽結構的電晶體。圖8B 示出除了溝槽的底部的長度及源極電極和汲極電極之間的 間隔以外與圖7B爲同樣條件的計算結果。 另外，圖9A示出溝槽的底部的長度（通道長度方向 的長度）爲3 0 n m，源極電極和汲極電極之間的間隔（通 道長度方向的長度）爲50nm的溝槽結構的電晶體。圖9B 示出除了溝槽的底部的長度及源極電極和汲極電極之間的 間隔以外與圖7B爲同樣條件的計算結果。 從計算結果可知：圖7 A、圖8 A以及圖9 A的結構的 所有電晶體的特性大致相等。各個電晶體的閾値（Vth ) -38- 201236160 爲0.8V ’ S値爲60mV/dec，都是理想的數値。 從這些計算結果可知：即使將源極電極和汲極電極之 間的間隔（通道長度方向的長度）縮短到5 0 n m，也可以 得到良好的電晶體特性，而沒有呈現閾値的負漂移或S値 的增大等短通道效應。 爲了比較，不使用溝槽結構的電晶體而使用平面型的 電晶體結構來進行了同樣的計算。當將源極電極和汲極電 極之間的間隔（通道長度方向的長度）縮短時，通道長度 也變短，而呈現閾値的負漂移或S値的增大等短通道效應 ，再者，還確認到對閘極施加負的偏壓時的洩漏電流（截 止電流）的增大。 與該用來比較的計算結果相比’圖7B、圖8B以及圖 9B的計算結果是理想的。藉由採用實施方式1所示的電 晶體結構，即使縮短源極電極和汲極電極之間的間隔（通 道長度方向的長度），由於有效的通道長度的變化小’所 以不會呈現短通道效應，從而可以抑制截止電流。其結果 ，能夠製造保持特性良好的記億單元。 【圖式簡單說明】 在圖式中： 圖1A至圖1C是示出本發明的一個方式的剖面圖及俯 視圖； 圖2A至圖2C是示出本發明的一個方式的剖面模式圖 -39- 201236160 圖3A和圖3B是示出本發明的一個方式的剖面圖及電 路圖； 圖4是示出本發明的一個方式的剖面圖； 圖5A和圖5B是示出本發明的一個方式的電路圖及示 意圖， 圖6是示出本發明的一個方式的剖面圖； 圖7A和圖7B是用於計算的結構剖面圖及計算結果； 圖8A和圖8B是用於計算的結構剖面圖及計算結果； 圖9A和圖9B是用於計算的結構剖面圖及計算結果； 圖10A和10B是示出本發明的一個方式的電路圖； 圖11是示出本發明的一個方式的可攜式設備的方塊 圖， 圖12是示出本發明的一個方式的半導體裝置的方塊 圖， 圖13是示出本發明的一個方式的電子書閱讀器的方 塊圖。 【主要元件符號說明】 100 :基板 108 :閘極絕緣層 1 1 〇 :閘極電極 1 1 6 :通道形成區 120 :雜質區 124 :金屬化合物區 -40- 201236160 1 26 :電極 1 3 0 :絕緣層 142a、 142b:電極 143a、 143b:絕緣層 144 :氧化物半導體層 1 4 6 :閘極絕緣層 148a、148b:閘極電極 1 4 9 :絕緣層 1 5 0 :絕緣層 1 5 1 :絕緣層 1 5 2 :絕緣層 1 53 :電極 154 :電極 1 5 6 :佈線 1 6 0 :電晶體 1 6 1 :元件隔離區 1 6 2 :電晶體 163 :電晶體 164 :電容器 1 6 5 :元件隔離區 25 0 :記憶單元 251 :記憶單元陣列 2 5 3 :週邊電路 2 54 :電容器 201236160 3 10： 3 12： 3 14： 3 16： 3 18： 320 ： 3 22 ： 324 ： 325 ： 3 26 : 3 2 8 ： 3 29 ： 3 3 0 ： 33 1: 3 3 2 ： 3 3 4 ： 3 3 6 ： 3 3 8 ： 3 5 0 ： 400 ： 402 ： 403 ： 404 ： 半導體基板 STI區 閘極絕緣層 半導體層 導電層 保護絕緣層 側壁絕緣層 雜質區 連接電極 絕緣層 電極 絕緣層 連接電極 連接電極 電極 連接電極 電極 連接電極 電晶體 週邊電路 基板 元件隔離絕緣層 通道形成區 406 :雜質區 201236160 408 :高濃度雜質區 410:金屬化合物區 4 1 1 :閘極絕緣層 4 1 2 :閘極電極 4 1 4 :側壁絕緣層 418a:源極電極或汲極電極 418b:源極電極或汲極電極 4 2 0 :層間絕緣層 4 2 2 :層間絕緣層 424a :連接電極層 424b :連接電極層 424c :連接電極層 4 2 5 :絕緣層 426 :連接電極 428 :電極 43 0 :連接電極 4 5 0 :電晶體 45 2 :記憶單元 8 0 1 :電晶體 803 :電晶體 8 0 4 :電晶體 8 0 5 :電晶體 8 〇 6 :電晶體 807 : X解碼器 -43 201236160 8 08 : Y解碼器 8 1 1 :電晶體 8 1 2 :儲存電容器 8 1 3 : X解碼器 814 : Υ解碼器 901 ： RF電路 902 :模擬基帶電路 903 :數位基帶電路 9 0 4 :電池 9 0 5 :電源電路 906:應用處理器Preferably, the gate insulating layer 146 is formed in consideration of the size of the transistor to be fabricated or the step coverage of the gate insulating layer 146. In addition, the gate leakage current can be reduced by using the following hi gh-k material as the material of the gate insulating layer 146: oxidation giving; yttrium oxide; bismuth acid ring (HfSixOy (x>y> 〇)): added Niobium bismuth citrate (HfSixOyNz (x>0, y>0, z>0)); aluminum acid (HfAlxOy (x> y, y> 〇)). Further, the gate i insulating layer 146 may have a single layer structure or a stacked structure. Then, a gate electrode 148a is formed on the gate insulating layer 146 by trenching the gate electrode. The gate electrode 148a may be formed of a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, niobium or tantalum or an alloy material containing the above-mentioned metal material as a main component. The gate electrode 148a may have a single layer structure or a stacked structure. As a layer contacting the gate electrode 148a of the gate insulating layer 146, a metal oxide containing nitrogen is used. Specifically, an In-Ga-Zn-ruthenium film containing nitrogen, an In-Sn-ruthenium film containing nitrogen, an In-Ga-0 film containing nitrogen, a Ιη-Ζπ-0 film containing nitrogen, and containing nitrogen are used. Sn-0 film, In-ruthenium film containing nitrogen, metal nitride film (InN, SnN, etc.). These films have a work function of 5 electron volts, preferably 5. Work function above 5 eV. When these films are used for the gate electrode, the threshold voltage of the transistor can be shifted in the positive direction, so that a so-called normally-off switching element can be realized. When the step of forming the gate electrode 1 48a in the trench for the gate electrode is completed, the transistor 162 of the trench structure is formed. -16- 201236160 Next, an insulating layer 149 covering the gate electrodes 148a, 148b is formed. The insulating layer M9 is preferably an insulating film having a good step coverage. The insulating layer 1 49 can be formed using a material such as a hafnium oxide film, a gallium oxide film, an aluminum oxide film, a tantalum nitride film, a hafnium oxynitride film, an aluminum oxynitride film, and a hafnium oxynitride film. In the present embodiment, an aluminum oxide film is used as the material of the insulating layer I49. In Figs. 1A and 1B, a gate insulating layer 146 is formed in contact with a side surface of the oxide semiconductor layer, and an insulating layer 149 is formed. Therefore, in the present embodiment, the ruthenium oxide film is covered by using a ruthenium oxide film of SiO 2 + a (note, α > 0) to cover the side surface of the oxide semiconductor layer 14 4 and covering the ruthenium oxide film with an aluminum oxide film. Oxygen in the film diffuses and passes through the insulating layer 149 ° After the insulating layer 149 is formed, the insulating layer 150 for filling the trench for element isolation is formed by a CVD method or the like. The element isolation regions 161, 165 are formed by filling the insulating layer 150 in the trench for element isolation. In addition, by laminating the gate insulating layer 146 and the insulating layer 149 in the trench for element isolation before forming the insulating layer 150, the region filled by the insulating layer 150 can be made smaller, and the insulating layer can be smoothly formed. 0塡 is filled into the trench for element isolation. Then, planarization processing is performed using CMP or the like to obtain the structures shown in Fig. 1 and Fig. 1B. In addition, as shown in FIG. 1B, an insulating layer 150 is also interposed between the gate electrode 1 4 8 a of the transistor 162 and the gate electrode 148b of the adjacent transistor 163 to prevent the gate from being blocked. A short circuit occurs between the pole electrodes. In addition, as shown in FIG. 1A, an electrode serving as a source electrode or a drain electrode of the transistor 1 62 and a source electrode serving as a transistor adjacent to the length of the channel or -17-201236160 bungee The electrodes of the electrodes are also filled with an insulating layer 150 to prevent short-circuiting of the source or drain electrodes. Since the channel of the transistor is formed along the inner wall of the trench, even if the channel formation region is not flat, the carrier can be smoothly along the I η - Ο -1 η - 结晶 of the crystalline oxide semiconductor layer (CAAC) flow past. In this embodiment, the contact depth is 〇. The oxide semiconductor layer 144 is formed in a manner of 4 μm of the inner wall of the trench, so that the channel length is about 0. 8 μπι or more. By making the channel length 0. Above 8 μηη, a normally-off transistor can be realized, and a short channel effect can be prevented. In addition, by adopting the trench structure, the planar area of the transistor can be reduced, so that high integration can be achieved. Embodiment 2 FIGS. 3A and 3B show an example of a semiconductor device using the transistor 162 shown in FIGS. 1A to 1C, which can hold contents and write times even in the absence of power supply. There is also no limit. The off current of the transistor 1 62 is small, so that the storage contents can be maintained for a long period of time by using such a transistor. In other words, the frequency of the update operation can be made extremely low, so that the power consumption can be sufficiently reduced. FIG. 3A shows an example of a cross section of a semiconductor device. The semiconductor device shown in Fig. 3A has a transistor 160 using a first semiconductor material at its lower portion and a transistor 162 using a second semiconductor material at its upper portion. Note that the transistor 1 62 is the same transistor as the transistor 1 62 described in the first embodiment, so in FIGS. 3A and 3B, -18-201236160 uses the same components for the same portions as those of FIG. 1A. a first semiconductor material and a second semiconductor material. For example, an oxide semiconductor such as germanium or the like can be used as a material of the first semiconductor, and a material of the oxygen semiconductor can be used. The use of oxide semiconductors has enabled the company to work at speed. On the other hand, the use of oxygen can maintain the charge for a long period of time due to its characteristics. Further, although the above-described transistors are described in the η state, it is of course possible to use ρ. Since the technical essence of the disclosed invention is to use the transistor 1 62 to maintain information, no specific structure is required. The material of the semiconductor device is semi-limited to the structure shown herein. The transistor 160 shown in FIG. 3A has a metal compound region 124 of the impurity region 120 disposed in a manner that the channel in the substrate 1〇〇 of the substrate (ie, germanium, etc.) holds the channel formation region 116; Layer 1 08; and set in the gate insulation) pole 1 1 0. 126 of the metal compound region 124 of the transistor 160. Here, the electrode 126 functions as a transistor 160 electrode. Further, an insulating layer is disposed on the substrate 1A to surround the electro-crystal, and to cover the transistor insulating layer 130. In addition, it is explained in order to realize a highly integrated number. The bulk material is preferably a different semiconductor material (the compound channel is used as an electromorphic channel type transistor of an electromorphic semiconductor of an external material). This is an oxide semiconductor to be a conductor of a semiconductor device. The structure of the device is placed in the semiconductor material forming region 1 16; the pin 120; the gate electrode on the 罾1 0 8 contacting the impurity channel forming region 1 16 is connected to the source electrode or the drain of the electrode. The body 160 is provided in a manner of 1 60. Preferably, the transistor 60 does not have a sidewall insulating layer as shown in FIG. 19*201236160 3 A. However, in the case of paying attention to the characteristics of the transistor 160 It is also possible to provide a sidewall insulating layer on the side of the gate electrode 1 1 , and to provide an impurity 12 0 ° including a region having a different impurity concentration, as shown in FIG. 3A, the transistor 162 is a trench structure having an oxide semiconductor layer 144. Here, it is preferable that the oxide semiconductor layer 144 is highly purified by sufficiently removing impurities such as hydrogen or supplying sufficient oxygen. Specifically, for example, oxide semi-conducting The hydrogen concentration of the layer 144 is set to 5 x 019 atoms/cm 3 or less, preferably 5 x 1018 atoms/cm 3 or less, and more preferably 5 x 1 017 atoms/cm 3 or less. Further, in the above oxide semiconductor layer 144 The hydrogen concentration is measured by Secondary Ion Mass Spectroscopy (SIMS). Thus, the hydrogen concentration is sufficiently lowered to be highly purified, and the oxygen deficiency is reduced by supplying sufficient oxygen. In the oxide semiconductor layer 144 of the defect level in the energy gap, the carrier concentration is less than 1x1012/cm3, preferably less than lxiou/cm3, and more preferably less than 1. 45xl01Q/cm3. Further, for example, the off current at room temperature (25 ° C) (here, the enthalpy per unit channel width (1 μπι)) is ΙΟΟζΑ (ΙζΑ (仄 安 ampere) is 1 χ 10·21 Α) or less, preferably 1 〇ζΑ below. Thus, by using an i-type (essential) or substantially i-type oxide semiconductor, a transistor 162 having excellent off-current characteristics can be obtained. Further, in the transistor 162 shown in Fig. 3A, in order to suppress leakage between elements due to miniaturization, the element isolation region 161 is provided. -20- 201236160 Further, although the island-shaped oxide semiconductor layer 144 which is processed to be smaller than the region surrounded by the element isolation region 161 is used, as described in Embodiment 1, it is also possible to oxidize before forming the trench for element isolation. The material semiconductor layer 144 is not processed into an island-like structure. In the case where the oxide semiconductor layer 14 4 is not processed into an island shape, contamination of the etching oxide semiconductor layer 144 at the time of processing can be prevented. Of course, when the oxide semiconductor layer is not processed into an island shape, the number of processes can be reduced. In addition, when the island-shaped oxide semiconductor layer 144 which is processed to be smaller than the region surrounded by the element isolation region 161 is used, it is not necessary to separate the oxide semiconductor layer by forming the trench for element isolation, so that the device can be used for isolation. The horizontal position of the bottom surface of the trench is shallower than the trench for the gate electrode. Alternatively, the total area for forming the trench for element isolation can be reduced. An insulating layer 153 is provided on the transistor 1 62, and an electrode 153 electrically connected to the gate electrode 148a is provided on the insulating layer 151. Further, an insulating layer 152 is provided on the electrode 153. Further, an electrode 154 is provided in an opening provided in the gate insulating layer 146, the insulating layer 150, the insulating layer M1, the insulating layer 152, and the like, and a wiring 156 connected to the electrode 154 is formed on the insulating layer 152. Further, in Fig. 3A, although the metal compound region 124, the electrode 142b, and the wiring 156 are connected using the electrode 126 and the electrode 154, the disclosed invention is not limited thereto. For example, electrode 1 42b may also be in direct contact with metal compound region 124. Alternatively, the wiring 156 may be directly in contact with the electrode 142b. Next, FIG. 3B shows an example of the circuit configuration corresponding to FIG. 3A. Note that in the circuit diagram, in order to indicate a transistor using an oxide semiconductor, -21 - 201236160 is sometimes attached with the symbol "os". In Fig. 3B, the first wiring (1st Line) is electrically connected to the source electrode of the transistor 160, and the second wiring (2nd Line) is electrically connected to the drain electrode of the transistor 160. Further, the third wiring (3rd Line) is electrically connected to one of the source electrode and the drain electrode of the transistor 162, and the fourth wiring (4th Line) is electrically connected to the gate electrode of the transistor 162. Further, the gate electrode of the transistor 160 and the other of the source electrode and the drain electrode of the transistor 162 are electrically connected to one electrode of the capacitor 164, and the fifth wiring (5th line) and the other electrode of the capacitor 164 are provided. The electrical connection 》 capacitor 164 can be formed by forming a pair of electrodes and a dielectric insulating layer sandwiched between the pair of electrodes by the same process as the transistor 160 or the transistor 162. Further, the capacitor 164 is not limited to being formed by the same process as the transistor 160 or the transistor 162, and the layer of the capacitor 164 may be separately disposed above the transistor 162. For example, a trench capacitor or a stacked capacitor may be separately formed above the transistor 162 or below the transistor 160 to perform three-dimensional lamination to achieve high integration, in the semiconductor device shown in FIG. 3B. By exhibiting the feature of maintaining the potential of the gate electrode of the transistor 160, information can be written, held, and read as follows. Explain the writing and maintenance of information. First, the electric potential of the fourth wiring is set to a potential at which the transistor 126 is turned on, and the electric crystal 1 62 is turned on. Thereby, the potential of the third wiring is applied to the gate electrode of the transistor 160 and the capacitor 1 64. That is to say, for the transistor -22- 201236160 plus igh HI will, the charge is in the flat. Electric) W human L0 write (for the charge of the C-type load, the pole charge of the poles of the two poles is applied to the transistor 16) 0 gate electrode. Then, by setting the potential of the fourth wiring to a potential at which the transistor 162 is turned off, the transistor 1 62 is turned off, and the charge applied to the gate electrode of the transistor 160 is held (hold). . Alternatively, a back gate electrode may be provided. Preferably, the transistor 162 is normally turned off by applying a voltage to the back gate electrode. This embodiment can be combined as appropriate in the first embodiment. (Embodiment 3) In the present embodiment, a structure different from the structure shown in Embodiment 2 will be described with reference to Fig. 4 in a semiconductor device using the electromorph 162 shown in Figs. 1A and 1B. The semiconductor device can hold the stored contents even in the absence of power supply, and there is no limitation on the number of writes. The semiconductor device shown in Fig. 4 has a transistor 350' using a first semiconductor material at its lower portion and a transistor 162 using a second semiconductor material at its upper portion. Note that although a plurality of transistors ' are provided on the upper and lower semiconductor materials, the description will be made by using the transistors 350 and the transistors 62. Further, Fig. 4, which is cut along the line Β 1 - Β 2, corresponds to a cross-sectional view perpendicular to the length of the channel of the transistor. Here, the first semiconductor material and the second semiconductor material are preferably different materials. For example, a semiconductor material other than an oxide semiconductor (-23-201236160, etc.) can be used as the first semiconductor material, and an oxide semiconductor can be used as the second semiconductor material. A transistor using a material other than an oxide semiconductor is easy to operate at a high speed. On the other hand, a transistor using an oxide semiconductor can maintain a charge for a long period of time due to its characteristics. Further, the 'transistor 162 using the second semiconductor material in the upper portion is the same as the transistor 162 described in the first embodiment and the second embodiment. Therefore, in FIG. 4, the same components are used for the same portions as those in FIG. 1A. The detailed description is omitted. Here, the lower portion of the transistor 350 using the first semiconductor material will be described. The transistor 350 has a semiconductor substrate 310, a gate insulating layer 314: a semiconductor layer 3 16 , a conductive layer 3 18 , a protective insulating layer 320, a sidewall insulating layer 322, an impurity region 324, and an insulating layer 326. Further, the semiconductor layer 316 and the conductive layer 318 function as a gate electrode, and the impurity region 324 serves as a source region or a drain region. Further, an STI (Shallow Trench Isolation) region 312 is adjacent to the transistor 3 50. As the STI region 312, first, a protective insulating film is formed on a desired region on the semiconductor substrate 310 and etched to form a trench (also referred to as a trench). After the trench is formed, the STI region 312 is formed by burying the insulating dielectric film in the trench. As the insulating dielectric film, a ruthenium oxide film, a tantalum nitride film, or the like can be used. Next, a detailed description of the transistor 350 will be performed. As a gate insulating layer 3 14 of the transistor 350, after forming an insulating film on the semiconductor substrate 310 on which the STI regions 3 1 2 -24 - 201236160 are formed, the desired position is patterned and etched, thereby A trench having a different depth from the STI region 312 is formed on the semiconductor substrate 310. Then, heat treatment is performed under oxygen to oxidize the semiconductor substrate 3 10 in the trench, and the gate insulating layer 3 14 can be formed. After the gate insulating layer 314 is formed, a ruthenium film is formed using an LPCVD method or the like. Further, the ruthenium film is subjected to n+, p + doping treatment or heat treatment to form a semiconductor layer having high conductivity as a so-called polysilicon. Then, a metal film is formed on the semiconductor layer by a sputtering method or the like. The metal film can be suitably used: tungsten; titanium; cobalt; nickel; an alloy film containing tungsten, titanium, cobalt, nickel; a metal nitride film; a vaporized film. Conductive layer 318 is then formed by patterning and etching the desired regions on the metal film. Further, the semiconductor layer 3 16 can be formed by etching the semiconductor layer by using the conductive layer 318 as a mask. Further, the conductive layer 318 and the semiconductor layer 3 16 are used as gate electrodes of the transistor 350. Next, a protective insulating layer 320 is formed on the conductive layer 318. The protective insulating layer 3 20 can be formed by forming a hafnium oxide film, a hafnium nitride film, or the like using a plasma CVD method or the like, and patterning and etching a desired region. Then, the sidewall insulating layer 3 2 2 can be formed by forming a tantalum nitride film by a plasma CVD method or the like so as to cover the semiconductor substrate 310 and the protective insulating layer 320 and performing etch back. Next, the protective insulating layer 420 and the sidewall insulating layer 322 are used as a mask to perform a doping treatment to form the impurity region 324. Further, as the dopant, boron or phosphorus or the like can be used, and as the impurity region 324, an n + region, a p + region, or the like can be appropriately formed by using the dopant of -25 to 201236160. Further, the impurity region 324 is used as a source region or a drain region of the transistor 350. Next, the insulating layer 3 26 is formed to cover the impurity region 324, the protective insulating layer 320, and the sidewall insulating layer 322. As the insulating layer 326, a hafnium oxide film or the like formed by a plasma CVD method or the like can be used. Next, an opening portion is formed in a desired region of the insulating layer 326, and a connection electrode 325 and a connection electrode 331 which are electrically connected to the impurity region 324 are formed. Further, after the connection electrode 325 and the connection electrode 331 are formed, a CMP process or the like for planarizing the surfaces of the insulating layer 326, the connection electrode 325, and the connection electrode 331 can be performed. Next, a conductive film is formed on the insulating layer 326, the connection electrode 325, and the connection electrode 331 by sputtering or the like, and a desired region is patterned and etched to form an electrode 328 and an electrode 332. The material of the electrode 328 and the electrode 332 can be suitably made of tungsten, copper, titanium, etc. Next, an insulating layer 3 2 9 is formed on the insulating layer 326, the electrode 328, and the electrode 332. » The insulating layer 3 29 can be used with the insulating layer 3 2 6 The same materials and methods are formed. The semiconductor substrate 310 provided with the transistor 350 using the first semiconductor material can be formed by the above process. Here, the connection relationship between the lower portion of the transistor 050 using the first semiconductor material and the upper portion of the transistor 162 using the second semiconductor material will be described. The transistor 350 is electrically connected to the transistor 162 by the impurity region 324, the connection electrode 325, the electrode 328, and the connection electrode 330. On the other hand, the transistor -26-201236160 350 is electrically connected to the wiring 156 by the impurity region 324, the connection electrode 331, the electrode 332' connecting electrode 334, the electrode 336, and the connection electrode 338. Further, the gate electrode of the transistor 350 (i.e., the semiconductor layer 316 and the conductive layer 318) is electrically connected to the source electrode of the transistor 162. Note that in Fig. 4, the connection of the gate electrode of the transistor 350 and the source electrode of the transistor 162 is not shown but is connected in the three-dimensional direction. As described above, the plurality of memory cells formed at the upper portion are formed of a transistor using an oxide semiconductor. Since the off-state current of the transistor using the oxide semiconductor is small, the storage contents can be maintained for a long period of time by using such a transistor. In other words, the frequency of the update operation can be made extremely low, so that the power consumption can be sufficiently reduced. On the other hand, a semiconductor material other than an oxide semiconductor is used in the peripheral circuit. As the semiconductor material other than the oxide semiconductor, for example, ruthenium, osmium, iridium, ruthenium carbide or gallium arsenide can be used, and a single crystal semiconductor is preferably used. A transistor using such a semiconductor material can perform a sufficiently high speed operation. Therefore, by using a transistor using a material other than the oxide semiconductor, various circuits (logic circuits, drive circuits, and the like) that are required to operate at high speed can be smoothly realized. As described above, a peripheral circuit including a transistor using a material other than an oxide semiconductor (in other words, a transistor capable of performing a sufficiently high-speed operation) and a transistor using an oxide semiconductor are provided (for a broader explanation, The storage circuit of the transistor having a very small off current is integrated, and a semiconductor device having novel features can be realized. Further, integration of the semiconductor device can be achieved by using a laminated structure of the peripheral circuit and the storage circuit. -27-201236160 This embodiment can be implemented in combination with the configuration described in the other embodiments. Fourth Embodiment In the present embodiment, a semiconductor device using the transistor 162 shown in FIG. 1A and FIG. 1B will be described with reference to FIGS. 5A to 6 in a configuration different from the configuration shown in the second embodiment and the third embodiment. . The semiconductor device is capable of holding stored contents even in the absence of power supply' and there is no limit to the number of writes. Fig. 5A shows an example of a circuit configuration of a semiconductor device, and Fig. 5B is a schematic view showing an example of a semiconductor device. First, the semiconductor device shown in Fig. 5A will be described, and then the semiconductor device shown in Fig. 5B will be described. In the semiconductor device shown in FIG. 5A, the bit line BL is electrically connected to the source electrode or the drain electrode of the transistor 162, the word line WL is electrically connected to the gate electrode of the transistor 162, and the source of the transistor 162 is The electrode or the drain electrode is electrically connected to the first terminal of the capacitor 254. The transistor 1 62 using an oxide semiconductor has a characteristic that the off current is extremely small. Therefore, by causing the transistor 162 to be in an off state, the potential of the first terminal of the capacitor 2 54 (or the charge accumulated in the capacitor 254) can be stored for a very long time." Further, the transistor 162 using an oxide semiconductor has It is not easy to present the advantages of the short channel effect. Next, a case where information is written and held to the semiconductor device (memory unit 25A) shown in FIG. 5 will be described. -28-201236160 First, the transistor 1 62 is turned on by setting the potential of the word line WL to a potential at which the transistor 162 is turned on. Thereby, the potential of the bit line BL is applied to the first terminal (write) of the capacitor 254. Then, by setting the potential of the word line WL to a potential at which the transistor 1 62 is turned off, the transistor 1 62 is turned off, whereby the potential of the first terminal of the capacitor 254 is stored (held). Since the off current of the transistor 162 is extremely small, the potential of the first terminal of the capacitor 2 54 (or the charge accumulated in the capacitor) can be stored for a long period of time. Next, the reading of the information will be described. When the transistor 1 62 is turned on, the bit line BL in the floating state is turned on with the capacitor 254, so that the charge is again distributed between the bit line BL and the capacitor 254. As a result, the potential of the bit line BL changes. The amount of change in the potential of the bit line BL takes a different 根据 depending on the potential of the first terminal of the capacitor 254 (or the charge accumulated in the capacitor 2 54). For example, where V is the potential of the first terminal of the capacitor 254, C is the capacitance of the capacitor 254, and CB is the capacitance component of the bit line BL (hereinafter also referred to as bit line capacitance), and VB0 is Under the condition that the potential of the bit line BL before the charge is redistributed, the potential of the bit line BL after the charge is redistributed becomes (CB*VB0 + C*V) / (CB + C). Therefore, as the state of the memory cell 250, when the potential of the first terminal of the capacitor 254 is two states of VI and V0 (VI > V0), the potential of the bit line BL when the potential VI is held (= (CB) *VB0 + C*V1)/(CB + C) ) is higher than the potential of the bit line BL when the potential V0 is held (=( -29- 201236160 CB * VBO + C* V0) / (CB + C)). Further, information can be read by comparing the potential of the bit line BL with the specified potential. Thus, the semiconductor device shown in Fig. 5A can maintain the charge accumulated in the capacitor 254 for a long period of time by utilizing the characteristic that the off current of the transistor 1 62 is extremely small. In other words, since the update work is not required, or the frequency of the update work can be made extremely low, the power consumption can be sufficiently reduced. In addition, the stored contents can be maintained for a long period of time even in the absence of power supply. Next, the semiconductor device shown in FIG. 5B will be described. The semiconductor device shown in FIG. 5B is provided with a memory cell array 25 1 having a plurality of cells 200 shown in FIG. 5A as a memory element, and a peripheral circuit 25 3 for operating the memory cell array 251 at a lower portion thereof. By employing the structure shown in FIG. 5B, the peripheral circuit 2 53 can be disposed directly under the memory cell array 251, so that the miniaturization of the semiconductor device can be realized. Next, a specific structure of the semiconductor device shown in Fig. 5B will be described with reference to Fig. 6 . The semiconductor device shown in Fig. 6 has a memory unit 45 2 at its upper portion and a peripheral circuit 400 at its lower portion. The lower peripheral circuit 400 has a transistor 450 using a first semiconductor material, and the memory cell 452 formed at the upper portion has a transistor 162 using a second semiconductor material. Further, Fig. 6 which is cut along the line C1-C2 corresponds to a cross-sectional view perpendicular to the channel length direction of the transistor. -30- 201236160 Here, the first semiconductor material and the second semiconductor material are preferably materials. For example, a semiconductor material other than an oxide semiconductor or the like can be used as the first semiconductor material, and an oxide semiconductor can be used as a semiconductor material. Electro-crystals using materials other than oxide semiconductors are easy to operate at high speed. On the other hand, electricity using an oxide semiconductor can maintain a charge for a long period of time due to its characteristics. Further, in the upper transistor 162 using the second semiconductor material, the transistor 162 described in the first embodiment to the third embodiment is the same as the first embodiment. Therefore, in FIG. 6, the same portions as those in FIG. 1A are denoted by the same reference numerals, and the detailed description is omitted. Description. Here, the lower portion of the transistor 450 using the first semiconductor material will be described. The transistor 450 in FIG. 6 has a channel formation region 404 formed in a substrate 402 including a semiconductor material such as germanium or the like; The impurity region 406 and the high concentration impurity 〇8 in the manner of the region 404 (collectively referred to as the impurity region); the metal compound region 410 contacting the high concentration impurity 408; forming the electrode insulating layer 411 on the channel forming region 404; The electrode electrode 412 is provided in contact with the gate insulating layer 411; the source electrode or the drain electrode and the source electrode or the drain electrode 418b electrically connected to the impurity region. Here, a side wall insulating layer is provided on the side surface of the gate electrode 4 1 2 . Further, a spacer insulating layer 403 is provided on the substrate 402 so as to surround the transistor 450, and an interlayer insulating layer 420 and an interlayer insulating layer 422 are provided to cover the transistor 450. The source electrode or the drain electrode 418a and the source electrode or the drain electrode 418b are formed by different materials between the layers (the body of the body and the solid crystal element body material (the gate 418a 414 of the gate holding the mass region) has a element The opening in which the electrode insulation 31 - 201236160 layer 420 and the interlayer insulating layer 422 are disposed is electrically connected to the gold 41. In other words, the source or drain electrode 418a and the drain electrode 418b are electrically connected to the mass region 408 by the metal compound region 410. In addition, the sidewall insulating layer 412 is not formed in order to realize the crystallization, etc. Further, the layer 422 is provided with a connection electrode layer 424a and a connection electrode layer connection electrode layer 424c. The layer 424a, the connection and the connection electrode layer 424c are electrically connected to the gate electrode 418a of the transistor 450 and the source electrode or the drain electrode 418b. The insulating layer 425 covers the interlayer insulating layer 422, the connection electrode layer electrode layer 424b, and the connection electrode layer 424c. To achieve flatness, the connection electrode layer 424c is electrically connected by the connection electrode 426. Further, the electrode 42 8 is formed of the same layer as the source electrode of the transistor 162. In addition, the wiring 1 56 The connection electrode is used to the electrode 428. By using the connection electrode layer 424c, the connection electrode 428, the connection electrode 430, and the wiring 156, electrical connection between the path 400 and the memory unit 452, etc. can be performed. Further, the semiconductor shown in FIG. The device exemplifies the connection of the memory cell 452 and the peripheral structure by the layer 424c and the electrode 42. However, the configuration is not limited thereto. Two or more wiring layers and electrodes may be provided between the memory cell circuits 400. As described above, The memory cell formed in the upper portion is formed by the transistor of the use body. Since the electric current using the oxide semiconductor is small, the use of such a transistor can be used for a long time as a source electrode of the compound region or a high concentration of the impurity 45 0 . The interlayer electrode 424b and the heavy electrode layer 424b source electrode are connected to each other by using 424a, and the electrode 4426 and the drain electrode 430 are electrically connected to the electrode 426 to realize the junction 4 5 of the peripheral electrical connection electrode path 400. The cut-off of the peripheral oxide semiconductor crystals is kept within -32 to 201236160. In other words, the frequency of the update operation can be made extremely low, and the power consumption is reduced. In other words, a semiconductor material other than the peripheral circuit is used. As the oxide semiconductor, for example, yttrium, lanthanum, cerium, lanthanum carbide or arsenide semiconductor can be preferably used. The use of such a semiconductor material is sufficiently high-speed operation. Thus, by using a transistor using a material other than oxygen, it is possible to smoothly realize a high-required circuit (logic circuit, drive circuit, etc.) as described above, by using a transistor having an oxide semi-conductor (in other words, A peripheral circuit capable of performing a sufficiently high-speed operation and a memory having an electro-optical explanation using an oxide semiconductor, which has a very small off-current, can realize a laminate of a peripheral circuit and a storage circuit of a semiconductor device having a novel feature Structure, can be integrated. This embodiment can be implemented in combination with the description of the other embodiments. (Embodiment 5) In the present embodiment, an example in which the semiconductor device described with reference to Figs. 10A to 13 is applied to a mobile device such as a mobile phone or an e-book reader will be described. In mobile phones, smart phones, and e-book readings, "SrAM is used to temporarily store image data, or gallium semiconductor materials that can be sufficiently oxide semiconductors, etc., and single crystals can be used to evolve semiconductors at speed. A transistor made of a material (for a more extensive memory circuit is set. In addition, by implementing the structure of the semiconductor package, the above-mentioned mobile device, such as a smart phone, etc., is implemented. Using -33-201236160 SRAM or DRAM Because the flash memory response speed is slow and it is not suitable for processing images. On the other hand, when SRAM or DRAM is used for temporary storage of image data, it has the following features: As shown in Fig. 10A, in general SRAM One memory cell is composed of a transistor 801 to six transistors of a transistor 806' and these transistors are driven by an X decoder 807 and a Y decoder 808. The transistor 803 and the transistor 805 and the transistor 804 and the transistor 806 Forming an inverter that enables high-speed driving. However, since one transistor is composed of six transistors, there is memory. The disadvantage of large cell area. When the minimum size of the design rule is set to F, the memory cell area of the SRAM is generally 100 to 150 F2. Therefore, the SRAM is the highest unit price per bit in various memories. On the one hand, in the DRAM, as shown in Fig. 10B, the cells are constituted by the transistor 811 and the storage capacitor 812, and these elements are driven by the X decoder 813 and the Y decoder 814. Since one unit is composed of one transistor and one Since the capacitance is small, the area occupied by the DRAM is generally 1 OF2 or less. However, since the DRAM needs to be updated all the time, power is consumed even without rewriting. In contrast, the above embodiment The memory cell area of the semiconductor device described is about 1 OF2, and does not require frequent update operations. Therefore, the memory cell area can be reduced and the power consumption can be reduced. FIG. 11 is a block diagram of the mobile device. The illustrated mobile device has: RF circuit 901; analog baseband circuit 902; digital baseband circuit 903: battery 904; power supply circuit 905; application processor 9 06; flash-34-201236160 remembers the body 910; the display controller 911; the storage circuit 912; 913; the touch sensor 919; the audio circuit 917; and the keyboard 9: the display 913 has: the display portion 914; the source driver 915 The pole driver 916. The application processor 906 has a CPU (Processing Unit: 907; a DSP (Digital Processor) 908; and an interface 909). The storage circuit 912 is generally composed of an SRAM or a DRAM. The semiconductor device described in the embodiment is used for this portion, and information can be written and read, and the stored content can be stored for a long period of time, thereby sufficiently reducing the power consumption. Further, Fig. 12 shows an example in which the semiconductor used in the above embodiment is applied to the storage circuit 950 of the display. The road 950 shown in Fig. 12 has a memory 952, a memory 953, a switch 954 95 5 , and a memory controller 951. In addition, the storage circuit 950: a display controller 956 for reading and controlling image data (input material) input from the signal line, data (image data) stored in the memory 958 and the memory 953; The display 956 signals the display 957 for display. First, a shadow (input image material A) is formed by an application processor (not shown). The input image data A is stored in the remembered body 952 by a switch. Then, the image stored in the memory 952 (storing image data A) is displayed by the switch 95 5 and the display 956 to the display 957. When there is no change in the input image data A, the image data display 18 and the like are stored. And the gate Central Signal (IF909 will be able to store power by the high-speed device; the switch is connected to the image controller 954 in the image controller A. -35- 201236160 to about 30 to 6 OHz The period is read from the memory 952 by the display controller 956 via the switch 955. In addition, for example, when the user performs the operation of rewriting the screen (that is, when the input image data A changes), the application processor forms a new one. Image data (input image data B). The input image data B is stored in the memory 953 by the switch 954. During this period, the stored image data A is also continuously read from the memory 952 by the switch 95 5 . When a new image (storing image data B) is stored in the memory 953, the stored image data B is read from the next frame of the display 957, and the stored image data B is switched by the switch 95 and The display controller 956 sends a display to the display 95 7. The reading continues until the next new image data is stored in the memory 952. As described above, by the account 952 and The memory 95 3 alternately performs writing of image data and reading of image data to display the display 95 7. In addition, it is also possible to record the display of the display 95 7 and the body 953, not limited to two different memories. By using the memory device described in the above embodiment for the memory 95 2 and the memory 953, information can be written and read at a high speed, and the content can be stored for a long period of time. Figure 13 is a block diagram of the e-book reader. The e-book reader shown in Figure 13 has a battery 1001, a power supply circuit 1 002, a microprocessor 1 003, and a flashing body 1 004; Audio circuit 1 005; keyboard 1 006; storage circuit 1 007; touch panel 1 008; display 1 009; and display controller 1 0 1 0. -36- 201236160 Here, the semiconductor device described in the above embodiments can be used The storage circuit 1007 of the storage circuit 1007 of FIG. 13 has a function of temporarily holding the contents of the book. As an example of the function, for example, there is a case where the user uses the emphasis function. The user is reading the electronic book. Sometimes, you need to mark a part. This mark function is called the emphasis function, that is, by changing the display color; underlining; changing the text to bold; changing the font of the text, etc., to make the part It is not the same as the surrounding. The emphasis function is the function of storing and retaining the information of the part specified by the user. When the information is held for a long time, the information can also be copied to the flash memory 1 0 04. Even In this case, by using the semiconductor device described in the above embodiment, information can be written and read at a high speed, and the stored content can be held for a long period of time, and the power consumption can be sufficiently reduced. As described above, the mobile device shown in the present embodiment is mounted with the semiconductor device according to the above embodiment. Therefore, it is possible to realize a mobile device that reads information at a high speed, stores content for a long period of time, and sufficiently reduces power consumption. The structure, method, and the like described in the present embodiment can be implemented in appropriate combination with the structures, methods, and the like described in the other embodiments. [Embodiment 1] In this embodiment, calculation was performed in order to confirm whether or not the transistor of the trench structure shown in Embodiment 1 exhibits a short channel effect. In addition, the device simulation software Sentaurus Device manufactured by Syn〇psys was used in the calculation. -37- 201236160 Figure 7A shows the structure and various dimensions used for the calculation. The thickness of the gate insulating layer is 5 ηηι, the thickness of the oxide semiconductor layer is 5 nm, and the depth of the trench for the gate electrode is 〇·4μηι. 7A shows a transistor of a trench structure in which the length of the bottom of the trench (the length in the channel length direction) is 90 nm, and the interval between the source electrode and the drain electrode (the length in the channel length direction) is ll 〇 nm. . The material of the oxide semiconductor layer is an In-Ga-Zn-0-based oxide semiconductor (the energy gap is 3. 15eV, electronic affinity is 4. 6eV, electron mobility is l〇cm2/Vs), and the work function of the electrode (source electrode and drain electrode) contacting the oxide semiconductor layer is 4. 6eV, and the work function of the gate electrode is 5. 5eV. Fig. 7B shows the result of calculation of the Vg-Id characteristic (Vds = 1 V, temperature: 27 ° C) of the transistor of the trench structure. In addition, Fig. 8A shows the length of the bottom of the trench (the length of the channel) The length is 60 nm, and the interval between the source electrode and the drain electrode (the length in the channel length direction) is a transistor of a trench structure of 80 nm. Fig. 8B shows the calculation results of the same conditions as those of Fig. 7B except for the length of the bottom of the trench and the interval between the source electrode and the drain electrode. In addition, FIG. 9A shows that the length of the bottom of the trench (the length in the channel length direction) is 30 nm, and the interval between the source electrode and the drain electrode (the length in the channel length direction) is 50 nm. Crystal. Fig. 9B shows the calculation results of the same conditions as those of Fig. 7B except for the length of the bottom of the trench and the interval between the source electrode and the drain electrode. From the calculation results, it is understood that the characteristics of all the transistors of the structures of Fig. 7A, Fig. 8A, and Fig. 9A are substantially equal. The threshold 値(Vth ) -38- 201236160 of each transistor is 0. The 8V ’ S値 is 60mV/dec, which is an ideal number. From these calculation results, it is known that even if the interval between the source electrode and the drain electrode (the length in the channel length direction) is shortened to 50 nm, good transistor characteristics can be obtained without exhibiting a negative drift of the threshold 或 or S. Short channel effects such as an increase in 値. For comparison, the same calculation was performed using a planar transistor structure without using a transistor of a trench structure. When the interval between the source electrode and the drain electrode (the length in the channel length direction) is shortened, the channel length is also shortened, and a short channel effect such as a negative drift of the threshold 或 or an increase in S 呈现 is exhibited, and further, It is confirmed that the leakage current (off current) increases when a negative bias is applied to the gate. The calculation results of Figs. 7B, 8B, and 9B are ideal as compared with the calculation results for comparison. By adopting the transistor structure shown in Embodiment 1, even if the interval between the source electrode and the drain electrode (the length in the channel length direction) is shortened, since the change in the effective channel length is small, the short channel effect is not exhibited. Therefore, the off current can be suppressed. As a result, it is possible to manufacture a cell unit with good retention characteristics. BRIEF DESCRIPTION OF THE DRAWINGS In the drawings: FIGS. 1A to 1C are cross-sectional views and plan views showing one embodiment of the present invention; and FIGS. 2A to 2C are cross-sectional schematic views showing a mode of the present invention - 39- Figure 3A and Figure 3B are cross-sectional views and circuit diagrams showing one embodiment of the present invention; Figure 4 is a cross-sectional view showing one embodiment of the present invention; and Figures 5A and 5B are circuit diagrams showing one embodiment of the present invention; Figure 6 is a cross-sectional view showing one mode of the present invention; Figures 7A and 7B are structural sectional views and calculation results for calculation; Figures 8A and 8B are structural sectional views and calculation results for calculation; 9A and 9B are structural sectional views and calculation results for calculation; Figs. 10A and 10B are circuit diagrams showing one mode of the present invention; and Fig. 11 is a block diagram showing a portable device of one embodiment of the present invention; Fig. 12 is a block diagram showing a semiconductor device according to an embodiment of the present invention, and Fig. 13 is a block diagram showing an electronic book reader according to an embodiment of the present invention. [Main component symbol description] 100: Substrate 108: Gate insulating layer 1 1 〇: Gate electrode 1 1 6 : Channel forming region 120: Impurity region 124: Metal compound region - 40 - 201236160 1 26 : Electrode 1 3 0 : Insulating layers 142a, 142b: electrodes 143a, 143b: insulating layer 144: oxide semiconductor layer 1 4 6 : gate insulating layer 148a, 148b: gate electrode 1 4 9 : insulating layer 1 50: insulating layer 1 5 1 : Insulating layer 1 5 2 : insulating layer 1 53 : electrode 154 : electrode 1 5 6 : wiring 1 6 0 : transistor 1 6 1 : element isolation region 1 6 2 : transistor 163 : transistor 164 : capacitor 1 6 5 : Component isolation region 25 0 : memory unit 251 : memory cell array 2 5 3 : peripheral circuit 2 54 : capacitor 201236160 3 10: 3 12: 3 14: 3 16: 3 18: 320 : 3 22 : 324 : 325 : 3 26 : 3 2 8 : 3 29 : 3 3 0 : 33 1: 3 3 2 : 3 3 4 : 3 3 6 : 3 3 8 : 3 5 0 : 400 : 402 : 403 : 404 : STI area gate insulation of the semiconductor substrate Layer semiconductor layer conductive layer protective insulating layer sidewall insulating layer impurity region connecting electrode insulating layer electrode insulating layer connecting electrode connecting electrode electrode connecting electricity Electrode electrode connection electrode transistor peripheral circuit substrate element isolation insulating layer channel formation region 406: impurity region 201236160 408: high concentration impurity region 410: metal compound region 4 1 1 : gate insulating layer 4 1 2 : gate electrode 4 1 4 : sidewall insulating layer 418a: source electrode or drain electrode 418b: source electrode or drain electrode 4 2 0 : interlayer insulating layer 4 2 2 : interlayer insulating layer 424a: connecting electrode layer 424b: connecting electrode layer 424c: connecting electrode Layer 4 2 5 : insulating layer 426 : connecting electrode 428 : electrode 43 0 : connecting electrode 4 5 0 : transistor 45 2 : memory unit 8 0 1 : transistor 803 : transistor 8 0 4 : transistor 8 0 5 : Transistor 8 〇 6 : Transistor 807 : X Decoder - 43 201236160 8 08 : Y decoder 8 1 1 : Transistor 8 1 2 : Storage capacitor 8 1 3 : X decoder 814 : Υ Decoder 901 : RF circuit 902: analog baseband circuit 903: digital baseband circuit 9 0 4: battery 9 0 5: power supply circuit 906: application processor

907 ： CPU907 : CPU

908 ： DSP 909 :介面 9 1 0 :快閃記憶體 9 1 1 :顯示器控制器 912 :儲存電路 9 1 3 :顯示器 914 :顯示部 9 1 5 :源極驅動器 9 1 6 :閘極驅動器 91 7 :聲頻電路 91 8 :鍵盤 919 :觸控感應器 -44- 201236160 95 0 :儲存電路 951 :記憶體控制器 952 :記憶體 95 3 :記憶體 954 :開關 9 5 5 :開關 956 :顯示器控制器 957 :顯示器 1 0 0 1 :電池 1 0 0 2 :電源電路 1 003 :微處理器 1 004 :快閃記憶體 1 005 :聲頻電路 1 006 :鍵盤 1 007 :儲存電路 1 008 :觸控面板 1 009 :顯示器 1 〇 1 〇 :顯示器控制器 -45908 : DSP 909 : interface 9 1 0 : flash memory 9 1 1 : display controller 912 : storage circuit 9 1 3 : display 914 : display portion 9 1 5 : source driver 9 1 6 : gate driver 91 7 : Audio circuit 91 8 : Keyboard 919 : Touch sensor -44 - 201236160 95 0 : Memory circuit 951 : Memory controller 952 : Memory 95 3 : Memory 954 : Switch 9 5 5 : Switch 956 : Display controller 957 : Display 1 0 0 1 : Battery 1 0 0 2 : Power circuit 1 003 : Microprocessor 1 004 : Flash memory 1 005 : Audio circuit 1 006 : Keyboard 1 007 : Storage circuit 1 008 : Touch panel 1 009 : Display 1 〇 1 〇: Display Controller - 45

Claims (1)

201236160 七、申請專利範圍： 1. 一種半導體裝置，包括： 第一絕緣層； 在該第一絕緣層中的溝槽； 與該溝槽的內壁面接觸的氧化物半導體層； 與該氧化物半導體層相鄰的閘極絕緣層； 在該溝槽中且與該氧化物半導體層相鄰的閘極電極， 在兩者之間夾有該閘極絕緣層。 2. 根據申請專利範圍第1項之半導體裝置，還包括 與該氧化物半導體層接觸的源極電極或汲極電極。 3 .根據申請專利範圍第1項之半導體裝置，以及 其中，該氧化物半導體層具有U字形狀的剖面形狀， 其中，該氧化物半導體層包含結晶，該結晶具有大致 垂直於該氧化物半導體層的表面的c軸。 4. 根據申請專利範圍第2項之半導體裝置，還包括 在該閘極絕緣層和該源極電極或汲極電極之間的第二絕緣 層。 5. 根據申請專利範圍第1項之半導體裝置， 其中，該內壁面至少包括該溝槽的底面。 6·—種半導體裝置，包括： 第一絕緣層； 在該第一絕緣層中的第一溝槽； 與該第一絕緣層接觸的氧化物半導體層，其中該氧化 物半導體層包括： -46 - 201236160 與該第一溝槽的第一側壁相鄰的第一區； 與該第一溝槽的底面相鄰的第二區；以及 與該第一溝槽的第二側壁相鄰的第三區，其中該 第一溝槽的第一側壁與該第一溝槽的第二側壁彼此相對， 在該第一絕緣層的第一區上的源極電極，該源極電極 電連接到該氧化物半導體層； 在該第一絕緣層的第二區上的汲極電極，該汲極電極 電連接到該氧化物半導體層，其中該第一溝槽位於該第一 絕緣層的第一區與該第一絕緣層的第二區之間； 與該氧化物半導體層相鄰的閘極絕緣層；以及 在該第一溝槽中且與該氧化物半導體層相鄰的閘極電 極，在兩者之間夾有該閘極絕緣層。 7. 根據申請專利範圍第6項之半導體裝置，還包括 在該第一絕緣層中的第二溝槽；以及 塡充該第二溝槽的第二絕緣層。 8. 根據申請專利範圍第6項之半導體裝置， 其中，該閘極絕緣層接觸於該氧化物半導體層的側面 〇 9. 根據申請專利範圍第6項之半導體裝置， 其中，該氧化物半導體層具有U字形狀的剖面形狀， 以及 其中，該氧化物半導體層包含結晶，該結晶具有大致 垂直於該氧化物半導體層的表面的c軸。 -47- 201236160 10. —種半導體裝置，包括： 第一絕緣層； 在該第一絕緣層中的第一溝槽； 在該第一絕緣層中的第二溝槽： 與該第一溝槽的內壁面接觸的氧化物半導體層； 與該氧化物半導體層相鄰的第二絕緣層，其中該第二 絕緣層與該第二溝槽的內壁面相鄰； 在該第一溝槽中且與該氧化物半導體層相鄰的閘極電 極，在兩者之間夾有該第二絕緣層；以及 塡充該第二溝槽的第三絕緣層。 11. 根據申請專利範圍第10項之半導體裝置，還包 括與該氧化物半導體層接觸的源極電極或汲極電極。 12. 根據申請專利範圍第10項之半導體裝置， 其中，該第二絕緣層接觸於該氧化物半導體層的側面 〇 13. 根據申請專利範圍第10項之半導體裝置， 其中，該氧化物半導體層具有U字形狀的剖面形狀， 以及 其中，該氧化物半導體層包含結晶，該結晶具有大致 垂直於該氧化物半導體層的表面的c軸。 14. 根據申請專利範圍第10項之半導體裝置，還包 括在該第二溝槽中的第四絕緣層， 其中，該第四絕緣層設置在該第二絕緣層和該第三絕 緣層之間。 -48 - 201236160 15. 根據申請專利範圍第11項之半導體裝置，還包 括在該第二絕緣層和該源極電極或汲極電極之間的第四絕 緣層 16. 根據申請專利範圍第10項之半導體裝置， 其中，該第一溝槽的內壁面至少包括該第一溝槽的底 面，以及 其中，該第二溝槽的內壁面至少包括該第二溝槽的底 面。 17. 根據申請專利範圍第10項之半導體裝置， 其中，該第二溝槽的底部的水平位置深於該第一溝槽 的底部的水平位置。 18. —種半導體裝置，包括： 半導體基板； 在該半導體基板中的第一溝槽； 在該半導體基板中的雜質區； 與該第一溝槽的內壁面接觸的第一閘極絕緣層； 在該第一溝槽中且在該第一閘極絕緣層上的第一閘極 電極； 在該第一閘極電極和該半導體基板上的第一絕緣層； 在該第一絕緣層上的第二絕緣層： 在該第二絕緣層中的第二溝槽； 與該第二溝槽的內壁面接觸的氧化物半導體層； 與該氧化物半導體層相鄰的第三絕緣層；以及 在該第二溝槽中且與該氧化物半導體層相鄰的第二閘 -49 - 201236160 極電極，在兩者之間夾有該第三絕緣層。 19. 根據申請專利範圍第18項之半導體裝置’還包 括： 在該第二絕緣層中的第三溝槽，其中該第三絕緣層與 該第三溝槽的內壁面相鄰；以及 塡充該第三溝槽的第四絕緣層。 20. 根據申請專利範圍第18項之半導體裝置，還包 括與該氧化物半導體層接觸的源極電極或汲極電極， 其中，該源極電極或汲極電極電連接到該第一閘極電 極。 21·根據申請專利範圍第18項之半導體裝置， 其中，該第一閘極電極包括半導體層和在該半導體層 上的導電層。 2 2.根據申請專利範圍第18項之半導體裝置，還包 括： 在該第一閘極電極上的保護絕緣層；以及 與該第一閘極電極和該保護絕緣層的側面接觸的側壁 絕緣層。 2 3 ·根據申請專利範圍第1 8項之半導體裝置， 其中，該氧化物半導體層具有U字形狀的剖面形狀， 以及 其中，該氧化物半導體層包含結晶，該結晶具有大致 垂直於該氧化物半導體層的表面的c軸》 24.根據申請專利範圍第19項之半導體裝置， -50- 201236160 其中，該第一溝槽的內壁面至少包括該第一溝槽的底 面，以及 其中，該第二溝槽的內壁面至少包括該第二溝槽的底 面。 2 5 .根據申請專利範圍第I 9項之半導體裝置， 其中，該第三溝槽的底部的水平位置深於該第二溝槽 的底部的水平位置。 26. —種半導體裝置，包括： 包含具有半導體材料的電晶體的電路；以及 在該電路上且與該電路接觸的記憶體，該記憶體包括 第一絕緣層； 在該第一絕緣層中的第一溝槽； 與該第一溝槽的內壁面接觸的氧化物半導體層； 與該氧化物半導體層相鄰的第二絕緣層；以及 在該第一溝槽中且與該氧化物半導體層相鄰的閘極電 極，在兩者之間夾有該第二絕緣層， 其中，該半導體材料與該氧化物半導體層的材料不同 〇 27. 根據申請專利範圍第26項之半導體裝置，還包 括 在該第一絕緣層中的第二溝槽，其中該第二絕緣層與 該第二溝槽的內壁面相鄰；以及 塡充該第二溝槽的第三絕緣層。 -51 - 201236160 28. 根據申請專利範圍第26項之半導體裝置，還包 括與該氧化物半導體層接觸的源極電極或汲極電極。 29. 根據申請專利範圍第26項之半導體裝置，其中 該第二絕緣層接觸於該氧化物半導體層的側表面。 3 0.根據申請專利範圍第26項之半導體裝置，以及 其中，該氧化物半導體層具有U字形狀的剖面形狀， 其中，該氧化物半導體層包含結晶，該結晶具有大致 垂直於該氧化物半導體層的表面的c軸。 3 1 ·根據申請專利範圍第26項之半導體裝置， 其中，該內壁面至少包括該第一溝槽的底面。 32.根據申請專利範圍第27項之半導體裝置， 其中，該第一溝槽的內壁面至少包括該第一溝槽的底 面，以及 其中，該第二溝槽的內壁面至少包括該第二溝槽的底 面。 3 3 .根據申請專利範圍第27項之半導體裝置， 其中，該第二溝槽的底部的水平位置深於該第—溝槽 的底部的水平位置》 -52-201236160 VII. Patent application scope: 1. A semiconductor device comprising: a first insulating layer; a trench in the first insulating layer; an oxide semiconductor layer in contact with an inner wall surface of the trench; and the oxide semiconductor a gate insulating layer adjacent to the layer; a gate electrode adjacent to the oxide semiconductor layer in the trench, the gate insulating layer being sandwiched therebetween. 2. The semiconductor device according to claim 1, further comprising a source electrode or a drain electrode in contact with the oxide semiconductor layer. 3. The semiconductor device according to claim 1, wherein the oxide semiconductor layer has a U-shaped cross-sectional shape, wherein the oxide semiconductor layer comprises crystals having a substantially perpendicular to the oxide semiconductor layer The c-axis of the surface. 4. The semiconductor device according to claim 2, further comprising a second insulating layer between the gate insulating layer and the source electrode or the drain electrode. 5. The semiconductor device according to claim 1, wherein the inner wall surface includes at least a bottom surface of the trench. a semiconductor device comprising: a first insulating layer; a first trench in the first insulating layer; an oxide semiconductor layer in contact with the first insulating layer, wherein the oxide semiconductor layer comprises: -46 a first region adjacent to the first sidewall of the first trench; a second region adjacent the bottom surface of the first trench; and a third adjacent to the second sidewall of the first trench a region, wherein the first sidewall of the first trench and the second sidewall of the first trench are opposite each other, a source electrode on the first region of the first insulating layer, the source electrode is electrically connected to the oxide a semiconductor layer; a drain electrode on the second region of the first insulating layer, the drain electrode being electrically connected to the oxide semiconductor layer, wherein the first trench is located in the first region of the first insulating layer Between the second regions of the first insulating layer; a gate insulating layer adjacent to the oxide semiconductor layer; and a gate electrode adjacent to the oxide semiconductor layer in the first trench, in two The gate insulating layer is sandwiched between the two. 7. The semiconductor device of claim 6, further comprising a second trench in the first insulating layer; and a second insulating layer filling the second trench. 8. The semiconductor device according to claim 6, wherein the gate insulating layer is in contact with the side surface of the oxide semiconductor layer. The semiconductor device according to claim 6, wherein the oxide semiconductor layer A cross-sectional shape having a U shape, and wherein the oxide semiconductor layer contains crystals having a c-axis substantially perpendicular to a surface of the oxide semiconductor layer. -47- 201236160 10. A semiconductor device comprising: a first insulating layer; a first trench in the first insulating layer; a second trench in the first insulating layer: and the first trench An oxide semiconductor layer contacting the inner wall surface; a second insulating layer adjacent to the oxide semiconductor layer, wherein the second insulating layer is adjacent to an inner wall surface of the second trench; and in the first trench a gate electrode adjacent to the oxide semiconductor layer, the second insulating layer being sandwiched therebetween; and a third insulating layer filling the second trench. 11. The semiconductor device according to claim 10, further comprising a source electrode or a drain electrode in contact with the oxide semiconductor layer. 12. The semiconductor device according to claim 10, wherein the second insulating layer is in contact with the side surface of the oxide semiconductor layer. The semiconductor device according to claim 10, wherein the oxide semiconductor layer A cross-sectional shape having a U shape, and wherein the oxide semiconductor layer contains crystals having a c-axis substantially perpendicular to a surface of the oxide semiconductor layer. 14. The semiconductor device of claim 10, further comprising a fourth insulating layer in the second trench, wherein the fourth insulating layer is disposed between the second insulating layer and the third insulating layer . The semiconductor device according to claim 11, further comprising a fourth insulating layer 16 between the second insulating layer and the source electrode or the drain electrode. According to claim 10 The semiconductor device, wherein an inner wall surface of the first trench includes at least a bottom surface of the first trench, and wherein an inner wall surface of the second trench includes at least a bottom surface of the second trench. 17. The semiconductor device according to claim 10, wherein a horizontal position of a bottom portion of the second trench is deeper than a horizontal position of a bottom portion of the first trench. 18. A semiconductor device comprising: a semiconductor substrate; a first trench in the semiconductor substrate; an impurity region in the semiconductor substrate; a first gate insulating layer in contact with an inner wall surface of the first trench; a first gate electrode in the first trench and on the first gate insulating layer; a first insulating layer on the first gate electrode and the semiconductor substrate; on the first insulating layer a second insulating layer: a second trench in the second insulating layer; an oxide semiconductor layer in contact with an inner wall surface of the second trench; a third insulating layer adjacent to the oxide semiconductor layer; The second gate-49 - 201236160 electrode in the second trench and adjacent to the oxide semiconductor layer has the third insulating layer interposed therebetween. 19. The semiconductor device of claim 18, further comprising: a third trench in the second insulating layer, wherein the third insulating layer is adjacent to an inner wall surface of the third trench; and a fourth insulating layer of the third trench. 20. The semiconductor device according to claim 18, further comprising a source electrode or a drain electrode in contact with the oxide semiconductor layer, wherein the source electrode or the drain electrode is electrically connected to the first gate electrode . The semiconductor device according to claim 18, wherein the first gate electrode comprises a semiconductor layer and a conductive layer on the semiconductor layer. 2. The semiconductor device according to claim 18, further comprising: a protective insulating layer on the first gate electrode; and a sidewall insulating layer in contact with the first gate electrode and a side surface of the protective insulating layer . The semiconductor device according to claim 18, wherein the oxide semiconductor layer has a U-shaped cross-sectional shape, and wherein the oxide semiconductor layer contains crystals having a substantially perpendicular to the oxide The c-axis of the surface of the semiconductor layer. The semiconductor device according to claim 19, wherein the inner wall surface of the first trench includes at least a bottom surface of the first trench, and wherein the The inner wall surface of the two grooves includes at least the bottom surface of the second groove. The semiconductor device according to claim 19, wherein the horizontal position of the bottom of the third trench is deeper than the horizontal position of the bottom of the second trench. 26. A semiconductor device comprising: a circuit comprising a transistor having a semiconductor material; and a memory on the circuit in contact with the circuit, the memory comprising a first insulating layer; in the first insulating layer a first trench; an oxide semiconductor layer in contact with an inner wall surface of the first trench; a second insulating layer adjacent to the oxide semiconductor layer; and in the first trench and the oxide semiconductor layer An adjacent gate electrode is sandwiched between the two, wherein the semiconductor material is different from the material of the oxide semiconductor layer. 27. The semiconductor device according to claim 26, further comprising a second trench in the first insulating layer, wherein the second insulating layer is adjacent to an inner wall surface of the second trench; and a third insulating layer filling the second trench. The semiconductor device according to claim 26, further comprising a source electrode or a drain electrode in contact with the oxide semiconductor layer. 29. The semiconductor device according to claim 26, wherein the second insulating layer is in contact with a side surface of the oxide semiconductor layer. The semiconductor device according to claim 26, wherein the oxide semiconductor layer has a U-shaped cross-sectional shape, wherein the oxide semiconductor layer contains crystals having a substantially perpendicular to the oxide semiconductor The c-axis of the surface of the layer. The semiconductor device according to claim 26, wherein the inner wall surface includes at least a bottom surface of the first trench. The semiconductor device of claim 27, wherein an inner wall surface of the first trench includes at least a bottom surface of the first trench, and wherein an inner wall surface of the second trench includes at least the second trench The bottom surface of the slot. The semiconductor device according to claim 27, wherein the horizontal position of the bottom of the second trench is deeper than the horizontal position of the bottom of the first trench - 52-
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