JP2013157359A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a semiconductor device, employing an oxide semiconductor, in which electric characteristics are stabilized and reliability is improved.SOLUTION: A method of manufacturing a semiconductor device employing an oxide semiconductor includes forming an oxide semiconductor film and then introducing oxygen into the oxide semiconductor film (first oxygen introduction processing), and forming an island-shaped oxide semiconductor layer by etching the oxide semiconductor film after the first oxygen introduction processing, and introducing oxygen at least to a side end portion of the island-shaped oxide semiconductor layer (second oxygen introduction processing).

Description

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

A technique for forming a transistor (also referred to as a thin film transistor (TFT)) using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to an electronic device such as an integrated circuit or an image display device. A silicon-based semiconductor material is widely known as a semiconductor thin film applicable to a transistor, but an oxide semiconductor has attracted attention as another material.

For example, research and development of oxide semiconductors such as zinc oxide and indium gallium zinc oxide have been activated. Note that an oxide semiconductor is known to have oxygen released during the manufacturing process to form defects (see Patent Document 1).

JP 2011-222767 A

Oxygen vacancies (oxygen defects) generated when oxygen is released from the oxide semiconductor serve as donors and generate electrons as carriers. In particular, an island-shaped semiconductor layer in which a channel of a transistor is formed is likely to have defects on the side surface, the resistance of the side surface is reduced, and a parasitic channel due to oxygen vacancy is likely to occur. When a parasitic channel is generated on the side surface of the island-shaped semiconductor layer, an unintended current (also referred to as leakage current or leakage current) flows between the source and drain through the parasitic channel, increasing the off-state current of the transistor or increasing the threshold value. It causes deterioration of electric characteristics of the transistor such as increase in voltage variation.

In view of such a problem, an object of one embodiment of the present invention is to manufacture a semiconductor device including an oxide semiconductor that has high reliability and stable electrical characteristics.

In order to solve the above problems, in a method for manufacturing a semiconductor device using an oxide semiconductor, after an oxide semiconductor film is formed, oxygen is introduced into the oxide semiconductor film (first oxygen introduction treatment). After the oxygen introduction treatment, the oxide semiconductor film is processed into an island-shaped oxide semiconductor layer, and oxygen is introduced into at least a side end portion of the island-shaped oxide semiconductor layer (second oxygen introduction treatment).

Therefore, according to one embodiment of the present invention, an island-shaped oxide semiconductor layer is formed by forming an oxide semiconductor film, performing a first oxygen introduction treatment on the oxide semiconductor film, and etching the oxide semiconductor film. , A manufacturing method of a semiconductor device in which a second oxygen introduction treatment is performed on at least a side end portion of the oxide semiconductor layer.

Oxygen vacancies on the surface of the oxide semiconductor film react with an insulating film or the like in contact with the oxide semiconductor to generate carriers and change characteristics of the semiconductor device. Therefore, oxygen vacancies on the surface of the oxide semiconductor film are preferably reduced as much as possible. In addition, since oxygen may be extracted in the formation process of the oxide semiconductor film, it is preferable that the oxide semiconductor film include oxygen in excess relative to the stoichiometric composition ratio. An oxide semiconductor film in which oxygen is excessively contained and oxygen vacancies are reduced can suppress the formation of carriers, exhibit stable electrical characteristics, and be a highly reliable semiconductor device.

The semiconductor device of one embodiment of the present invention can be applied to either a top-gate transistor or a bottom-gate transistor. In the case of a top-gate transistor, an oxide semiconductor film is formed, a first oxygen introduction treatment is performed on the oxide semiconductor film, and an island-shaped oxide semiconductor layer is formed by etching the oxide semiconductor film. A second oxygen introduction treatment is performed on at least a side end portion of the oxide semiconductor layer, a gate insulating layer is formed over the oxide semiconductor layer, a gate electrode layer is formed over the gate insulating layer, and the oxide semiconductor layer is electrically A source electrode layer and a drain electrode layer to be connected to each other may be formed. As the first oxygen introduction treatment and the second oxygen introduction treatment, for example, an ion implantation method can be applied.

In the case of a bottom-gate transistor, a gate electrode layer is formed, a gate insulating layer is formed over the gate electrode layer, an oxide semiconductor film is formed over the gate insulating layer, and the first oxygen is formed over the oxide semiconductor film. An introduction treatment is performed, and the oxide semiconductor film is etched to form an island-shaped oxide semiconductor layer. At least a side end portion of the oxide semiconductor layer is subjected to a second oxygen introduction treatment, and the oxide semiconductor layer is electrically connected to the oxide semiconductor layer. A source electrode layer and a drain electrode layer to be connected to each other may be formed. As the first oxygen introduction treatment and the second oxygen introduction treatment, for example, plasma treatment can be applied.

In the second oxygen introduction treatment, as a method for introducing oxygen into at least the side end portion, after the first oxygen introduction treatment, the oxide semiconductor film is etched using a mask to form an island-shaped oxide semiconductor layer. A method in which oxygen is introduced into the side end portion of the oxide semiconductor layer and then the mask is removed can be applied by performing the second oxygen introduction treatment with the mask formed and leaving the mask. At this time, if the thickness of the mask is greater than or equal to 1 μm and less than or equal to 2 μm, oxygen is not introduced into the oxide semiconductor layer overlapping the mask by the second oxygen introduction treatment. I do not receive it.

Note that the region overlapping with the mask of the oxide semiconductor layer can be a film including a crystal having a c-axis substantially perpendicular to the surface. When the oxide semiconductor layer has a c-axis that is substantially perpendicular to the surface, variation in electrical characteristics of the transistor due to irradiation with visible light or ultraviolet light can be reduced.

With the semiconductor device of one embodiment of the present invention, a semiconductor device including an oxide semiconductor that has high reliability and stable electrical characteristics can be manufactured.

4A to 4D illustrate a method for manufacturing a semiconductor device of one embodiment of the present invention. 4A to 4D illustrate a method for manufacturing a semiconductor device of one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device of one embodiment of the present invention. The figure which calculated the introduction depth of the oxygen introduce | transduced into the oxide semiconductor layer. 4A to 4D illustrate a method for manufacturing a semiconductor device of one embodiment of the present invention. 4A to 4D illustrate a method for manufacturing a semiconductor device of one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device of one embodiment of the present invention. 4A and 4B are a cross-sectional view, a top view, and a circuit diagram illustrating one embodiment of a semiconductor device. 8A and 8B are a circuit diagram and a perspective view illustrating one embodiment of a semiconductor device. 8A and 8B are a cross-sectional view and a top view illustrating one embodiment of a semiconductor device. 10A and 10B each illustrate an electronic device that is one embodiment of a semiconductor device.

Hereinafter, embodiments of the invention disclosed in this specification will be described in detail with reference to the drawings. However, the invention disclosed in this specification is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed. Further, the invention disclosed in this specification is not construed as being limited to the description of the embodiments below. The ordinal numbers attached as the first and second are used for convenience and do not indicate the order of steps or the order of lamination. In addition, a specific name is not shown as a matter for specifying the invention in this specification.

In the present specification and the like, the terms “upper” and “lower” do not limit that the positional relationship between the components is “directly above” or “directly below”. For example, the expression “a gate electrode layer over an insulating layer” does not exclude the case where another component is included between the insulating layer and the gate electrode layer.

Further, in this specification and the like, the terms “electrode layer” and “wiring layer” do not functionally limit these components. For example, an “electrode layer” may be used as part of a “wiring layer” and vice versa. Furthermore, the terms “electrode layer” and “wiring layer” include a case where a plurality of “electrode layers” and “wiring layers” are integrally formed.

In addition, the functions of “source” and “drain” may be switched when transistors having different polarities are employed or when the direction of current changes in circuit operation. Therefore, in this specification, the terms “source” and “drain” can be used interchangeably.

Note that in this specification and the like, “electrically connected” includes a case of being connected via “something having an electric action”. Here, the “thing having some electric action” is not particularly limited as long as it can exchange electric signals between connection targets.

For example, “thing having some electric action” includes electrodes and wirings.

(Embodiment 1)
In this embodiment, one embodiment of a method for manufacturing a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

First, the oxide semiconductor film 403 is formed over the substrate 400 (see FIG. 1A).

There is no particular limitation on the substrate that can be used, but it is necessary that the substrate has at least heat resistance enough to withstand subsequent heat treatment. For example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used.

Alternatively, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or a substrate in which a semiconductor element is provided over these substrates can be used.

Note that a base insulating layer may be provided before the oxide semiconductor film 403 is provided. For the base insulating layer, a sputtering method, an MBE method, a CVD method, a pulse laser deposition method, an ALD method, or the like can be used as appropriate. Note that when the base insulating layer is formed by a sputtering method, impurity elements such as hydrogen can be reduced.

As the base insulating layer, an oxide insulating layer such as silicon oxide, gallium oxide, aluminum oxide, silicon oxynitride, silicon nitride oxide, hafnium oxide, or tantalum oxide is preferably used. In addition, these compounds can be used in the form of a single layer structure or a laminated structure of two or more layers. In the case of a stacked structure, for example, a silicon oxide film formed by a CVD method may be used for a base insulating layer in contact with a substrate. The insulating layer in contact with the oxide insulating layer is an oxide insulating layer with a reduced hydrogen concentration, so that diffusion of hydrogen to the oxide semiconductor is suppressed and oxygen vacancies in the oxide semiconductor layer Since oxygen is supplied from the oxide insulating layer, the electric characteristics of the transistor can be improved.

Note that silicon oxynitride refers to a silicon oxynitride having a higher oxygen content than nitrogen in the composition. For example, at least oxygen is 50 atomic% or more and 70 atomic% or less, and nitrogen is 0.5 atomic% or more and 15 or less. The atomic percent or less and silicon is contained in the range of 25 atomic percent to 35 atomic percent. However, the above ranges are those measured using Rutherford Backscattering Spectrometry (RBS) or Hydrogen Forward Scattering (HFS). Further, the content ratio of the constituent elements takes a value that the total does not exceed 100 atomic%.

Since the base insulating layer is in contact with the oxide semiconductor film 403, it is preferable that oxygen in an amount exceeding at least the stoichiometric composition ratio exists in the layer (in the bulk). For example, in the case where a silicon oxide layer is used as the base insulating layer, SiO _{2 (2 + α)} (where α> 0) is set.

Note that in the case where an oxide insulating layer is used as the base insulating layer, oxygen can be supplied to the oxide semiconductor film 403 by heating with the oxide semiconductor film 403 provided over the oxide insulating layer. In addition, oxygen vacancies in the oxide semiconductor film 403 can be reduced and semiconductor characteristics can be improved. Oxygen may be supplied to the oxide semiconductor film 403 by performing a heating step with at least part of the oxide semiconductor film 403 and the oxide insulating layer in contact with each other. Note that the heat treatment may be performed before the oxide semiconductor film 403 is processed into the island-shaped oxide semiconductor layer 409 or after the oxide semiconductor film 403 is processed into an island-shape. However, it is preferable to perform heat treatment before processing into an island shape because the amount of oxygen released from the base insulating layer to the outside is small, so that more oxygen can be supplied to the oxide semiconductor film.

The oxide semiconductor film 403 can be formed by a sputtering method, an evaporation method, a pulsed laser deposition (PLD method), a PCVD method, an ALD method, an MBE method, or the like.

An oxide semiconductor used for the oxide semiconductor film 403 preferably contains at least indium (In) or zinc (Zn). In particular, In and Zn are preferably included. In addition to the stabilizer, gallium (Ga) is preferably used as a stabilizer for reducing variation in electrical characteristics of the transistor including the oxide semiconductor. In addition, it is preferable to have tin (Sn), hafnium (Hf), and aluminum (Al) as the stabilizer.

As other stabilizers, lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), One or more of dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), gadolinium (Gd), cerium (Ce), zirconium (Zr) You may have seeds.

For example, as an oxide semiconductor, indium oxide, tin oxide, and zinc oxide, which are oxides of a single metal, In—Zn oxide, Sn—Zn oxide, Al—Zn, which are oxides of a binary metal, Oxide, Zn—Mg oxide, Sn—Mg oxide, In—Mg oxide, In—Ga oxide, In—Ga—Zn oxide that is an oxide of a ternary metal, In-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn Oxide, In—La—Zn oxide, In—Ce—Zn oxide, In—Pr—Zn oxide, In—Nd—Zn oxide, In—Sm—Zn oxide, In -Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, n-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn -Based oxides, In-Sn-Ga-Zn-based oxides that are oxides of quaternary metals, In-Hf-Ga-Zn-based oxides, In-Al-Ga-Zn-based oxides, In-Sn- An Al—Zn-based oxide, an In—Sn—Hf—Zn-based oxide, or an In—Hf—Al—Zn-based oxide can be used.

Note that here, for example, an In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn as its main components, and there is no limitation on the ratio of In, Ga, and Zn. Moreover, metals other than In, Ga, and Zn may be contained.

Alternatively, a material represented by InMO ₃ (ZnO) _m (m> 0 is satisfied, and m is not an integer) may be used as the oxide semiconductor. Note that M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co. Alternatively, a material represented by In ₂ SnO ₅ (ZnO) _n (n> 0 is satisfied, and n is an integer) may be used as the oxide semiconductor.

For example, In: Ga: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3) or In: Ga: Zn = 2: 2: 1 (= 2/5: 2/5: 1). / 5), In: Ga: Zn = 3: 2: 1 (= 1/2: 1/3: 1/6) atomic ratio In—Ga—Zn-based oxides and oxides in the vicinity of the composition thereof. Can be used. Alternatively, In: Sn: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3), In: Sn: Zn = 2: 1: 3 (= 1/3: 1/6: 1) / 2) or In: Sn: Zn = 2: 1: 5 (= 1/4: 1/8: 5/8) atomic ratio In—Sn—Zn-based oxide or an oxide in the vicinity of the composition. Use it.

Note that for example, the composition of an oxide in which the atomic ratio of In, Ga, and Zn is In: Ga: Zn = a: b: c (a + b + c = 1) has an atomic ratio of In: Ga: Zn = A: B: C, (A + B + C = 1) is the vicinity of r of the oxide composition, a, b, c are (a−A) ² + (b−B) ² + (c−C) ² ≦ It refers to meet the r ^2. For example, r may be 0.05. The same applies to other oxides.

However, the composition is not limited thereto, and a material having an appropriate composition may be used depending on required semiconductor characteristics (mobility, threshold value, variation, etc.). In order to obtain the required semiconductor characteristics, it is preferable that the carrier concentration, the impurity element concentration, the defect density, the atomic ratio between the metal element and oxygen, the interatomic bond distance, the density, and the like be appropriate.

For example, high mobility can be obtained relatively easily with an In—Sn—Zn-based oxide. However, mobility can be increased by reducing the defect density in the bulk also in the case of using an In—Ga—Zn-based oxide.

An oxide semiconductor film is in a single crystal state, a polycrystalline (also referred to as polycrystal) state, an amorphous state, or the like. Preferably, the oxide semiconductor film is a CAAC-OS film (C Axis Crystallized Oxide Semiconductor) film.

The CAAC-OS film is not completely single crystal nor completely amorphous. The CAAC-OS film is an oxide semiconductor film with a crystal-amorphous mixed phase structure where crystal parts and amorphous parts are included in an amorphous phase. Note that the crystal part is often large enough to fit in a cube whose one side is less than 100 nm. Further, in the observation image obtained by a transmission electron microscope (TEM), the boundary between the amorphous part and the crystal part included in the CAAC-OS film is not clear. Further, a grain boundary (also referred to as a grain boundary) cannot be confirmed in the CAAC-OS film by TEM. Therefore, in the CAAC-OS film, reduction in electron mobility due to grain boundaries is suppressed.

In the crystal part included in the CAAC-OS film, the c-axis is aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface, and triangular when viewed from the direction perpendicular to the ab plane. It has a shape or hexagonal atomic arrangement, and metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers as viewed from the direction perpendicular to the c-axis. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. In this specification, a simple term “perpendicular” includes a range from 85 ° to 95 °. In addition, a simple term “parallel” includes a range from −5 ° to 5 °.

Note that the distribution of crystal parts in the CAAC-OS film is not necessarily uniform. For example, in the formation process of the CAAC-OS film, in the case where crystal growth is performed from the surface side of the oxide semiconductor film, the proportion of crystal parts in the vicinity of the surface of the oxide semiconductor film is higher in the vicinity of the surface. Further, when an impurity or the like is added to the CAAC-OS film, the crystal part in a region to which the impurity is added becomes amorphous in some cases.

Since the c-axis of the crystal part included in the CAAC-OS film is aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface, the shape of the CAAC-OS film (formation surface) Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface). Note that the c-axis direction of the crystal part is parallel to the normal vector of the surface where the CAAC-OS film is formed or the normal vector of the surface. The crystal part is formed by film formation or by performing crystallization treatment such as heat treatment after film formation.

By using the CAAC-OS film, change in electrical characteristics of the transistor due to irradiation with visible light or ultraviolet light can be reduced. Thus, a highly reliable transistor can be obtained.

Note that part of oxygen included in the oxide semiconductor film may be replaced with nitrogen.

Note that as an example, in the case where the oxide semiconductor film is formed using an In—Zn-based metal oxide, the composition ratio of the target in terms of the number of atoms is In / Zn = 1 to 100, preferably In / Zn = 1 to 1. 20, More preferably, In / Zn = 1 to 10. By setting the atomic ratio of Zn within a preferable range, the field effect mobility can be improved. Here, in order to include oxygen excessively, it is preferable that the atomic ratio of the metal oxide, In: Zn: O = X: Y: Z, is Z> 1.5X + Y.

In the case where an In—Ga—Zn-based oxide is formed as the oxide semiconductor film by a sputtering method, the atomic ratio is preferably In: Ga: Zn = 1: 1: 1, 4: 2: 3, 3: 1. : 2, 1: 1: 2, 2: 1: 3, or 3: 1: 4 In—Ga—Zn—O target is used. When an oxide semiconductor film is formed using the In—Ga—Zn—O target having the above-described atomic ratio, a polycrystalline or CAAC-OS film can be easily formed.

In the case where an In—Sn—Zn-based oxide is formed as the oxide semiconductor film by a sputtering method, the atomic ratio is preferably In: Sn: Zn = 1: 1: 1, 2: 1: 3, 1 : In: Sn—Zn—O target represented by 2: 2 or 20:45:35 is used. When an oxide semiconductor layer is formed using the In—Sn—Zn—O target having the above-described atomic ratio, polycrystal or CAAC is easily formed.

Here, the filling rate of the target is 90% to 100%, preferably 95% to 99.9%. By increasing the filling rate of the target, the formed oxide semiconductor layer can be made dense.

Note that a metal oxide that can be used for the oxide semiconductor film has an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. In this manner, when a metal oxide having a wide band gap is used, the off-state current of the transistor can be reduced.

The oxide semiconductor film may have a structure in which a plurality of oxide semiconductor layers are stacked. For example, the oxide semiconductor film is a stack of a first oxide semiconductor film and a second oxide semiconductor film, and the first oxide semiconductor film and the second oxide semiconductor film have different metal oxide compositions. May be used. For example, a ternary metal oxide may be used for the first oxide semiconductor film, and a binary metal oxide may be used for the second oxide semiconductor layer. For example, the first oxide semiconductor film and the second oxide semiconductor film may both be ternary metal oxides.

Alternatively, the constituent elements of the first oxide semiconductor film and the second oxide semiconductor film may be the same, and the composition ratio of the two may be different. For example, the atomic ratio of the first oxide semiconductor film is In: Ga: Zn = 1: 1: 1, and the atomic ratio of the second oxide semiconductor film is In: Ga: Zn = 3: 1: 2. It is good. The atomic ratio of the first oxide semiconductor film is In: Ga: Zn = 1: 3: 2, and the atomic ratio of the second oxide semiconductor film is In: Ga: Zn = 2: 1: 3. It is good.

At this time, the In and Ga contents in the oxide semiconductor film on the side close to the gate electrode (channel side) of the first oxide semiconductor film and the second oxide semiconductor film are preferably In> Ga. The content ratio of In and Ga in the oxide semiconductor film far from the gate electrode (back channel side) is preferably In ≦ Ga.

In oxide semiconductors, heavy metal s orbitals mainly contribute to carrier conduction, and increasing the In content tends to increase the overlap of s orbitals. Compared with an oxide having a composition of In ≦ Ga, high mobility is provided. In addition, since Ga has a larger energy generation energy of oxygen deficiency than In, and oxygen deficiency is less likely to occur, an oxide having a composition of In ≦ Ga has stable characteristics compared to an oxide having a composition of In> Ga. Prepare.

By using an oxide semiconductor with an In> Ga composition on the channel side and an oxide semiconductor with an In ≦ Ga composition on the back channel side, the mobility and reliability of the transistor can be further improved. It becomes.

Alternatively, oxide semiconductors having different crystallinities may be used for the first oxide semiconductor film and the second oxide semiconductor film. That is, a single crystal oxide semiconductor, a polycrystalline oxide semiconductor, an amorphous oxide semiconductor, or a CAAC-OS may be combined as appropriate. In addition, when an amorphous oxide semiconductor is applied to at least one of the first oxide semiconductor film and the second oxide semiconductor film, internal stress and external stress of the oxide semiconductor film 403 are relieved, The variation in characteristics of the transistor is reduced, and the reliability of the transistor can be further improved.

On the other hand, an amorphous oxide semiconductor easily absorbs an impurity serving as a donor such as hydrogen, and oxygen vacancies easily occur. Therefore, an oxide semiconductor having crystallinity such as CAAC-OS is preferably used for the oxide semiconductor layer on the channel side.

Alternatively, the oxide semiconductor film 403 may have a stacked structure of three or more layers, and a structure in which an amorphous oxide semiconductor layer is sandwiched between a plurality of crystalline oxide semiconductor layers. Alternatively, a structure in which an oxide semiconductor layer having crystallinity and an amorphous oxide semiconductor layer are alternately stacked may be employed.

The above structures in the case where the oxide semiconductor film 403 has a stacked structure of a plurality of layers can be used in appropriate combination.

Note that the number of alkali metals and alkaline earth metals in the oxide semiconductor layer is preferably small, and the concentration thereof is preferably 1 × 10 ¹⁸ atoms / cm ³ or more, more preferably 2 × 10 ¹⁶ atoms / cm ³ or less. And This is because an alkali metal and an alkaline earth metal may generate carriers when combined with an oxide semiconductor, which causes an increase in off-state current of the transistor.

The thickness of the oxide semiconductor film is 1 nm to 100 nm, preferably 1 nm to 35 nm.

The oxide semiconductor film is preferably formed by a sputtering method with a substrate heating temperature of 100 ° C. to 600 ° C., preferably 150 ° C. to 550 ° C., more preferably 200 ° C. to 500 ° C. in an oxygen gas atmosphere. . The higher the substrate heating temperature during film formation, the lower the impurity element concentration of the obtained oxide semiconductor film. In addition, the atomic arrangement in the oxide semiconductor film is aligned, the density is increased, and a polycrystalline or CAAC-OS film is easily formed.

Further, even when a film is formed in an oxygen gas atmosphere, a polycrystalline or CAAC-OS film is easily formed because an excess atom such as a rare gas is not included. However, a mixed atmosphere of oxygen gas or a rare gas such as argon may be used. In that case, the proportion of oxygen gas is 30% by volume or more, preferably 50% by volume or more, and more preferably 80% by volume or more. Note that argon and oxygen used for forming the oxide semiconductor film preferably do not contain water, hydrogen, or the like. For example, it is preferable that the purity of argon is 9N (dew point −121 ° C., water 0.1 ppb, hydrogen 0.5 ppb), and the purity of oxygen is 8N (dew point −112 ° C., water 1 ppb, hydrogen 1 ppb).

In this embodiment, an In—Ga—Zn-based oxidation with an atomic ratio of In: Ga: Zn = 3: 1: 2 is used in an atmosphere where the flow ratio of argon and oxygen is 2: 1. A physical film is formed to 20 nm.

Since an amorphous oxide semiconductor can obtain a flat surface relatively easily, a transistor using the oxide semiconductor can reduce interface scattering of carriers (electrons) during operation, and is relatively easy and relatively high. Mobility can be obtained.

In addition, in an oxide semiconductor having crystallinity, defects in a bulk can be further reduced, and mobility higher than that of an oxide semiconductor in an amorphous state can be obtained by increasing surface flatness. In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on the flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, more preferably Is preferably formed on a surface of 0.1 nm or less.

Note that Ra is a three-dimensional extension of the centerline average roughness defined in JIS B601 so that it can be applied to a surface. “A value obtained by averaging the absolute values of deviations from a reference surface to a specified surface” "And is defined by the following equation.

In the above, S ₀ is surrounded by four points represented by the measurement plane (coordinates (x ₁ , y ₁ ) (x ₁ , y ₂ ) (x ₂ , y ₁ ) (x ₂ , y ₂ )). (Rectangular region) indicates the area, and Z ₀ indicates the average height of the measurement surface. Ra can be evaluated with an atomic force microscope (AFM). The measurement surface is a surface indicated by all measurement data, and is composed of three parameters (X, Y, Z), and is represented by Z = F (X, Y).

The reference plane is a plane parallel to the XY plane at the average height of the designated plane. In other words, the average value of the height of the specific surface when the Z _0, the height of the reference surface is also represented by Z _0.

In this manner, in the region where the channel of the oxide semiconductor layer is formed, planarization treatment may be performed so that the average surface roughness of the base insulating layer is 0.3 nm or less. The planarization treatment may be performed before formation of the oxide semiconductor film.

For example, dry etching or the like may be performed as the planarization process. Here, as an etching gas, a chlorine-based gas such as chlorine, boron chloride, silicon chloride, or carbon tetrachloride, a fluorine-based gas such as carbon tetrafluoride, sulfur fluoride, or nitrogen fluoride may be used.

Further, it is preferable that hydrogen contained in the oxide semiconductor layer be as small as possible. This hydrogen may be contained as a hydrogen molecule, water, a hydroxyl group, or other hydride in addition to a hydrogen atom. Therefore, heat treatment for removing (dehydrating or dehydrogenating) excess hydrogen (including water and a hydroxyl group) included in the oxide semiconductor layer is preferably performed. The temperature of the heat treatment is 300 ° C. or more and 700 ° C. or less, or less than the strain point of the substrate. The heat treatment can be performed in a reduced pressure atmosphere or an inert atmosphere. Further, the heat treatment may be performed after the oxide semiconductor film is formed and before being processed into an island shape, or may be performed after being processed into an island shape. Further, the heat treatment for dehydration and dehydrogenation may be performed a plurality of times, and may be combined with other heat treatments.

The heat treatment is preferably performed by performing a heat treatment in a reduced pressure atmosphere or an inert atmosphere and then switching to an oxidizing atmosphere while maintaining the temperature. When heat treatment is performed in a reduced pressure atmosphere or an inert atmosphere, the concentration of impurities (for example, hydrogen) in the oxide semiconductor layer can be reduced, but oxygen deficiency may occur at the same time. The generated oxygen deficiency can be reduced by heat treatment in an oxidizing atmosphere.

When the oxide semiconductor layer is subjected to heat treatment, an impurity element such as hydrogen in the film can be extremely reduced. As a result, the field effect mobility of the transistor can be increased to near the ideal field effect mobility.

Next, first oxygen introduction treatment is performed on the oxide semiconductor film 403 (see FIG. 1B).

As a method for introducing oxygen 450, oxygen (including at least one of oxygen radicals, oxygen atoms, oxygen atom ions, and oxygen molecular ions) is used as an ion implantation method, ion doping method, plasma immersion ion implantation method, plasma. It may be introduced into the oxide semiconductor film by treatment or the like.

In this embodiment, oxygen is introduced by an ion implantation method using oxygen atom ions as the first oxygen introduction treatment. A gas cluster ion beam may be used for the ion implantation method. The oxygen introduction treatment may be performed on the entire surface at once, or may be performed using a linear ion beam or the like.

Next, a resist mask 436 is provided over the oxide semiconductor film 403, and the oxide semiconductor film 403 is selectively etched, so that an island-shaped oxide semiconductor layer 409 is formed (see FIG. 1C).

As a method for manufacturing the resist mask 436, an inkjet method or a photolithography process can be used. The thickness of the resist mask 436 is preferably 1 μm or more and 2 μm or less. The resist mask 436 also functions as a mask for performing the second oxygen introduction treatment in a subsequent formation step, and thus can sufficiently barrier so that oxygen is not introduced into a region overlapping with the resist mask 436. It is preferable that it is the film thickness.

Etching of the oxide semiconductor film 403 may be dry etching, wet etching, or both. For example, as an etchant used for wet etching of the oxide semiconductor film 403, a mixed solution of phosphoric acid, acetic acid, and nitric acid, or the like can be used. Moreover, ITO-07N (manufactured by Kanto Chemical Co., Inc.) may be used. As the dry etching, a parallel plate RIE (Reactive Ion Etching) method, an ICP (Inductively Coupled Plasma) etching method, or the like can be used. Etching conditions (such as the amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, and the electrode temperature on the substrate side) may be adjusted as appropriate so that the desired processed shape can be etched.

By etching, the thickness of the side edge portion of the oxide semiconductor film is reduced to be a tapered shape. Although different depending on the composition of the oxide semiconductor layer, etching conditions, and the like, the side end portion of the oxide semiconductor layer has a taper angle of about 20 ° to 50 ° from the substrate surface. Note that the taper angle refers to an inclination angle formed between a side surface and a bottom surface of a layer having a tapered shape when the layer is observed from a direction perpendicular to a cross section thereof (a surface orthogonal to the surface of the substrate).

Subsequently, a second oxygen introduction treatment is performed on the oxide semiconductor layer 409. In the second oxygen introduction treatment, oxygen may be introduced at least into the side end portion of the oxide semiconductor layer. Note that the side edge portion of the oxide semiconductor layer 409 here refers to a region where the thickness is reduced by etching when the oxide semiconductor film 403 is processed into the island-shaped oxide semiconductor layer 409. In the second oxygen introduction process, oxygen may be introduced not only into the side end portion but also into a region damaged by etching.

In the second oxygen introduction treatment, after the first oxygen introduction treatment, oxygen is again applied to a region in which the region where oxygen is excessively introduced (near the oxide semiconductor film surface) is removed by etching treatment. It is a process to introduce. Therefore, even if a region where oxygen is excessively introduced is removed, oxygen vacancies in the region can be compensated by the second oxygen introduction treatment.

In this embodiment, oxygen 450 is introduced into the side end portion of the oxide semiconductor layer 409 by performing second oxygen introduction treatment on the oxide semiconductor layer 409 with the resist mask 436 attached (FIG. 1 D)).

Since oxygen 450 is introduced with the resist mask 436 attached, damage to the oxide semiconductor layer which overlaps with a region where the resist mask 436 is provided can be reduced by oxygen introduction treatment.

Therefore, the oxide semiconductor layer 409 in a region overlapping with the resist mask 436 does not have a broken crystal state and can be a film including a crystal having a c-axis substantially perpendicular to the surface, for example. In addition, in a region where oxygen is introduced by the second oxygen introduction treatment (a side end portion of the oxide semiconductor layer 409), the crystal state is changed by the second oxygen introduction treatment, for example, an amorphous state is obtained. There is.

The second oxygen introduction treatment can be performed using the same method as the first oxygen introduction treatment. Note that the conditions for introducing oxygen may be changed between the second oxygen introduction treatment and the first oxygen introduction treatment, or the same conditions may be used. For example, in the second oxygen introduction process, the acceleration voltage at the time of ion implantation may be smaller than the acceleration voltage at the time of the first oxygen introduction process. By reducing the acceleration voltage during the second oxygen introduction treatment, damage to the oxide semiconductor layer can be reduced.

In the second oxygen introduction treatment, ion implantation may be performed at an angle from the normal direction of the substrate in accordance with the taper angle of the side end portion of the oxide semiconductor layer 409. For example, ion implantation may be performed by adjusting the ion implantation apparatus or the substrate 400 so that ions can be implanted vertically into the side end portion of the oxide semiconductor layer 409.

Here, the calculation result of the oxygen introduction depth in the oxide semiconductor film in the case where the oxygen introduction treatment is performed on the oxide semiconductor film is shown. For calculation, software called TRIM (Transport of Ion in Matter) was used. TRIM is software for calculating the ion introduction process by the Monte Carlo method. In the calculation, an amorphous In—Ga—Zn-based oxide film (composition ratio [In: Ga: Zn] = [3] provided on a silicon oxide film (SiO ₂ , film density 2.3 g / cm ² ). : 2], film density 6.8 g / cm ² , film thickness 20 nm), oxygen atom ions with an acceleration voltage of 2.5 kV and a dose of 1.0 × 10 ¹⁶ ions / cm ² were introduced. did. FIG. 4A shows the concentration of oxygen introduced into the oxide semiconductor film.

The horizontal axis in FIG. 4A is the oxygen introduction depth (nm) from the surface of the oxide semiconductor film, and the vertical axis is the concentration of introduced oxygen (atoms / cm ³ ). As shown in FIG. 4A, the maximum value of the concentration of oxygen introduced into the oxide semiconductor film is in the vicinity of a depth of 5 nm, and the concentration of oxygen introduced in a region of 15 nm or more in depth is Is 1/100 or less of the concentration in the 5 nm region. In the region where the depth is 18 nm or more, the oxygen introduction concentration is 1.0 × 10 ¹⁹ or less.

Therefore, when an oxide semiconductor film is processed into an island-shaped oxide semiconductor layer, a region with a high oxygen introduction concentration is removed by etching at a side end portion of the oxide semiconductor layer, and a region with a low oxygen introduction concentration is removed. Is exposed on the surface of the oxide semiconductor layer. On the surface, oxygen vacancies generate carriers and cause variation in electrical characteristics of the oxide semiconductor layer.

Therefore, in order to fill oxygen vacancies at the side end portions of the oxide semiconductor layer, it is necessary to perform a second oxygen introduction treatment.

Subsequently, the amount of oxygen introduced when the second oxygen introduction treatment is performed on the side end portion of the oxide semiconductor layer is calculated. 4B, after the first oxygen introduction treatment, before the second oxygen introduction treatment is performed on a region where the depth from the surface of the oxide semiconductor film to the depth of 15 nm is removed by etching (FIG. 4B ) And the concentration of oxygen introduced (indicated by the solid line in FIG. 4B) when the second oxygen introduction treatment is performed after the etching.

The horizontal axis of FIG. 4B is the introduction depth (nm) of oxygen from the surface of the oxide semiconductor layer, and the vertical axis is the concentration of introduced oxygen (atoms / cm ³ ). Note that the introduction depth of oxygen from the surface of the oxide semiconductor layer was based on the surface of the oxide semiconductor layer before the surface was removed by etching. The first oxygen introduction treatment was performed under the same conditions as the oxygen introduction treatment shown in FIG. 4A, and then the region from the surface having a depth of 15 nm was removed by etching. As shown by a broken line in FIG. 4B, a region where the concentration of the introduced oxygen is high is removed from the side end portion of the oxide semiconductor layer after the first oxygen introduction treatment. Only a region where the amount of oxygen introduced is small remains. As a second oxygen introduction treatment, the result of introducing oxygen atom ions with an acceleration voltage of 2.5 kV and a dose of 1.0 × 10 ¹⁶ ions / cm ² is shown by a solid line in FIG. It is a result.

As shown in FIG. 4B, the concentration of oxygen introduced into the side edge portion of the oxide semiconductor layer by the second oxygen introduction treatment is the same as that in the first oxygen introduction treatment shown in FIG. It is about the same as the oxygen concentration near the maximum value. Accordingly, even if the region where oxygen is introduced at a high concentration is removed by performing the second oxygen introduction treatment, oxygen is sufficiently introduced by performing the second oxygen introduction treatment thereafter. You can see that

In the semiconductor device of this embodiment, the first oxygen introduction treatment after the oxide semiconductor film 403 is formed, and the second oxygen after the oxide semiconductor film 403 is formed in the island-shaped oxide semiconductor layer 409. By the introduction treatment, oxygen vacancies in the oxide semiconductor layer are reduced; thus, a highly reliable semiconductor device with stable electric characteristics can be obtained.

Next, the resist mask 436 is removed, and a gate insulating layer 402 is formed over the oxide semiconductor layer 409 (see FIG. 2A).

Note that oxygen introduction treatment may be performed before the gate insulating layer 402 is formed and after the resist mask is removed. The oxygen introduction treatment may be performed on at least the side end portion of the oxide semiconductor layer 409 and a region damaged by etching, resist peeling, or the like.

As a method for introducing oxygen, a method similar to that for the first oxygen introduction treatment and the second oxygen introduction treatment may be used. As a method for introducing oxygen after removing the resist, when plasma treatment is used, damage to the oxide semiconductor layer 409 is reduced.

As the material of the gate insulating layer 402, hafnium oxide, yttrium oxide, hafnium silicate (HfSi _x O _y , x> 0, y> 0), hafnium silicate to which nitrogen is added, hafnium aluminate (HfAl _x O _y , x > 0, y> 0), and high-k materials such as lanthanum oxide can be used to reduce gate leakage current. Further, the gate insulating layer 402 may have a single-layer structure or a stacked structure.

The thickness of the gate insulating layer 402 is 1 nm to 20 nm, and a sputtering method, an MBE method, a CVD method, a PLD method, an ALD method, or the like can be used as appropriate. The gate insulating layer 402 is formed using a sputtering apparatus that performs film formation in a state where a plurality of substrate surfaces are set substantially perpendicular to the surface of the sputtering target, that is, a so-called CP sputtering apparatus (Column Plasma Sputtering system). May be.

In this embodiment, silicon oxynitride is formed to a thickness of 20 nm by a CVD method.

In addition, since the gate insulating layer 402 is in contact with the oxide semiconductor layer, oxygen in an amount exceeding at least the stoichiometric composition ratio is preferably present in the layer (in the bulk).

Note that planarization treatment may be performed on the top surface of the oxide semiconductor layer 409 in order to improve the coverage with the gate insulating layer 402. In particular, when an insulating layer with a small thickness is used as the gate insulating layer 402, the surface of the oxide semiconductor layer 409 is preferably flat.

Note that after the gate insulating layer is provided, oxygen introduction treatment may be further performed on the oxide semiconductor layer 409. In the oxygen introduction treatment for the oxide semiconductor layer 409, oxygen may be introduced at least in the side end portion or the region damaged by the etching of the oxide semiconductor layer 409. Further, the oxygen introduction treatment may be performed on the entire surface of the oxide semiconductor layer. Since oxygen is introduced through the gate insulating layer 402, damage to the oxide semiconductor layer 409 in the oxygen introduction treatment is low.

Next, the gate electrode layer 401 is formed over the gate insulating layer 402 so as to overlap with the oxide semiconductor layer 409 (see FIG. 2B).

The material of the gate electrode layer 401 can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium, or an alloy material containing any of these materials as its main component. As the gate electrode layer 401, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or a silicide film such as nickel silicide may be used. Furthermore, conductive materials such as indium tin oxide, indium tin oxide containing tungsten oxide, and indium tin oxide containing titanium oxide can be used. Alternatively, a stacked structure of the conductive material and the metal material can be employed.

Further, as one layer of the gate electrode layer in contact with the gate insulating layer 402, a metal oxide containing nitrogen, specifically, an In—Ga—Zn—O film containing nitrogen, an In—Sn—O film containing nitrogen, An In—Ga—O film containing nitrogen, an In—Zn—O film containing nitrogen, an Sn—O film containing nitrogen, an In—O film containing nitrogen, a metal nitride film (InN, SnN, etc.) Can be used. These films have a work function of 5 eV or 5.5 eV or more, and when used as a gate electrode, the threshold voltage of the electrical characteristics of the transistor can be made positive, so that a so-called normally-off switching element can be realized.

In this embodiment, a stacked structure of a tantalum nitride film with a thickness of 30 nm and a tungsten film with a thickness of 135 nm is formed by a sputtering method.

Next, the insulating layer 407 is provided over the gate electrode layer 401, and the source electrode layer 465a and the drain electrode layer which are electrically connected to the oxide semiconductor layer 409 through the openings provided in the gate insulating layer 402 and the insulating layer 407 465b is formed (see FIG. 2C).

As the insulating layer 407, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a hafnium oxide film, a gallium oxide film, a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, and a nitride film are typically used. A single layer or a stacked layer of an inorganic insulating film such as an aluminum oxide film can be used.

Note that in particular, when aluminum oxide is used for the insulating layer, the blocking effect of preventing passage of both oxygen, impurities such as hydrogen, moisture, hydroxyl groups, hydrides (also referred to as hydrogen compounds), and oxygen is high. Therefore, the aluminum oxide layer prevents impurities such as hydrogen and moisture, which cause fluctuations, from entering the oxide semiconductor layer during and after the manufacturing process, and includes oxygen as a main component material of the oxide semiconductor layer. It functions as a protective film that prevents release.

As a method for forming openings in the gate insulating layer 402 and the insulating layer 407, for example, selective etching using a mask or the like may be performed. Etching may be dry etching or wet etching, and both may be combined to form an opening. The opening only needs to reach the oxide semiconductor layer 409, and the shape is not particularly limited.

The source electrode layer 465a and the drain electrode layer 465b may be formed by filling the openings with a conductive material. The source electrode layer 465a and the drain electrode layer 465b can be formed using a material similar to that used for the gate electrode layer 401 described above.

Through the above process, the transistor 420 can be manufactured.

FIG. 3 shows a top view and a cross-sectional view of the transistor 420 of this embodiment. 3A is a top view of the transistor 420, FIG. 3B is a cross-sectional view taken along dashed-dotted line AB in FIG. 3A, and FIG. 3C is FIG. Sectional drawing in the dashed-dotted line CD is shown.

The transistor 420 includes an oxide semiconductor layer 409 over the substrate 400, a gate insulating layer 402 over the oxide semiconductor layer 409, a gate electrode layer 401 over the gate insulating layer 402, and over the gate insulating layer 402 and the gate electrode layer 401. And the source electrode layer 465a and the drain electrode layer 465b which are electrically connected to the oxide semiconductor layer through openings provided in the insulating layer 407 and the gate insulating layer 402.

The oxide semiconductor layer 409 is subjected to a first oxygen introduction treatment after the oxide semiconductor film is formed and a second oxygen introduction treatment after the oxide semiconductor layer 409 is processed into the island-shaped oxide semiconductor layer 409. The surface of 409 is sufficiently oxygenated. Therefore, oxygen vacancies are less likely to occur in a region where the insulating layer 402 is in contact with the side end portion of the oxide semiconductor layer 409 that overlaps with the gate electrode layer 401 (eg, a region surrounded by a dotted line in FIG. 3C). It is possible to prevent the side end portion from being lowered in resistance. Therefore, a transistor with stable electrical characteristics using an oxide semiconductor can be provided.

This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 2)
In this embodiment, a method for manufacturing a semiconductor device of one embodiment of the present invention, which is different from that in Embodiment 1, will be described with reference to FIGS. In the present embodiment, the same parts as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

In the method for manufacturing the semiconductor device of this embodiment, first, the gate electrode layer 401 is formed over the substrate 400, and the gate insulating layer 402 is formed over the gate electrode layer 401 (see FIG. 5A).

As the substrate 400, a substrate similar to the substrate 400 described in Embodiment 1 can be used. Note that a base insulating layer may be provided before the gate electrode layer 401 is formed. In this embodiment, the base insulating layer has a function of preventing diffusion of impurities from the substrate 400, and is one or more selected from a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, and a silicon nitride oxide film. It can be formed by the film.

The gate electrode layer 401 and the gate insulating layer 402 can be formed using a method and a material similar to those in Embodiment 1. In this embodiment, a tungsten film with a thickness of 100 nm is formed as the gate electrode layer 401 by a sputtering method, and a silicon nitride film with a thickness of 50 nm is formed as a gate insulating layer 402 by a plasma CVD method. A silicon oxynitride film having a thickness of 200 nm is formed. Note that heat treatment for dehydration may be performed after the formation of the gate electrode layer 401 and / or the gate insulating layer 402.

Note that the gate insulating layer 402 is in contact with the oxide semiconductor film 403 to be formed later; therefore, when the gate insulating layer 402 is formed using an oxide insulating layer containing excess oxygen, oxygen can be supplied to the oxide semiconductor film 403, which is preferable. .

Next, an oxide semiconductor film 403 is formed (see FIG. 5B). The oxide semiconductor film 403 can be formed using a method similar to that in Embodiment 1. Note that the gate insulating layer 402 and the oxide semiconductor film 403 are preferably formed successively without exposing the gate insulating layer 402 to the air. When the oxide semiconductor film 403 is formed without exposing the gate insulating layer 402 to the air, impurities such as hydrogen and moisture can be prevented from being adsorbed to the surface of the gate insulating layer 402. In this embodiment, an In—Ga—Zn-based oxidation in which an atomic ratio is In: Ga: Zn = 1: 1: 1 is used in an atmosphere where the flow ratio of argon and oxygen is 2: 1. A material film is formed to a thickness of 35 nm.

Next, first oxygen introduction treatment is performed on the oxide semiconductor film 403 (see FIG. 5C). In this embodiment, oxygen plasma treatment is performed as the oxygen introduction treatment. Note that the oxygen plasma treatment is a treatment in which oxygen 450 (including at least one of oxygen radicals, oxygen atoms, oxygen atom ions, and oxygen molecular ions) is introduced into an oxide semiconductor film, in particular, oxygen is turned into plasma. This refers to the process to be introduced.

Oxygen may be introduced into the oxide semiconductor film 403 using a gas containing oxygen for the plasma generator, or an ozone generator or the like may be used. More specifically, for example, oxygen 450 is generated by using an apparatus for performing an etching process on a semiconductor device, an apparatus for performing ashing on a resist mask, or the like to process the oxide semiconductor film 403. can do.

In the oxygen plasma treatment, oxygen 450 can be introduced into the entire surface of the oxide semiconductor film 403 at a time, so that a higher throughput can be obtained for a substrate with a larger area than the oxygen ion implantation performed in Embodiment 1. An oxygen introduction treatment can be performed.

Next, a resist mask 436 is provided over the oxide semiconductor film 403, and the oxide semiconductor film 403 is etched to form an island-shaped oxide semiconductor layer 409 (see FIG. 6A). The formation of the resist mask 436 and the etching of the oxide semiconductor film 403 can be performed using a method similar to the method described in Embodiment 1.

Next, a second oxygen introduction treatment is performed on the oxide semiconductor layer 409 while the resist mask 436 is left (see FIG. 6B). In the second oxygen introduction treatment, oxygen 450 may be introduced into at least a side end portion of the oxide semiconductor layer 409. In this embodiment, oxygen plasma treatment is performed as the second oxygen introduction treatment. The second oxygen introduction treatment may be performed under the same conditions as the first oxygen introduction treatment, or may be different conditions.

Note that in the case where oxygen plasma treatment is used for the second oxygen introduction treatment, the resist mask 436 may be removed by ashing, and the oxide semiconductor layer 409 may be damaged. For this reason, the second oxygen introduction process may be performed with a smaller applied power than the first oxygen introduction process.

Next, the resist mask 436 is removed, and a source electrode layer 465a and a drain electrode layer 465b are formed over the oxide semiconductor layer 409 and the gate insulating layer 402 (see FIG. 6C). The source electrode layer 465a and the drain electrode layer 465b can be formed using a material similar to that in Embodiment 1. The source electrode layer 465a and the drain electrode layer 465b are formed by forming a conductive film to be the source electrode layer 465a and the drain electrode layer 465b and then etching the conductive film.

Note that after the resist mask 436 is removed, before the conductive film to be the source electrode layer 465a and the drain electrode layer 465b is formed, oxygen introduction treatment may be performed on the oxide semiconductor layer 409. For the oxygen introduction treatment, a method similar to the first oxygen introduction treatment and the second oxygen introduction treatment can be used. Here, oxygen vacancies can be compensated for by removing the resist mask by performing oxygen introduction treatment.

For etching the conductive film to be the source electrode layer 465a and the drain electrode layer 465b, a gas containing chlorine, for example, chlorine (Cl ₂ ), boron trichloride (BCl ₃ ), silicon tetrachloride (SiCl ₄ ), carbon tetrachloride ( A gas containing CCl ₄ ) or the like can be used. Alternatively, a gas containing fluorine, for example, a gas containing carbon tetrafluoride (CF ₄ ), sulfur fluoride (SF ₆ ), nitrogen fluoride (NF ₃ ), trifluoromethane (CHF ₃ ), or the like can be used. Alternatively, a gas obtained by adding a rare gas such as helium (He) or argon (Ar) to these gases can be used.

As an etching method, a parallel plate RIE (Reactive Ion Etching) method or an ICP (Inductively Coupled Plasma) etching method can be used. Etching conditions (such as the amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, the substrate-side electrode temperature, etc.) are adjusted as appropriate so that the desired processed shape can be etched.

Further, ultraviolet light or KrF laser light is preferably used for light exposure for forming a resist mask used for etching the conductive film. The channel length L of the transistor 430 is determined by the distance between the lower end portion of the source electrode layer 465a and the lower end portion of the drain electrode layer 465b over the oxide semiconductor layer 409. Note that in the case of performing exposure with a channel length L of less than 25 nm, it is preferable to perform exposure at the time of forming a resist mask using extreme ultraviolet (Extreme Ultraviolet) having a very short wavelength of several nm to several tens of nm. Exposure by extreme ultraviolet light has a high resolution and a large depth of focus. Therefore, the channel length L of a transistor to be formed later can be 10 nm to 1000 nm, and the operation speed of the circuit can be increased.

Note that the method for manufacturing the source electrode layer and the drain electrode layer is not limited to the above. For example, an insulating layer is formed over the gate insulating layer 402 and the oxide semiconductor layer 409 and reaches the oxide semiconductor layer 409 in the insulating layer. An opening may be formed, and the opening may be filled with a conductive film.

Through the above, the transistor 430 can be formed using the method for manufacturing a semiconductor device of one embodiment of the present invention.

In this embodiment, a protective insulating layer 407 (also referred to as an interlayer insulating layer or a planarization insulating layer) is formed over the source electrode layer 465a and the drain electrode layer 465b. The protective insulating layer 407 can be formed using a material and a method similar to those of the gate insulating layer 402. For example, a silicon oxynitride film or the like may be formed as the protective insulating layer 407. Note that when the protective insulating layer 407 includes an aluminum oxide film, release of oxygen from the oxide semiconductor layer 409 and entry of moisture or the like into the oxide semiconductor layer 409 can be prevented.

Further, after the formation of the protective insulating layer 407, oxygen introduction treatment may be performed on the oxide semiconductor layer 409 through the protective insulating layer 407. By performing the oxygen introduction treatment, oxygen vacancies in the oxide semiconductor layer 409 can be further reduced, and a change in electrical characteristics of the transistor can be prevented, so that a transistor with stable electrical characteristics can be provided. For the oxygen introduction treatment, a method similar to the first oxygen introduction treatment and the second oxygen introduction treatment can be used.

Further, a planarization insulating layer or an insulating layer serving as an interlayer insulating layer may be formed over the protective insulating layer. As the planarization insulating layer, an organic material such as polyimide, acrylic, or benzocyclobutene resin can be used. Note that the planarization insulating layer may be formed by stacking a plurality of insulating layers formed using these materials. For example, an acrylic resin film with a thickness of 1500 nm may be formed as the planarization insulating layer.

7A and 7B are a top view and a cross-sectional view of the transistor 430 described in this embodiment. 7A is a top view of the transistor 430, FIG. 7B is a cross-sectional view taken along one-dot chain line EF in FIG. 7A, and FIG. 7C is FIG. Sectional drawing in the dashed-dotted line GH is shown.

The transistor 430 is subjected to a first oxygen introduction treatment after the oxide semiconductor film is formed and a second oxygen introduction treatment after being processed into the island-shaped oxide semiconductor layer 409, so that sufficient oxygen is added to the surface. The oxide semiconductor layer 409 is formed. Therefore, oxygen deficiency occurs in a region where the protective insulating layer 407 is in contact with the side end portion of the oxide semiconductor layer 409 which overlaps with the gate electrode layer 401 (eg, a region surrounded by a dotted line in FIG. 7C). It is difficult to prevent the side end portion from being lowered in resistance. Therefore, a transistor with stable electrical characteristics using an oxide semiconductor can be provided.

This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 3)
In this embodiment, an example of a semiconductor device using the transistor described in this specification, capable of holding stored data even when power is not supplied, and having no limit on the number of writing times will be described with reference to drawings. To do. Note that the semiconductor device of this embodiment is configured using the transistor described in Embodiments 1 and 2 as the transistor 162. As the transistor 162, any of the structures of the transistors described in Embodiments 1 and 2 can be used.

FIG. 8 illustrates an example of a structure of a semiconductor device. 8A is a cross-sectional view of the semiconductor device, FIG. 8B is a top view of the semiconductor device, and FIG. 8C is a circuit diagram of the semiconductor device. Here, FIG. 8A corresponds to a cross section along dashed-dotted lines A1-A2 and B1-B2 in FIG. Note that in FIG. 8B, some components of the semiconductor device illustrated in FIG. 8A are omitted for clarity.

The semiconductor device illustrated in FIGS. 8A and 8B includes a transistor 160 using a first semiconductor material in a lower portion and a transistor 162 using a second semiconductor material in an upper portion. . The transistor 162 can have the same structure as that described in Embodiments 1 and 2.

Here, it is desirable that the first semiconductor material and the second semiconductor material have different band gaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (such as silicon), and the second semiconductor material can be an oxide semiconductor. A transistor including a material other than an oxide semiconductor can easily operate at high speed. On the other hand, a transistor including an oxide semiconductor can hold charge for a long time due to its characteristics.

Note that although all the above transistors are described as n-channel transistors, it goes without saying that p-channel transistors can be used. Further, the technical essence of the disclosed invention is that an oxide semiconductor is used for the transistor 162 in order to retain information; therefore, specific materials of the semiconductor device such as a material used for the semiconductor device and a structure of the semiconductor device are included. The configuration need not be limited to that shown here.

A transistor 160 in FIG. 8A is provided over the channel formation region 116, the channel formation region 116 provided in the substrate 100, the semiconductor layer including the impurity element region 120 provided so as to sandwich the channel formation region 116. The gate insulating layer 108, the gate electrode layer 110 provided on the gate insulating layer 108, the insulating layer 130 on the impurity element region 120 and the gate electrode layer 110, and the opening provided in the insulating layer 130 are formed. The conductive layer 112a and the conductive layer 112b are in contact with the impurity element region 120.

An insulating layer 135 is provided over the insulating layer 130, and conductive layers 114a and 114b that are in contact with the conductive layers 112a and 112b are formed in openings provided in the insulating layer 135, respectively. Further, the insulating layer 140 is provided over the insulating layer 135, and the conductive layer 115 in contact with the conductive layer 114a is provided in the insulating layer 140. The conductive layer 115 is in contact with the drain electrode layer 147a of the transistor 162.

Note that in order to achieve high integration, it is preferable that the transistor 160 have no sidewall insulating layer as illustrated in FIG. On the other hand, in the case where importance is attached to the characteristics of the transistor 160, a sidewall insulating layer may be provided on the side surface of the gate electrode layer 110 to form the impurity element region 120 including regions having different impurity element degrees.

Planarization treatment is preferably performed on the top surface of the insulating layer 140. In this embodiment, the oxide semiconductor layer 144 is formed over the insulating layer 140 which is sufficiently planarized by polishing treatment (eg, CMP treatment) (preferably, the average surface roughness of the upper surface of the insulating layer 130 is 0.15 nm or less). Form.

A transistor 162 illustrated in FIG. 8A is a transistor in which an oxide semiconductor is used for a channel formation region. Here, the transistor 162 includes an oxide semiconductor layer 144, a source electrode layer 147b and a drain electrode layer 147a in contact with the oxide semiconductor layer 144, and a gate over the oxide semiconductor layer 144, the source electrode layer 147b, and the drain electrode layer 147a. An insulating layer 146 and a gate electrode layer 148b over the gate insulating layer 146 are included. The oxide semiconductor layer 144 included in the transistor 162 is preferably highly purified. With the use of a highly purified oxide semiconductor, the transistor 162 with extremely excellent off characteristics can be obtained.

The oxide semiconductor layer 144 included in the transistor 162 includes a first oxygen introduction treatment after the oxide semiconductor film is formed and a second oxygen after the oxide semiconductor film is etched into the island-shaped oxide semiconductor layer 144. By the introduction treatment, oxygen vacancies in the oxide semiconductor layer are reduced and the semiconductor layer is highly purified. Therefore, the transistor has extremely high off characteristics, stable electrical characteristics, and high reliability. Note that in FIG. 8, the transistor described in Embodiment 1 is applied to the transistor 162; however, the transistor described in Embodiment 2 may be applied.

Since the transistor 162 has low off-state current, stored data can be held for a long time by using the transistor 162. In other words, since it is possible to obtain a semiconductor memory device that does not require a refresh operation or has a very low frequency of the refresh operation, power consumption can be sufficiently reduced.

The gate electrode layer 110 and the drain electrode layer 147a are electrically connected through the conductive layer 112a, the conductive layer 114a, and the conductive layer 115, and the capacitor 164 is formed by the drain electrode layer 147a, the gate insulating layer 146, and the conductive layer 148a. It is configured. That is, the drain electrode layer 147 a functions as one electrode of the capacitor 164, and the conductive layer 148 a functions as the other electrode of the capacitor 164. Note that in the case where a capacitor is not necessary, the capacitor 164 can be omitted. Further, the capacitor 164 may be separately provided above the transistor 162.

An insulating layer 150 is provided over the transistor 162 and the capacitor 164. A wiring 157 for connecting the transistor 162 to another transistor is provided over the insulating layer 150. The wiring 157 is connected to the source electrode layer 147b through an electrode layer 153 provided in an opening provided in the insulating layer 150 and the gate insulating layer 146.

8A and 8B, the transistor 160 and the transistor 162 are provided so that at least part of them overlap with each other. The source region or the drain region of the transistor 160 and the oxide semiconductor layer 144 are provided. It is preferable that a part is provided so as to overlap. In addition, the transistor 162 and the capacitor 164 are provided so as to overlap with at least part of the transistor 160. By adopting such a planar layout, the occupation area of the semiconductor device can be reduced, and thus high integration can be achieved.

Next, an example of a circuit configuration corresponding to FIGS. 8A and 8B is illustrated in FIG.

In FIG. 8C, the first wiring (1st Line) and the source electrode layer of the transistor 160 are electrically connected to each other, and the second wiring (2nd Line) and the drain electrode layer of the transistor 160 are electrically connected to each other. Connected. In addition, the third wiring (3rd Line) and one of the source electrode layer and the drain electrode layer of the transistor 162 are electrically connected, and the fourth wiring (4th Line) and the gate electrode layer of the transistor 162 are connected. Are electrically connected. One of a gate electrode layer of the transistor 160 and a source electrode layer or a drain electrode layer of the transistor 162 is electrically connected to the other electrode of the capacitor 164, and a fifth wiring (5th Line) and a capacitor The other of the 164 electrodes is electrically connected.

In the semiconductor device illustrated in FIG. 8C, information can be written, held, and read as follows by utilizing the feature that the potential of the gate electrode layer of the transistor 160 can be held.

Information writing and holding will be described. First, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned on, so that the transistor 162 is turned on. Accordingly, the potential of the third wiring is supplied to the gate electrode layer of the transistor 160 and the capacitor 164. That is, predetermined charge is supplied to the gate electrode layer of the transistor 160 (writing). Here, it is assumed that one of two charges (hereinafter, referred to as low level charge and high level charge) that gives two different potential levels is given. After that, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off and the transistor 162 is turned off, whereby the charge given to the gate electrode layer of the transistor 160 is held (held).

Since the off-state current of the transistor 162 is extremely small, the charge of the gate electrode layer of the transistor 160 is held for a long time.

Next, reading of information will be described. When an appropriate potential (reading potential) is applied to the fifth wiring in a state where a predetermined potential (constant potential) is applied to the first wiring, according to the amount of charge held in the gate electrode layer of the transistor 160, The second wiring takes different potentials. In general, when the transistor 160 is an n-channel transistor, the apparent threshold value V _{th_H in the} case where a high-level charge is applied to the gate electrode layer of the transistor 160 is a low-level charge applied to the gate electrode layer of the transistor 160. This is because it becomes lower than the apparent threshold value V _{th_L in the} case of Here, the apparent threshold voltage refers to the potential of the fifth wiring necessary for turning on the transistor 160. Therefore, the charge given to the gate electrode layer of the transistor 160 can be determined by _setting the potential of the fifth wiring to a potential V _{0 that} is intermediate between V _{th_H} and V _{th_L} . For example, in the case where a high-level charge is applied in writing, the transistor 160 is turned on when the potential of the fifth wiring is V ₀ (> V _{th_H} ). When the low-level charge is _supplied , the transistor 160 remains in the “off state” even when the potential of the fifth wiring is V ₀ (<V _{th_L} ). Therefore, the held information can be read by looking at the potential of the second wiring.

Note that in the case of using memory cells arranged in an array, it is necessary to read only information of a desired memory cell. In the case where information is not read out in this manner, a potential at which the transistor 160 is turned off regardless of the state of the gate electrode layer, that is, a potential lower than V _{th_H} may be _supplied to the fifth wiring. _{Alternatively} , a potential that turns on the transistor 160 regardless of the state of the gate electrode layer, that is, a potential higher than V _{th_L} may be _supplied to the fifth wiring.

In the semiconductor device described in this embodiment, stored data can be held for an extremely long time by using a transistor with an extremely small off-state current that uses an oxide semiconductor for a channel formation region. That is, the refresh operation is not necessary or the frequency of the refresh operation can be extremely low, so that power consumption can be sufficiently reduced. In addition, stored data can be held for a long time even when power is not supplied (note that a potential is preferably fixed).

In addition, in the semiconductor device described in this embodiment, high voltage is not needed for writing data and there is no problem of deterioration of elements. For example, unlike the conventional nonvolatile memory, it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, so that the problem of deterioration of the gate insulating layer does not occur at all. That is, in the semiconductor device according to the disclosed invention, the number of rewritable times that is a problem in the conventional nonvolatile memory is not limited, and the reliability is dramatically improved. Further, since data is written depending on the on / off state of the transistor, high-speed operation can be easily realized.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 4)
In this embodiment, a semiconductor device which uses the transistor described in Embodiments 1 and 2 and can hold stored data even when power is not supplied and has no limit on the number of writing operations. A structure different from the structure shown in Embodiment Mode 3 will be described with reference to FIGS. Note that the semiconductor device of this embodiment is configured using the transistor described in Embodiments 1 and 2 as the transistor 162. As the transistor 162, any of the structures of the transistors described in Embodiments 1 and 2 can be used.

FIG. 9A illustrates an example of a circuit configuration of a semiconductor device, and FIG. 9B is a conceptual diagram illustrating an example of a semiconductor device. First, the semiconductor device illustrated in FIG. 9A will be described, and then the semiconductor device illustrated in FIG. 9B will be described below.

In the semiconductor device illustrated in FIG. 9A, the bit line BL and the source electrode layer or the drain electrode layer of the transistor 162 are electrically connected, and the word line WL and the gate electrode layer of the transistor 162 are electrically connected. The source or drain electrode layer of the transistor 162 and the first terminal of the capacitor 254 are electrically connected.

The transistor 162 including an oxide semiconductor has a feature of extremely low off-state current. Therefore, when the transistor 162 is turned off, the potential of the first terminal of the capacitor 254 (or the charge accumulated in the capacitor 254) can be held for an extremely long time.

Next, the case where data is written and held in the semiconductor device (memory cell 250) illustrated in FIG. 9A is described.

First, the potential of the word line WL is set to a potential at which the transistor 162 is turned on, so that the transistor 162 is turned on. Accordingly, the potential of the bit line BL is supplied to the first terminal of the capacitor 254 (writing). After that, the potential of the first terminal of the capacitor 254 is held (held) by setting the potential of the word line WL to a potential at which the transistor 162 is turned off and the transistor 162 being turned off.

Since the off-state current of the transistor 162 is extremely small, the potential of the first terminal of the capacitor 254 (or charge accumulated in the capacitor) can be held for a long time.

Next, reading of information will be described. When the transistor 162 is turned on, the bit line BL in a floating state and the capacitor 254 are brought into conduction, and charge is redistributed between the bit line BL and the capacitor 254. As a result, the potential of the bit line BL changes. The amount of change in the potential of the bit line BL varies depending on the potential of the first terminal of the capacitor 254 (or the charge accumulated in the capacitor 254).

For example, the potential of the first terminal of the capacitor 254 is V, the capacitor of the capacitor 254 is C, the capacitor component of the bit line BL (hereinafter also referred to as bit line capacitor) is CB, and before the charge is redistributed. When the potential of the bit line BL is VB0, the potential of the bit line BL after the charge is redistributed is (CB × VB0 + C × V) / (CB + C). Therefore, when the potential of the first terminal of the capacitor 254 assumes two states of V1 and V0 (V1> V0) as the state of the memory cell 250, the potential of the bit line BL when the potential V1 is held. It can be seen that (= CB × VB0 + C × V1) / (CB + C) is higher than the potential of the bit line BL when the potential V0 is held (= CB × VB0 + C × V0) / (CB + C)).

Then, information can be read by comparing the potential of the bit line BL with a predetermined potential.

As described above, the semiconductor device illustrated in FIG. 9A can hold charge that is accumulated in the capacitor 254 for a long time because the off-state current of the transistor 162 is extremely small. That is, the refresh operation is not necessary or the frequency of the refresh operation can be extremely low, so that power consumption can be sufficiently reduced. Further, stored data can be retained for a long time even when power is not supplied.

Next, the semiconductor device illustrated in FIG. 9B is described.

The semiconductor device illustrated in FIG. 9B includes a memory cell array 251a and a memory cell array 251b each including a plurality of memory cells 250 illustrated in FIG. 9A as a memory circuit in an upper portion, and a memory cell array 251 (memory cell array) in a lower portion. 251a and the memory cell array 251b) have a peripheral circuit 253 necessary for operating. Note that the peripheral circuit 253 is electrically connected to the memory cell array 251.

With the structure illustrated in FIG. 9B, the peripheral circuit 253 can be provided immediately below the memory cell array 251 (the memory cell array 251a and the memory cell array 251b), so that the semiconductor device can be downsized.

The transistor provided in the peripheral circuit 253 is preferably formed using a semiconductor material different from that of the transistor 162. For example, silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or the like can be used, and a single crystal semiconductor is preferably used. In addition, an organic semiconductor material or the like may be used. A transistor using such a semiconductor material can operate at a sufficiently high speed. Therefore, various transistors (logic circuit, drive circuit, etc.) that require high-speed operation can be suitably realized by the transistor.

Note that in the semiconductor device illustrated in FIG. 9B, the structure in which the two memory cell arrays 251 (the memory cell array 251a and the memory cell array 251b) are stacked is illustrated; however, the number of stacked memory cells is not limited thereto. . A configuration in which three or more memory cells are stacked may be employed.

Next, a specific structure of a semiconductor device applicable to the memory cell 250 illustrated in FIG. 9 is described with reference to FIGS. 10B is a top view of the semiconductor device, and FIG. 10A is a cross-sectional view taken along dashed-dotted lines C1-C2 and D1-D2 in FIG. 10B. Note that in FIG. 10A, some components of the semiconductor device illustrated in FIG. 10B are omitted for clarity.

The memory cell illustrated in FIG. 10 includes a transistor 162 in which a channel is formed in an oxide semiconductor, and a capacitor 254. Note that the structure of the transistor 162 is similar to that of the transistor 162 included in the semiconductor device illustrated in FIG. 8, and thus detailed description thereof is omitted.

In FIG. 10, the capacitor 254 includes a drain electrode layer 147a, a gate insulating layer 146, and a conductive layer 158a. The conductive layer 148a is formed in the same process as the gate electrode layer 148b of the transistor 162.

The electrode layer 153 electrically connected to the source electrode layer 147b illustrated in FIG. 10, the wiring 157, and the layer electrically connected to these function as the bit line BL illustrated in FIG. In addition, the gate electrode layer 148b illustrated in FIG. 10 and the layer electrically connected to the gate electrode layer 148b function as the word line WL illustrated in FIG.

Since the transistor 162 has low off-state current, stored data can be held for a long time by using the transistor 162. In other words, since it is possible to obtain a semiconductor memory device that does not require a refresh operation or has a very low frequency of the refresh operation, power consumption can be sufficiently reduced.

The oxide semiconductor layer 144 included in the transistor 162 includes a first oxygen introduction treatment after the oxide semiconductor film is formed and a second oxygen after the oxide semiconductor film is formed in the island-shaped oxide semiconductor layer 144. By the introduction treatment, oxygen vacancies in the oxide semiconductor layer are reduced; thus, the transistor has stable electric characteristics and high reliability.

As shown in FIG. 9, since the memory cell array 251 including the transistor 162 and the capacitor 254 are densely stacked so as to overlap with each other, the occupied area of the semiconductor device can be further reduced, so that high integration is achieved. Can be achieved.

As described above, the plurality of memory cells formed in multiple layers in the upper portion are formed using transistors including an oxide semiconductor. Since a transistor including a highly purified and intrinsic oxide semiconductor has a small off-state current, stored data can be retained for a long time by using the transistor. That is, the frequency of the refresh operation can be made extremely low, so that power consumption can be sufficiently reduced.

As described above, a peripheral circuit using a transistor using a material other than an oxide semiconductor (in other words, a transistor capable of sufficiently high-speed operation) and a transistor using an oxide semiconductor (in a broader sense, sufficiently off) By integrally including a memory circuit using a transistor having a small current, a semiconductor device having characteristics that have never been achieved can be realized. Further, the peripheral circuit and the memory circuit have a stacked structure, whereby the semiconductor device can be integrated.

The above transistor has high on-characteristics, and can operate at high speed and respond at high speed. Also, miniaturization can be achieved. Therefore, a high-performance and highly reliable semiconductor device can be provided by using the transistor.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 5)
The semiconductor device disclosed in this specification can be applied to a variety of electronic devices. Electronic devices include television devices (also referred to as televisions or television receivers), monitors for computers, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, audio Examples include a playback device, a gaming machine (such as a pachinko machine or a slot machine), and a game housing.

FIG. 11 shows a specific example of an electronic device. 11A and 11B illustrate a tablet terminal that can be folded. FIG. 11A illustrates an open state in which the tablet terminal includes a housing 9630, a display portion 9631a, a display portion 9631b, a display mode switching switch 9034, a power switch 9035, a power saving mode switching switch 9036, and a fastener 9033. And an operation switch 9038.

The semiconductor device described in Embodiment 1 or 2 can be used for the display portion 9631a and the display portion 9631b, so that a highly reliable tablet terminal can be provided. Further, the memory device described in Embodiment 3 or 4 may be applied to the semiconductor device in this embodiment.

Part of the display portion 9631 a can be a touch panel region 9632 a and data can be input when a displayed operation key 9638 is touched. Note that in the display portion 9631a, a structure in which half of the regions have a display-only function and a structure in which the other half has a touch panel function is shown as an example; however, the structure is not limited thereto. The entire surface of the display portion 9631a can display keyboard buttons to serve as a touch panel, and the display portion 9631b can be used as a display screen.

Further, in the display portion 9631b, as in the display portion 9631a, part of the display portion 9631b can be a touch panel region 9632b. Further, a keyboard button can be displayed on the display portion 9631b by touching a position where the keyboard display switching button 9539 on the touch panel is displayed with a finger or a stylus.

Touch input can be performed simultaneously on the touch panel region 9632a and the touch panel region 9632b.

A display mode switching switch 9034 can switch the display direction such as vertical display or horizontal display, and can select switching between monochrome display and color display. The power saving mode change-over switch 9036 can optimize the display luminance in accordance with the amount of external light during use detected by an optical sensor built in the tablet terminal. The tablet terminal may include not only an optical sensor but also other detection devices such as a gyroscope, an acceleration sensor, and other sensors that detect inclination.

FIG. 11A illustrates an example in which the display areas of the display portion 9631b and the display portion 9631a are the same, but there is no particular limitation, and one size may differ from the other size, and the display quality may also be high. May be different. For example, one display panel may be capable of displaying images with higher definition than the other.

FIG. 11B illustrates a closed state, in which the tablet terminal includes a housing 9630, a solar battery 9633, a charge / discharge control circuit 9634, a battery 9635, and a DCDC converter 9636. Note that FIG. 11B illustrates a structure including a battery 9635 and a DCDC converter 9636 as an example of the charge / discharge control circuit 9634.

Note that since the tablet terminal can be folded in two, the housing 9630 can be closed when not in use. Accordingly, since the display portion 9631a and the display portion 9631b can be protected, a tablet terminal with excellent durability and high reliability can be provided from the viewpoint of long-term use.

In addition, the tablet type terminal shown in FIGS. 11A and 11B has a function for displaying various information (still images, moving images, text images, etc.), a calendar, a date or a time. A function to display on the display unit, a touch input function to touch or edit information displayed on the display unit, a function to control processing by various software (programs), and the like can be provided.

Electric power can be supplied to the touch panel, the display unit, the video signal processing unit, or the like by the solar battery 9633 mounted on the surface of the tablet terminal. Note that the solar cell 9633 is preferable because it can efficiently charge the battery 9635 on one or two surfaces of the housing 9630. Note that as the battery 9635, when a lithium ion battery is used, there is an advantage that reduction in size can be achieved.

Further, the structure and operation of the charge / discharge control circuit 9634 illustrated in FIG. 11B are described with reference to a block diagram in FIG. FIG. 11C illustrates the solar battery 9633, the battery 9635, the DCDC converter 9636, the converter 9637, the switches SW1 to SW3, and the display portion 9631. The battery 9635, the DCDC converter 9636, the converter 9637, and the switches SW1 to SW3 are illustrated. This corresponds to the charge / discharge control circuit 9634 shown in FIG.

First, an example of operation in the case where power is generated by the solar battery 9633 using external light is described. The power generated by the solar battery is boosted or lowered by the DCDC converter 9636 so as to be a voltage for charging the battery 9635. When power from the solar cell 9633 is used for the operation of the display portion 9631, the switch SW1 is turned on, and the converter 9637 increases or decreases the voltage required for the display portion 9631. In the case where display on the display portion 9631 is not performed, the battery 9635 may be charged by turning off SW1 and turning on SW2.

Note that the solar cell 9633 is described as an example of the power generation unit, but is not particularly limited, and the battery 9635 is charged by another power generation unit such as a piezoelectric element (piezo element) or a thermoelectric conversion element (Peltier element). There may be. For example, it is good also as a structure performed combining a non-contact electric power transmission module which transmits / receives electric power by radio | wireless (non-contact), and another charging means.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

100 substrate 108 gate insulating layer 110 gate electrode layer 112a conductive layer 112b conductive layer 114a conductive layer 114b conductive layer 115 conductive layer 116 channel formation region 120 impurity element region 130 insulating layer 135 insulating layer 140 insulating layer 144 oxide semiconductor layer 146 gate insulating Layer 147a drain electrode layer 147b source electrode layer 148a conductive layer 148b gate electrode layer 150 insulating layer 153 electrode layer 157 wiring 158a conductive layer 160 transistor 162 transistor 164 capacitor 250 memory cell 251 memory cell array 251a memory cell array 251b memory cell array 253 peripheral circuit 254 Capacitor 400 Substrate 401 Gate electrode layer 402 Gate insulating layer 403 Oxide semiconductor film 407 Insulating layer 409 Oxide semiconductor layer 420 Transistor 430 Transistor 436 Resist mask 450 Oxygen 465a Source electrode layer 465b Drain electrode layer 9033 Fastener 9034 Switch 9035 Power switch 9036 Switch 9038 Operation switch 9630 Housing 9631 Display portion 9631a Display portion 9631b Display portion 9632a Region 9632b Region 9633 Solar cell 9634 Charge / discharge control Circuit 9635 Battery 9636 DCDC converter 9537 Converter 9638 Operation key 9539 Button

Claims (6)

Forming an oxide semiconductor film,
Performing a first oxygen introduction treatment on the oxide semiconductor film;
An island-shaped oxide semiconductor layer is formed by etching the oxide semiconductor film,
A method for manufacturing a semiconductor device, in which a second oxygen introduction treatment is performed on at least a side end portion of the oxide semiconductor layer. Forming an oxide semiconductor film,
Performing a first oxygen introduction treatment on the oxide semiconductor film;
An island-shaped oxide semiconductor layer is formed by etching the oxide semiconductor film,
Performing a second oxygen introduction treatment on at least a side end of the oxide semiconductor layer;
Forming a gate insulating layer on the oxide semiconductor layer;
Forming a gate electrode layer on the gate insulating layer;
In a method for manufacturing a semiconductor device in which a source electrode layer and a drain electrode layer that are electrically connected to the oxide semiconductor layer are formed,
The semiconductor device manufacturing method, wherein the first oxygen introduction treatment and the second oxygen introduction treatment are performed by an ion implantation method. Forming a gate electrode layer;
Forming a gate insulating layer on the gate electrode layer;
Forming an oxide semiconductor film over the gate insulating layer;
A first oxygen introduction treatment is performed on the oxide semiconductor film to form an island-shaped oxide semiconductor layer by etching the oxide semiconductor film,
Performing a second oxygen introduction treatment on at least a side end of the oxide semiconductor layer;
In a method for manufacturing a semiconductor device in which a source electrode layer and a drain electrode layer that are electrically connected to the oxide semiconductor layer are formed,
The method for manufacturing a semiconductor device, wherein the first oxygen introduction treatment and the second oxygen introduction treatment are plasma treatments. In any one of Claims 1 thru | or 3,
After the first oxygen introduction treatment, the oxide semiconductor film is etched using a mask to form an island-shaped oxide semiconductor layer,
While leaving the mask, the oxide semiconductor layer is subjected to a second oxygen introduction treatment,
A method for manufacturing a semiconductor device, in which the mask is removed.   5. The method for manufacturing a semiconductor device according to claim 4, wherein the thickness of the mask is 1 μm or more and 2 μm or less.   6. The method for manufacturing a semiconductor device according to claim 4, wherein a region of the oxide semiconductor layer overlapping with the mask includes a crystal having a c-axis substantially perpendicular to a surface.