JP5721674B2 - トレンチポリシリコンダイオード - Google Patents
トレンチポリシリコンダイオード Download PDFInfo
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- JP5721674B2 JP5721674B2 JP2012194777A JP2012194777A JP5721674B2 JP 5721674 B2 JP5721674 B2 JP 5721674B2 JP 2012194777 A JP2012194777 A JP 2012194777A JP 2012194777 A JP2012194777 A JP 2012194777A JP 5721674 B2 JP5721674 B2 JP 5721674B2
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims description 171
- 229920005591 polysilicon Polymers 0.000 title claims description 171
- 239000007943 implant Substances 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 13
- 238000001514 detection method Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims 1
- 238000000034 method Methods 0.000 description 41
- 230000015556 catabolic process Effects 0.000 description 22
- 238000004519 manufacturing process Methods 0.000 description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 238000002955 isolation Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 210000000746 body region Anatomy 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- JCALBVZBIRXHMQ-UHFFFAOYSA-N [[hydroxy-(phosphonoamino)phosphoryl]amino]phosphonic acid Chemical group OP(O)(=O)NP(O)(=O)NP(O)(O)=O JCALBVZBIRXHMQ-UHFFFAOYSA-N 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/866—Zener diodes
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0814—Diodes only
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/6609—Diodes
- H01L29/66098—Breakdown diodes
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
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- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Description
[付記]
概念1:
縦型トレンチポリシリコンダイオードを製造する方法であって、
N+(P+)型基板上にN−(P−)型エピタキシャル領域を形成すること;
前記エピタキシャル領域内にトレンチを形成すること;
前記トレンチ内に絶縁層を形成すること;
前記トレンチをポリシリコンで充填して、前記トレンチの上面を形成すること;
P+(N+)型ドーパントをインプラントして、前記トレンチ内に前記ポリシリコンのP+(N+)型領域を形成すること;
N+(P+)型ドーパントをインプラントして、前記トレンチ内に前記ポリシリコンのN+(P+)型領域を形成すること;
前記トレンチ内にポリシリコンダイオードを形成することであって、前記ダイオードの一部は、前記トレンチの前記上面より低い、
を備えた、方法。
概念2:
前記絶縁層は酸化物を含む、概念1に記載の方法。
概念3:
前記トレンチ内の前記絶縁層は、それらの間の良好な絶縁のために、トレンチMOSFETトランジスタのドレイン−ソース間ブレークダウン電圧より大きなブレークダウン電圧定格を有する、概念1〜2のいずれか1項に記載の方法。
概念4:
前記絶縁層は、厚みが数千Åであり、前記トレンチ内の前記絶縁層の厚みは、ブレークダウン電圧要件によって決まる、概念1〜2のいずれか1項に記載の方法。
概念5:
前記ダイオードの形成は、前記トランジスタのMOSFETトレンチの形成より前である、概念1〜4のいずれか1項に記載の方法。
概念6:
前記ダイオードは、ツェナーダイオードある、概念1〜5のいずれか1項に記載の方法。
概念7:
前記ツェナーダイオードは、静電放電保護に使用される、概念6に記載の方法。
概念8:
前記ツェナーダイオードは、クランピング機能に使用される、概念6に記載の方法。
概念9:
前記ダイオードは、トレンチダイオードであり温度検出に使用される、概念1〜5のいずれか1項に記載の方法。
概念10:
前記トレンチ内の前記N+(P+)型ドープドポリシリコンは、抵抗器として使用される、概念1〜9のいずれか1項に記載の方法。
概念11:
静電放電保護を備えたトレンチポリシリコンダイオードであって、
N+(P+)型基板と;
前記基板上のN−(P−)型エピタキシャル領域と;
前記N−(P−)型エピタキシャル領域内に形成され、上面を備えたトレンチと;
前記トレンチの内側を覆う絶縁層と;
前記トレンチを充填して、前記トレンチの上面を形成するポリシリコンと;
P+(N+)型ESDインプラントによって形成された前記トレンチ内のP+(N+)型ドーピングポリシリコンと;
N+(P+)型ソースインプラントによって形成された前記トレンチ内のN+(P+)型ドーピングポリシリコンと;
ダイオードの一部が前記トレンチの前記上面より下方に形成されるように、前記トレンチ内に形成されたダイオードと、
を含む、トレンチポリシリコンダイオード。
概念12:
前記絶縁層は酸化物を含む、概念11に記載のトレンチポリシリコンダイオード。
概念13:
前記トレンチ内の前記絶縁層は、それらの間の良好な絶縁のために、トレンチMOSFETトランジスタのドレイン−ソース間ブレークダウン電圧より大きなブレークダウン電圧定格を有する、概念11〜12のいずれか1項に記載のトレンチポリシリコンダイオード。
概念14:
前記絶縁層は、厚みが数千Åであり、前記トレンチ内の前記絶縁層の厚みは、ブレークダウン電圧要件によって決まる、概念11〜12のいずれか1項に記載のトレンチポリシリコンダイオード。
概念15:
前記ダイオードは、前記トランジスタのMOSFETトレンチの形成より前に形成されている、概念11〜14のいずれか1項に記載のトレンチポリシリコンダイオード。
概念16:
前記ダイオードは、ツェナーダイオードある、概念11〜15のいずれか1項に記載のトレンチポリシリコンダイオード。
概念17:
前記ツェナーダイオードは、静電放電保護に使用される、概念16に記載のトレンチポリシリコンダイオード。
概念18:
前記ツェナーダイオードは、クランピング機能に使用される、概念16に記載のトレンチポリシリコンダイオード。
概念19:
前記ダイオードは、トレンチダイオードであり、温度検出に使用される、概念11〜15のいずれか1項に記載のトレンチポリシリコンダイオード。
概念20:
前記トレンチ内の前記N+(P+)型ドープドポリシリコンは、抵抗器として使用される、概念11〜19のいずれか1項に記載のトレンチポリシリコンダイオード。
概念21:
トレンチポリシリコンダイオードを製造する方法であって、
N+(P+)型基板上のN−(P−)型エピタキシャル領域内にトレンチを形成すること;
前記トレンチ内に絶縁層を形成することであって、前記絶縁層は、前記トレンチの内側を覆い;
前記トレンチ内をポリシリコンで充填し、前記トレンチの上面を形成すること;
前記ボディ領域内にダイオードを形成することであって、前記ダイオードの一部は、前記トレンチの前記上面より低い、
を備えた、方法。
概念22:
概念21に記載の方法であって、
前記N−(P−)型エピタキシャル領域内に複数のツェナーダイオードを形成し、前記複数のツェナーダイオードを並列に接続して、前記トランジスタを静電放電から保護するステップをさらに含む、方法。
概念23:
前記絶縁層は酸化物を含む、概念21〜22のいずれか1項に記載の方法。
概念24:
前記トレンチ内の前記絶縁層は、それらの間の良好な絶縁のために、トレンチMOSFETトランジスタのドレイン−ソース間ブレークダウン電圧より大きなブレークダウン電圧定格を有する、概念21〜23のいずれか1項に記載の方法。
概念25:
前記絶縁層は、厚みが数千Åであり、前記トレンチ内の絶縁層の厚みは、ブレークダウン電圧要件によって決まる、概念21〜23のいずれか1項に記載の方法。
概念26:
前記ダイオードの形成は、前記トランジスタのMOSFETトレンチの形成より前に行う、概念21〜25のいずれか1項に記載の方法。
概念27:
前記ダイオードはツェナーダイオードある、概念21に記載の方法。
概念28:
前記ツェナーダイオードは静電放電保護に使用される、概念27に記載の方法。
概念29:
前記ツェナーダイオードはクランピング機能に使用される、概念27に記載の方法。
概念30:
前記ダイオードはトレンチダイオードであり温度検出に使用される、概念21〜26のいずれか1項に記載の方法。
概念31:
前記トレンチ内の前記N+(P+)型ドープドポリシリコンは、抵抗器として使用される、概念21〜30のいずれか1項に記載の方法。
概念32:
第1のピンおよび第2のピンに電気的に接続された第1のトレンチポリシリコンダイオードと、
前記第1のピンおよび前記第2のピンに接続された第2のトレンチポリシリコンダイオードと、
を含む温度センサであって、
前記第1のトレンチポリシリコンダイオードの一部は、N−(P−)型エピタキシャル領域の表面の下にあり、
前記第1のトレンチポリシリコンダイオード及び前記第2のトレンチポリシリコンダイオードはアンチパラレルに接続されており、前記第1のピンと前記第2のピンの間で測定された電圧によって温度を決定することができ、前記第2のトレンチポリシリコンダイオードの一部が、前記N−(P−)型エピタキシャル領域の表面の下にある、
温度センサ。
概念33:
前記第1のトレンチダイオードおよび第2のトレンチダイオードは、トレンチポリシリコンダイオードである、概念32に記載の温度センサ。
概念34:
複数の電圧と対応する温度値を含むルックアップテーブルをさらに含む、概念32、33のいずれか1項に記載の温度センサ。
概念35:
前記第1のダイオードおよび第2のダイオードは、P+型ポリシリコン領域およびN+型ポリシリコン領域を含む、概念32〜34のいずれか1項に記載の温度センサ。
Claims (13)
- 第1の型の導電率を有する基板と、
前記基板上に配置されており、前記第1の型の導電率を有するエピタキシャル層と、
前記エピタキシャル層に形成した縦型ポリシリコントレンチダイオードと、
前記縦型ポリシリコントレンチダイオードと前記エピタキシャル層の材料との間に配置された絶縁層と、を備え、
前記縦型ポリシリコントレンチダイオードは、当該トレンチの上面を形成するようにポリシリコンが充填されたトレンチを有しており、
前記縦型ポリシリコントレンチダイオードの第1部分は、前記第1の型の導電率と反対の第2の型の導電率の領域を含んでおり、
前記縦型ポリシリコントレンチダイオードの第2部分は、前記トレンチの上面よりも低い高さの前記第1の型の導電率の領域を含んでいる、
集積回路。 - 前記トレンチの上面は、前記エピタキシャル層の上部と同じ高さにある、請求項1に記載の集積回路。
- 前記絶縁層は、厚みが数千オングストロームである、請求項2に記載の集積回路。
- 前記ポリシリコントレンチダイオードは、ツェナーダイオードある、請求項1に記載の集積回路。
- 前記ツェナーダイオードは、温度検出を行うように構成される、請求項4に記載の集積回路。
- 前記ポリシリコントレンチダイオードとアンチパラレルに接続された第2のダイオードを備えている、請求項1に記載の集積回路。
- 前記第2のダイオードは、ポリシリコントレンチダイオードである、請求項6に記載の集積回路。
- N+(P+)型基板と、
前記基板上のN−(P−)型エピタキシャル領域と、
前記N−(P−)型エピタキシャル領域内に形成されており、上面を有している第1及び第2のトレンチと、
前記第1及び第2のトレンチの内側を覆う絶縁層と、
前記第1及び第2のトレンチを充填して、前記トレンチの前記上面を形成するポリシリコンと、
P+(N+)型インプラントによって形成され、前記第1及び第2のトレンチ内に第1ダイオード部分を形成するP+(N+)型ポリシリコン領域と、
N+(P+)型ソースインプラントによって形成され、前記第1及び第2のトレンチ内に第2ダイオード部分を形成するN+(P+)型ポリシリコン領域と、
を備え、
第1の縦型ポリシリコントレンチダイオードが、前記第1のトレンチ内に形成され、第2の縦型ポリシリコントレンチダイオードが、前記第2のトレンチ内に形成され、前記第1及び第2の縦型ポリシリコントレンチダイオードのPN接合が前記トレンチの前記上面より下方に形成されている、
温度検出装置。 - 前記第1のダイオードと前記第2のダイオードはアンチパラレルに接続されている、請求項8に記載の温度検出装置。
- 前記第1のダイオードに亘って測定された電圧に対応する温度を決定するように構成されている、請求項9に記載の温度検出装置。
- 前記測定された電圧を前記温度に変換するルックアップテーブルを備えている、請求項10に記載の温度検出装置。
- 前記トレンチの上面は、前記エピタキシャル層の上部と同じ高さにある、請求項8に記載の温度検出装置。
- 前記第1のダイオード、前記第2のダイオードの少なくとも1つはツェナーダイオードである、請求項8に記載の温度検出装置。
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US7612431B2 (en) | 2009-11-03 |
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US20070145411A1 (en) | 2007-06-28 |
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US8072013B1 (en) | 2011-12-06 |
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US9431550B2 (en) | 2016-08-30 |
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