CN114447114A - 功率半导体元件及其制造方法 - Google Patents

功率半导体元件及其制造方法 Download PDF

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CN114447114A
CN114447114A CN202011190506.5A CN202011190506A CN114447114A CN 114447114 A CN114447114 A CN 114447114A CN 202011190506 A CN202011190506 A CN 202011190506A CN 114447114 A CN114447114 A CN 114447114A
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epitaxial layer
terminal
region
terminal electrode
trench
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张立鸣
陈美玲
李序恒
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Chuangyi Semiconductor Co ltd
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Chuangyi Semiconductor Co ltd
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Abstract

本公开涉及一种功率半导体元件及其制造方法，该功率半导体元件包括：第一电性外延层、第二电性第一掺杂区、第一电性第二掺杂区、元件电极、第一终端电极和第二终端电极，外延层包括主动区和终端区。第一掺杂区位于主动区中；第二掺杂区位于第一掺杂区中。接触金属层位于外延层上，与第二掺杂区电性接触。元件电极位主动区中的元件沟槽中，并与外延层和接触金属层电性隔离。第一终端电极位于终端区中的第一终端沟槽中，并与外延层电性隔离。第二终端电极位于第一终端沟槽的底部，并与第一终端电极和外延层电性隔离。第一终端电极和第二终端电极均可选择浮接。

Description

功率半导体元件及其制造方法
技术领域
本申请涉及一种功率电子元件及其制造方法，特别涉及一种功率半导体元件及其制造方法。
背景技术
功率半导体元件一般用于开关模式电源或其他高速电源开关的装置中。通常功率半导体元件的需求除了是在主动区能通过大电流之外，还要具备能在终端区(terminationregion)承受较大的崩溃电压。目前已经有几种功率半导体元件(例如，萧特基阻障二极管、金属氧化物半导体场效应晶体管或金属氧化物半导体萧特基二极管)被广泛使用。然而，一般平板式的萧特基阻障二极管因为有崩溃电压不高的问题，所以近来发展出沟槽式金属氧化物半导体萧特基阻障二极管(Trench MOS Barrier Schottky diode，TMBS diode)。
典型的功率半导体元件，以沟槽式金属氧化物半导体萧特基阻障二极管为例，主要是在N+基材上先形成N-外延层，再于N-外延层中形成多个沟槽式栅极，且于沟槽式栅极和N-外延层之间设置栅极氧化层。然后在N-外延层表面与沟槽式栅极表面沉积萧特基阻障金属层与阳极金属。
然而，随着功率半导体元件密度的提升，栅极-漏极间电荷(Qgd)会变大，使栅极的充放电速度变慢而影响元件的效能。为了降低栅极-漏极间电荷以改善元件切换损耗，必须降低元件电容值，例如使用分离栅极架构以减少栅漏极面积，然而这将导致元件的电荷平衡更加复杂。
因此，有需要提供一种先进的功率半导体元件及其制造方法，来解决现有技术所面临的问题。
发明内容
本说明书的一实施例，是公开一种功率半导体元件，此功率半导体元件包括：外延层、第一掺杂区、第二掺杂区、接触金属层、栅电极、第一终端电极以及第二终端电极。外延层具有第一电性，并包括一个主动区和一个终端区。第一掺杂区具有第二电性，位于主动区的外延层中；第二掺杂区具有第一电性，位于第一掺杂区之中。接触金属层位于外延层上，与第二掺杂区电性接触。栅电极位于主动区中的元件沟槽之中，并与外延层和接触金属层电性隔离。第一终端电极位于终端区中的第一终端沟槽之中，并与外延层电性隔离。第二终端电极位于第一终端沟槽的底部，并与第一终端电极和外延层电性隔离。其中，第一终端电极和第二终端电极均可选择浮接或与接触金属层电性接触。
本说明书的另一实施例，是公开一种功率半导体元件的制作方法，此功率半导体元件的制作方法包括下述步骤：首先提供一个具有第一电性的外延层，使其包括一个主动区和一个终端区。于主动区的外延层中形成具有第二电性的第一掺杂区。于第一掺杂区形成具有第一电性的第二掺杂区。于外延层上形成接触金属层，使其与第二掺杂区电性接触。于主动区中形成一个栅电极，使其位于延伸进入外延层的元件沟槽之中，并与外延层和接触金属层电性隔离。于终端区中形成第一终端电极，使其位于延伸进入外延层的第一终端沟槽之中，并与外延层电性隔离。于第一终端沟槽的底部形成第二终端电极，使其与第一终端电极和外延层电性隔离，并使第一终端电极和第二终端电极均可选择浮接(floating)或与接触金属层电性接触。
根据上述实施例，本说明书是提供一种功率半导体元件及其制造方法，是在一个具有沟槽式结构的功率半导体元件的终端区中配置至少一个沟槽，并于沟槽中配置至少两个上下堆叠且彼此隔离的终端电极场板，使二者同时与源极电性连接，或者同时浮接；抑或使其中一者与源极电性连接，另一者浮接。前述的具有沟槽式结构的功率元件，可以例如是(但不限定为)金属氧化物半导体场效应晶体管、金属氧化物半导体萧特基二极管、萧特基阻障二极管或其他合适的功率半导体元件。且沟槽的数目及终端电极场板连接方式的选择，可以根据功率半导体元件操作时的电场需求预先设计，可通过此增进功率金属氧化物-半导体晶体管单元的电荷平衡。
前述发明内容仅是本说明书各个面向的一般概述，同时介绍公开内容的一些相关的概念，而这些概念将在下述的实施方式中进一步详细说明。前述发明内容并非用以限定所请发明的关键或必要特征，也非单独地用以限定本说明书所请的发明范围。本说明书所请的发明范围，是由以下所述的权利要求为准。通过参考下述说明书的整体公开内容、说明书附图以及每一个权利要求，可以对本发明上述及其他各方面的技术内容有更佳的了解。
附图说明
为让本发明的上述特征和优点能更明显易懂，下文特举实施例作详细说明如下。但必须注意的是，这些特定的实施案例与实施方式，并非用以限定本发明。本发明仍可采用其他特征、元件、方法及参数来加以实施。优选实施例的提出，仅是用以例示本发明的技术特征，并非用以限定本发明的权利要求。
图1A至图1G是根据本说明书的一实施例所示出，制作功率半导体元件的一系列制程结构剖面示意图；
图2A是根据本说明书的一实施例所示出的功率半导体元件的部分布线结构上视图；
图2B是沿着图2A的切线S1所示出的功率半导体元件部分结构剖面图；
图2C是沿着图2A的切线S2所示出的功率半导体元件部分结构剖面图；
图2D是根据本说明书的另一实施例所示出的功率半导体元件部分结构剖面图；
图3是根据本说明书的另一实施例所示出的功率半导体元件部分结构剖面图；以及
图4是根据本说明书的又一实施例所示出的功率半导体元件部分结构剖面图。
具体实施方式
本说明书是提供一种功率半导体元件及其制作方法，可调整功率半导体元件终端区的电场分布，以改善功率半导体元件操作时的电荷平衡。以下将提出多个实施例，并参考后附附图来进行说明。在附图中，相似的元件符号用来表示相似或均等的元件。且附图仅是为了例示，其并未按照比例示出。以下实施方式仅针对本发明的有限的范围和实施方式进行例示说明。
应当理解的是，其所阐述的具体细节、连结关系和制作方法，仅是用以增进理解。相关领域中技术人员当能轻易在忽略一个或多个特定具体细节或元件，或通过其他方法来实施本发明。而为了避免让使本说明书晦涩难懂，已现有的结构或操作方法不再此赘述。不同的实施例的步骤或构件的顺序，不受例示内容的限制。因此在一些实施例中，步骤的进行或构件的组装顺序，可以与例示的实施例相同或不同。此外，并非所有例示的步骤或构件都是实施本发明所必需的。
请参照图1A至图1G，图1A至图1G是根据本说明书的一实施例所示出，制作功率半导体元件100的一系列制程结构剖面示意图。制作功率半导体元件100的方法包括下述步骤：首先，在半导体基材101上提供一个具有第一电性的外延层102。在本说明书的一些实施例之中，半导体基材101可以包含一个具有n型掺质(例如，砷、磷、锑等五价原子)的半导体基底层。在本说明书的一些实施例中，构成半导体基底层的材料可以是例如单晶硅(monocrystalline silicon)、多晶硅(poly-silicon)或碳化硅(silicon carbide，SiC)。在本实施例中，半导体基材101可以是一个包含单晶硅层的晶圆。
在本说明书的一些实施例之中，外延层102的形成，可以包括以外延沉积制程，例如物理气相沉积(Physical Vapor Deposition，PVD)技术或化学气相沉积(ChemicalVapor Deposition，CVD)，在半导体基材101上成长具有n型掺质的半导体外延层102。其中，构成外延层102的材料与构成半导体外延层102的材料相同或相异；且半导体基材101中n型掺质的掺杂浓度，大于外延层102中n型掺质的掺杂浓度。
例如，在本实施例之中，可以采用分子束外延(Molecular beam epitaxy,MBE)技术(但不以此为限)，在具有n型掺质的单晶硅半导体基材101上，形成具有n型掺质的单晶硅外延层102。在本说明书的一些实施例中，外延层102可以区分为至少一个主动区102A以及一个位于主动区外侧的终端区102T(如图1A所示出)。
接着，对外延层102进行至少一次的光刻胶蚀刻制程，分别在外延层102的主动区102A中形成多个元件沟槽(例如，元件沟槽103a和103b)，并且在外延层102的终端区102T中形成多个终端沟槽(例如，元件沟槽104a、104b、104c和104d)。在本说明书的一些实施例之中，元件沟槽103a和103b和终端沟槽104a、104b、104c和104d可以是通过不同的光刻胶蚀刻制程分别形成。
在本实施例之中，元件沟槽103a和103b和终端沟槽104a、104b、104c和104d则是通过同一个光刻胶蚀刻制程所同时形成。元件沟槽103a和103b和终端沟槽104a、104b、104c和104d分别由外延层102的表面102s向下延伸进入外延层102中(如图1B所示出)。元件沟槽103a和103b之间的间距P1，可以与终端沟槽104a、104b、104c和104d之间的间距P2相同或不同。另外，主动区102A边缘的元件沟槽103a和终端区102T边缘的终端沟槽104a二者之间的距离d1，可以与间距P1或P2相同或不同。
然后，在外延层102上形成一介电层105，使介电层105分别覆盖于元件沟槽103a和103b的底部103r和侧壁103s上，同时覆盖于终端沟槽104a、104b、104c和104d的底部104r和侧壁104s上(如图1C所示出)。
接着在栅极介电层(闸介电层)105上沉积多晶硅材料，以填充元件沟槽103a和103b和终端沟槽104a、104b、104c和104d。并以介电层105为停止层，移除位于栅极介电层105上的多晶硅材料。再以另一次光刻胶蚀刻制程(未示出)，移除位于元件沟槽103a和103b和终端沟槽104a、104b、104c和104d中的一部分多晶硅材料，以分别于元件沟槽103a和103b的底部103r形成分离电极106a和106b，并且分别于终端沟槽104a、104b、104c和104d的底部104r形成一个下方终端电极107a、107b、107c和107d(如图1D所示出)
再通过热氧化或沉积制程，分别在分离电极106a和106b上方形成介电隔离层109a和109b，同时(但不以此为限)在下方终端电极107a、107b、107c和107d上方形成介电隔离层110a、110b、110c和110d。并且沉积多晶硅材料，以填充元件沟槽103a和103b和终端沟槽104a、104b、104c和104d。经过平坦化后，于填充元件沟槽103a和103b之中形成栅电极111a和111b，并且在终端沟槽104a、104b、104c和104d之中形成上方终端电极112a、112b、112c和112d。
在本实施例中，栅电极111a和111b分别堆叠在分离电极106a和106b上方，且分别通过介电隔离层109a和109b彼此电性隔离。上方终端电极112a、112b、112c和112d分别堆叠在下方终端电极107a、107b、107c和107d上，且分别通过介电隔离层110a、110b、110c和110d彼此电性隔离。
其中，栅电极111a和111b及分离电极106a和106b，分别通过形成在元件沟槽103a和103b的底部103r和侧壁103s上的一部分介电层105与主动区102A中的外延层102电性隔离。上方终端电极112a、112b、112c和112d及下方终端电极107a、107b、107c和107d分别通过形成在终端沟槽104a、104b、104c和104d的底部104r和侧壁上104s的一部分介电层105与终端区102T中的外延层102电性隔离(如图1E所示出)。
然后，在主动区102A和终端区102T上方形成一个介电保护层114。并以罩幕(未示出)遮罩终端区102T，对主动区102A进行多次离子植入制程，先于主动区102A中的外延层102中形成多个具有p型电性的掺杂阱区115。并且在主动区102A边缘的元件沟槽103a和终端区102T边缘的终端沟槽104a之间，形成一个具有p型电性的边界掺杂区113。再于掺杂阱区115中形成多个n型电性的源极掺杂区116，分别邻接于对应的栅电极111a和111b(如图1F所示出)。
之后，以光刻胶蚀刻制程(未示出)图案化介电保护层114，形成多个开将位于主动区102A中的源极掺杂区116暴露于外。并于图案化的介电保护层114上形成接触金属层118，使其填满开口而形成接触插塞117a和117b，分别与源极掺杂区116电性接触。在本实施例中，接触金属层118同时覆盖于终端区102T上方，并与位于终端区102T中的所有上方终端电极112a、112b、112c和112d及下方终端电极107a、107b、107c和107d重叠，且通过与图案化介电保护层114使接触金属层118与位于终端区102T的一部分外延层102电性隔离。但在本说明书的一些实施例中，接触金属层118可以仅与位于终端区102T中的一部分上方终端电极112a、112b、112c和112d及一部分的下方终端电极107a、107b、107c和107d重叠。
在本说明书的一些实施例中，还可以选择性地在终端沟槽104a、104b、104c和104d的外侧进行离子植入制程，以形成一个具有p型电性的环形掺杂区123，围绕终端区102T。在本实施例中，环形掺杂区123的掺杂深度t1，大于p型电性的掺杂阱区115的掺杂深度t2。
另外，亦可在终端区102T上方形成上方介电层124和钝化层125，覆盖于终端沟槽104a、104b、104c和104d上方的一部分接触金属层118上。在本说明书的一些实施例中，上方介电层124可以是包括氮化硅、聚酰亚胺(polyimide、PI)的多层结构。钝化层125可以是硅氧化物层、氮化硅、塑化层(例如聚酰亚胺(polyimide，PI)层)或上述的组合(如图1G所示出)。
后续，进行一连串的后段制程(Back End of Line，BEOL)，按照功率半导体元件100的设计，分别在终端区102T中形成多个接触插塞(详述如下)，使终端沟槽104a、104b、104c和104d中的上方终端电极112a、112b、112c和112d以及下方终端电极107a、107b、107c和107d，选择性地与接触金属层118电性接触。在主动区102A中形成多个接触插塞120a和120b，使分离电极106a和106b通过接触插塞120a和120b与接触金属层118电性接触。并在终端沟槽104a、104b、104c和104d的外侧形成栅极结构121，使其通过接触插塞122a和122b，分别与栅电极111a和111b电性接触，完成如图2A至图2C所示出的功率半导体元件100的制备。
图2A是根据本说明书的一实施例所示出的功率半导体元件100的部分布线结构上视图；图2B是沿着图2A的切线S1所示出的功率半导体元件100部分结构剖面图；以及图2C是沿着图2A的切线S2所示出的功率半导体元件100部分结构剖面图。
在本实施例中，位于终端沟槽104a中的上方终端电极112a和下方终端电极107a，分别通过接触插塞119a和119b与接触金属层118电性接触。位于终端沟槽104b中的上方终端电极112b，通过接触插塞119c与接触金属层118电性接触；位于终端沟槽104b中的下方终端电极107b则被浮接，而未与任何金属层或导线电性接触)；位于终端沟槽104c中的上方终端电极112c和下方终端电极107c也被浮接，而未与任何金属层或导线电性接触。位于终端沟槽104d中的下方终端电极107d，通过接触插塞119c与接触金属层118电性接触；位于终端沟槽104d中的上方终端电极112d则被浮接，而未与任何金属层或导线电性接触。
通过选择(改变)位于终端沟槽104a、104b、104c和104d中的上方终端电极112a、112b、112c和112d以及下方终端电极107a、107b、107c和107d的电性连接方式，可以调整功率半导体元件100操作时的电场分布，有助于增进功率金属氧化物-半导体晶体管单元的电荷平衡。
另外，在本说明书的一些实施例中，位于终端沟槽104a’中连接上方终端电极112a’以及下方终端电极107a’的接触插塞119a’和119b’可以有不一样的制作方式和结构。请参照图2D，图2D是根据本说明书的另一实施例所示出的功率半导体元件100’部分结构剖面图。由于，上方终端电极112a’以及下方终端电极107a’的连接方式可以预先设定，因此可以在形成上方终端电极112a’、下方终端电极107a’介电隔离层110a’和介电层105’时，让下方终端电极107a’在预定形成接触插塞119b’的位置，直接向上延伸，并与上方终端电极112a’电性连接。然后，再直接以金属材质填充界层开口来形成接触插塞119a’和119b’，分别将上方终端电极112a’和下方终端电极107a’电性连接至接触金属层118；不需要在界层开口的侧壁上形成介电层。
请参照图3，图3是根据本说明书的另一实施例所示出的功率半导体元件200部分结构剖面图。其中，功率半导体元件200的结构大致与功率半导体元件100类似，差别在于功率半导体元件200主动区102A中的栅极211a和211b的结构有所不同。在本实施例中，栅极211a和211b分别填满元件沟槽103a和103b，不包括任何分离电极。另外，功率半导体元件200的环形掺杂区123的电性并不限定为p型。在一实施例中，功率半导体元件200的环形掺杂区123可以是一种n型电性，由外延层102的表面102s延伸进入外延层102的掺杂阱区。
请参照图4，图4是根据本说明书的又一实施例所示出的功率半导体元件400部分结构剖面图。其中，功率半导体元件400主动区402A中的结构大致与功率半导体元件100的主动区102A类似，差别在于功率半导体元件400的环形掺杂区423向终端区402T的边缘外推一段距离H，使环形掺杂区423不直接与终端沟槽104d接触。另外，终端区402T中还包括一个氧化层426和一个金属垫427。
在本实施例中，氧化层426覆盖在终端区402T的外延层102的表面102s上，与位于终端区402T环形掺杂区423部分重叠，并包覆于上方介电层424和钝化层425之中。环形掺杂区423可以是一个具有p型电性或n型电性(以P/N表示)的掺杂阱区423a由外延层102的表面102s延伸进入外延层102。金属垫427位于环形掺杂区423的上方，同时与环形掺杂区423电性接触，并且被介电层424及钝化层425所包覆，可更进一步提供功率半导体元件400较佳的电荷平衡。
根据上述实施例，本说明书是提供一种功率半导体元件及其制造方法，是在一个具有沟槽式结构的功率半导体元件的终端区中配置至少一个沟槽，并于沟槽中配置至少两个上下堆叠且彼此隔离的终端电极场板，使二者同时与源极电性连接，或者同时浮接；抑或使其中一者与源极电性连接，另一者浮接。前述具有沟槽式结构的功率半导体元件，可以例如是(但不限定为)金属氧化物半导体场效应晶体管、金属氧化物半导体萧特基二极管、萧特基阻障二极管或其他合适的功率半导体元件。且沟槽的数目及终端电极场板连接方式的选择，可以根据功率半导体元件操作时的电场需求预先设计，可通过此增进功率金属氧化物-半导体晶体管单元的电荷平衡。
虽然本发明已以实施例公开如上，然其并非用以限定本发明，任何所属技术领域中技术人员，在不脱离本发明的精神和范围内，当可作些许的变动与润饰，故本发明的保护范围当视权利要求所界定者为准。

Claims (10)

1.一种功率半导体元件，包括：
一外延层，具有一第一电性，并包括一主动区和一终端区；
一第一掺杂区，具有一第二电性，位于该主动区的该外延层中；
一第二掺杂区，具有该第一电性，位于该第一掺杂区中；
一接触金属层，位于该外延层上，与该第二掺杂区电性接触；
一元件电极，位于该主动区中的一元件沟槽之中，并与该外延层和该接触金属层电性隔离；
一第一终端电极，位于该终端区中的一第一终端沟槽之中，并与该外延层电性隔离；以及
一第二终端电极，位于该第一终端沟槽的一底部，并与该第一终端电极和该外延层电性隔离；
其中，该第一终端电极和该第二终端电极均能选择浮接或与该接触金属层电性接触。
2.如权利要求1所述的功率半导体元件，其中该第一终端电极和该第二终端电极中未浮接者，与该接触金属层电性连接。
3.如权利要求1所述的功率半导体元件，还包括一分离电极，位于该元件沟槽的一底部，与该元件电极和该外延层电性隔离，并与该接触金属层电性连接。
4.如权利要求3所述的功率半导体元件，其中该元件电极位于该分离电极上方并通过一介电隔离层彼此电性隔离；且该元件电极和该分离电极是通过覆盖于该元件沟槽的一底部和一侧壁上的一介电层与该外延层电性隔离。
5.如权利要求1所述的功率半导体元件，其中该接触金属层覆盖于该终端区上，并通过一介电层与该终端区电性隔离。
6.如权利要求1所述的功率半导体元件，还包括一边界掺杂区，具有该第二电性，位于该元件沟槽与该第一终端沟槽之间，且与该接触金属层电性隔离。
7.如权利要求1所述的功率半导体元件，还包括:
一第三终端电极，位于该终端区中远离该主动区的一第二终端沟槽之中，并与该外延层电性隔离；以及
一第四终端电极，位于该第二终端沟槽的一底部，并与该第三终端电极和该外延层电性隔离；
其中，该第三终端电极和该第四终端电极均能选择浮接或与该接触金属层电性接触。
8.如权利要求1所述的功率半导体元件，还包括另一元件电极，位于该主动区中延伸进入该外延层的另一元件沟槽之中，并与该外延层和该接触金属层电性隔离。
9.一种功率半导体元件的制作方法，包括：
提供一外延层，使其具有一第一电性，并包括一主动区和一终端区；
于该主动区的该外延层中形成一第一掺杂区，使其具有一第二电性；
于该第一掺杂区中形成一第二掺杂区，具有该第一电性；
于该外延层上形成一接触金属层，与该第二掺杂区电性接触；
于该主动区中形成一元件电极，使其延伸进入该外延层的一元件沟槽之中，并与该外延层和该接触金属层电性隔离；
于该终端区中形成一第一终端电极，使其位于延伸进入该外延层的一第一终端沟槽之中，并与该外延层电性隔离；以及
于该第一终端沟槽的一底部形成一第二终端电极，使其与该第一终端电极和该外延层电性隔离；其中，该第一终端电极和该第二终端电极均能选择浮接或与该接触金属层电性接触。
10.如权利要求9所述的功率半导体元件的制作方法，其中该元件沟槽和该第一终端沟槽同时形成；且该元件电极和该第一终端电极同时形成。
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