JP5671481B2 - ナノワイヤ・メッシュ・デバイス及びその製造方法 - Google Patents
ナノワイヤ・メッシュ・デバイス及びその製造方法 Download PDFInfo
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- JP5671481B2 JP5671481B2 JP2011549448A JP2011549448A JP5671481B2 JP 5671481 B2 JP5671481 B2 JP 5671481B2 JP 2011549448 A JP2011549448 A JP 2011549448A JP 2011549448 A JP2011549448 A JP 2011549448A JP 5671481 B2 JP5671481 B2 JP 5671481B2
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- Y10S977/742—Carbon nanotubes, CNTs
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- Ceramic Engineering (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
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Description
12:SOI基板
12A:埋込み絶縁層
12B:上部半導体層
14:材料スタック
15:半導体材料
15’:犠牲材料
16:第1のハードマスク層
18:第2のハードマスク層
19:窒化物ライナ
20:パターン形成されたハードマスク
24:ダミー・ゲート
25:トレンチ
26:犠牲材料層
28:フィン
30:スペーサ
32:半導体ナノワイヤ
34:ゲート導体
36A:ソース領域
36B:ドレイン領域
Claims (22)
- 基板の表面上に配置された、垂直方向に積層され垂直方向に離間配置された複数の半導体ナノワイヤであって、各々の半導体ナノワイヤは2つの端部セグメントを有し、前記基板の表面に犠牲材料により垂直方向に離間配置された複数の半導体材料からなる複数のソース領域及びドレイン領域に対して、前記端部セグメントの一方は前記ソース領域に接続され、前記端部セグメントの他方は前記ドレイン領域に接続される、垂直方向に積層され垂直方向に離間配置された複数の半導体ナノワイヤと、
前記垂直方向に積層され垂直方向に離間配置された複数の半導体ナノワイヤの少なくとも一部分の上にゲート誘電体及びゲート導体を含むゲート領域であって、前記各ソース領域及び前記各ドレイン領域はゲート領域と自己整合される、ゲート領域と、
を含む半導体構造体。 - 前記半導体ナノワイヤの各々は、200nm未満のピッチ及び40nm未満の幅を有する、請求項1に記載の半導体構造体。
- 前記半導体ナノワイヤの各々は、Si含有半導体材料を含む、請求項1に記載の半導体構造体。
- 前記半導体ナノワイヤの各々は、5%未満又はこれと等しい高さの変動を有する、請求項1に記載の半導体構造体。
- 垂直方向に積層され垂直方向に離間配置された各々の半導体ナノワイヤの間、及び、前記ゲート領域と前記ソース及びドレイン領域との間に配置されたスペーサをさらに含む、請求項1に記載の半導体構造体。
- 垂直方向に離間配置された各々の半導体ナノワイヤは、200nm未満の距離だけ分離される、請求項1に記載の半導体構造体。
- 各々の半導体ナノワイヤ上に配置され、5nm未満の厚さを有する界面酸化物層をさらに含む、請求項1に記載の半導体構造体。
- 前記ソース領域及びドレイン領域の上部に配置され、前記ゲート領域を取り囲み、かつ、前記ゲート領域の上面と同一平面上の上面を有する犠牲材料層を更に含む、請求項1に記載の半導体構造体。
- 半導体オン・インシュレータ基板の埋込み絶縁層の表面上に配置された、垂直方向に積層され垂直方向に離間配置された複数のシリコン・ナノワイヤであって、各々のシリコン・ナノワイヤは2つの端部セグメントを有し、前記基板の表面に犠牲材料により垂直方向に離間配置された複数の半導体材料からなる複数のソース領域及びドレイン領域に対して、前記端部セグメントの一方は前記ソース領域に接続され、前記端部セグメントの他方は前記ドレイン領域に接続され、前記シリコン・ナノワイヤの各々は、200nm未満のピッチと、40nm未満の幅と、5%未満又はこれと等しい高さの変動とを有する、垂直方向に積層され垂直方向に離間配置された複数のシリコン・ナノワイヤと、
前記垂直方向に積層され垂直方向に離間配置された複数のシリコン・ナノワイヤの少なくとも一部分の上にゲート誘電体及びゲート導体を含むゲート領域であって、各ソース領域及び各ドレイン領域はゲート領域と自己整合される、ゲート領域と、
前記ソース領域及びドレイン領域の上部に配置され、前記ゲート領域を取り囲み、かつ、前記ゲート領域の上面と同一平面上の上面を有する、犠牲材料層と、
を含む半導体構造体。 - 垂直方向に離間配置された各々のシリコン・ナノワイヤは、200nm未満の距離だけ分離される、請求項9に記載の半導体構造体。
- 各々のシリコン・ナノワイヤ上に配置され、5nm未満の厚さを有する界面酸化物層をさらに含む、請求項9に記載の半導体構造体。
- 垂直方向に積層され垂直方向に離間配置された各々のシリコン・ナノワイヤの間、及び、前記ゲート領域と各ソース領域及び各ドレイン領域との間に配置されたスペーサをさらに含む、請求項9に記載の半導体構造体。
- 半導体構造体を形成する方法であって、
半導体材料及び犠牲材料の交互層を含むパターン形成された材料スタックの上部に複数のパターン形成されたハードマスクを準備することであって、前記パターン形成された材料スタックの最下層は半導体基板の上部半導体層である、準備することと、
前記複数のパターン形成されたハードマスクの各々の中央部の上に少なくとも1つのダミー・ゲートを形成することと、
前記少なくとも1つのダミー・ゲートに当接する犠牲材料層を形成することと、
前記少なくとも1つのダミー・ゲートを除去して、前記犠牲材料層内に少なくとも1つのトレンチを形成することであって、各々のトレンチは、前記複数のパターン形成されたハードマスクの前記中央部の上に中心があり、フィン領域をソース及びドレイン領域と区別する、除去することと、
前記複数のパターン形成されたハードマスクをエッチング・マスクとして用いて、前記パターン形成された材料スタックの前記少なくとも1つのトレンチ内に複数のフィンをエッチングすることと、
前記少なくとも1つのトレンチ内の前記複数のパターン形成されたハードマスク及び犠牲材料の各層を除去して、前記少なくとも1つのトレンチ内に、垂直方向に積層され垂直方向に離間配置された複数の半導体ナノワイヤを形成することと、
前記少なくとも1つのトレンチを少なくともゲート領域で充填することと、
を含む方法。 - 前記半導体基板は半導体オン・インシュレータであり、前記パターン形成された材料スタックの前記最下層は埋込み絶縁層上に配置される、請求項13に記載の方法。
- 前記上部半導体層を除く犠牲材料及び半導体材料の前記交互層は、エピタキシャル成長プロセスによって形成され、前記エピタキシャル成長プロセスは、800℃未満の温度及び100トール未満の圧力で実行される、請求項13に記載の方法。
- 前記犠牲材料層の各層は、前記エピタキシャル成長プロセス中にin-situ(インサイチュ)でドープされた半導体材料である、請求項15に記載の方法。
- 前記複数のパターン形成されたハードマスクを除去することと、前記少なくとも1つのトレンチ内の犠牲材料の各層を除去することとの間に、前記少なくとも1つのトレンチ内にスペーサを形成することをさらに含み、前記スペーサは、堆積及びエッチングによって形成され、前記エッチングは、各フィンの側壁上にスペーサ材料が残らないように、大規模のオーバーエッチングを用いて実行される、請求項13に記載の方法。
- 前記犠牲材料の各層を除去することは、前記半導体材料の層と比較してより低い前記犠牲材料の酸化電位を利用するエッチング剤を用いて化学的に実行される、請求項13に記載の方法。
- 前記犠牲材料の各層を除去することは、プラズマ・エッチング・プロセスを用いて実行される、請求項13に記載の方法。
- 前記少なくとも1つのトレンチ内の前記複数のパターン形成されたハードマスク及び犠牲材料の各層を除去することと、前記少なくとも1つのトレンチを少なくともゲート領域で充填することとの間に固体ソース拡散アニールを実行することをさらに含み、前記固体ソース拡散アニールは、前記少なくとも1つのトレンチの外部にある前記半導体材料層内にソース領域及びドレイン領域を形成する、請求項13に記載の方法。
- 前記固体ソース拡散アニールは、不活性雰囲気中で、800℃又はこれより高い温度で実行される、請求項20に記載の方法。
- 各々の半導体ナノワイヤは、200nm未満のピッチ及び40nm未満の幅を有する、請求項13に記載の方法。
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