CN104979211B - 纳米线器件及其制造方法 - Google Patents

纳米线器件及其制造方法 Download PDF

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CN104979211B
CN104979211B CN201410145605.XA CN201410145605A CN104979211B CN 104979211 B CN104979211 B CN 104979211B CN 201410145605 A CN201410145605 A CN 201410145605A CN 104979211 B CN104979211 B CN 104979211B
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CN104979211A (zh
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洪中山
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
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Abstract

本发明实施例公开了一种纳米线器件及其制造方法，其中，纳米线器件的制造方法包括：在衬底上悬置的纳米线表面形成第一绝缘层；在衬底上沉积伪栅材料并图案化伪栅材料，形成伪栅结构和被伪栅结构全包围的沟道区，其中的伪栅结构包括伪栅、和伪栅与沟道区之间的第一绝缘层；氧化伪栅，在伪栅的两侧表面形成第一氧化层；以及分别对沟道区的两侧进行纳米线外延至支撑垫，形成源区和漏区。基于本发明实施例得到的纳米线器件中，具有纳米线以上的栅极轮廓和纳米线以下的栅极轮廓一致的栅极轮廓。

Description

纳米线器件及其制造方法
技术领域
本发明涉及半导体技术领域，尤其涉及纳米线器件及其制造方法。
背景技术
随着微电子器件的尺寸进入15纳米（nm）节点，维持载流子迁移率的改善和短沟道控制对半导体器件制造提出了挑战。纳米线器件，即沟道长度为纳米数量级的半导体器件，可以提供改善的迁移率和短沟道控制，例如，锗沟道有助于提高P沟道金属氧化物半导体（positive channel Metal Oxide Semiconductor，PMOS）晶体管载流子的迁移率，III-V族半导体材料的沟道有助于提高N沟道金属氧化物半导体（negative channel Metal OxideSemiconductor，NMOS）晶体管载流子的迁移率。
在实现本发明的过程中，发明人发现，在制造纳米线器件的过程中，现有技术是利用各向同性刻蚀工艺去除纳米线下面的伪栅材料，通过该方式得到的纳米线器件中，纳米线以上的栅极轮廓和纳米线以下的栅极轮廓不能一致，难以达到对栅极轮廓的要求。
发明内容
本发明的发明人针对上述现有技术中存在的问题提出了新的技术方案以使得纳米线以下的栅极轮廓与纳米线以上的栅极轮廓一致。
根据本发明实施例的一个方面，提供一种纳米线器件的制造方法，包括：
在衬底上悬置的纳米线表面形成第一绝缘层；所述衬底包括两个支撑垫和两个支撑垫之间的凹槽，两个支撑垫上分别具有第二绝缘层，凹槽的底面上具有第三绝缘层，在所述凹槽的上方通过两个支撑垫悬置有至少一根纳米线；
在所述衬底上沉积伪栅材料并图案化所述伪栅材料，形成伪栅结构和被所述伪栅结构全包围的沟道区，所述伪栅结构包括伪栅、和伪栅与沟道区之间的第一绝缘层；
氧化伪栅，在伪栅的两侧表面形成第一氧化层；以及
分别对沟道区的两侧进行纳米线外延至支撑垫，形成源区和漏区。
在一个实施例的制造方法中，图案化所述伪栅材料包括：在所述伪栅材料上形成硬掩膜层；图案化所述硬掩膜层，定义栅极区域；各向异性刻蚀所述伪栅材料、纳米线、以及纳米线周围的第一绝缘层直至去除部分所述第三绝缘层。
在一个实施例的制造方法中，所述纳米线的材料具体为锗或III-V族半导体材料，所述伪栅材料具体为多晶硅锗、多晶硅、非晶硅或非晶硅锗。
在一个实施例的制造方法中，所述纳米线的材料具体为单晶硅，所述伪栅材料具体为多晶硅锗或者非晶硅锗。
在一个实施例的制造方法中，所述氧化伪栅还包括：在沟道区的两侧表面形成第二氧化层；所述氧化伪栅之后，还包括：去除部分第一氧化层和全部第二氧化层，以暴露出沟道区侧面。
在一个实施例的制造方法中，所述第一氧化层的厚度大于所述第二氧化层的厚度。
在一个实施例的制造方法中，所述纳米线为两根以上时，其中若干根纳米线的材料为锗或III-V族半导体材料，其余纳米线的材料为单晶硅，伪栅材料为多晶硅锗或者非晶硅锗。
在一个实施例的制造方法中，对沟道区的两侧进行纳米线外延时，还对沟道区两侧的纳米线外延部分进行原位掺杂。
在一个实施例的制造方法中，形成源区和漏区之后，还包括：至少进行一次离子注入；所述离子注入包括漏轻掺杂注入或源区/漏区掺杂注入。
在一个实施例的制造方法中，形成源区和漏区之后，还包括：
通过自对准硅化物工艺，在伪栅、源区和漏区分别形成硅化物。
在一个实施例的制造方法中，还包括：分别在源区和漏区的表面、伪栅的侧面、和衬底上形成氮化硅层；在所述氮化硅层上形成层间介质层；进行化学机械抛光以露出伪栅；去除伪栅和第一绝缘层，形成沟槽；形成栅极结构。
在一个实施例的制造方法中，所述形成栅极结构包括：在沟道区表面形成界面氧化层；在所述界面氧化层上、沟槽侧壁及沟槽底部形成高K栅介质层；形成全包围沟道区并覆盖所述高K栅介质层的栅极；进行化学机械抛光以露出栅极。
在一个实施例的制造方法中，所述形成栅极结构包括：在沟道区表面、沟槽侧壁及沟槽底部形成界面氧化层；在所述界面氧化层上形成高K栅介质层；形成全包围沟道区并覆盖所述高K栅介质层的栅极；进行化学机械抛光以露出栅极。
根据本发明实施例的另一方面，提供一种基于上述方法制造的纳米线器件，包括：
衬底，所述衬底包括两个支撑垫和两个支撑垫之间的凹槽，两个支撑垫上分别具有第二绝缘层，凹槽底面上具有第三绝缘层；
在所述凹槽内的上方通过两个支撑垫悬置的纳米线形成的沟道区；
由所述沟道区两侧至支撑垫的纳米线外延部分形成的源区和漏区；
位于第三绝缘层上的栅极结构，所述栅极结构全包围所述沟道区。
在一个实施例的纳米线器件中，所述栅极结构包括：全包围所述沟道区的栅极；位于所述栅极与所述沟道区之间的界面氧化层；位于所述界面氧化层上、栅极侧壁及栅极底部的高K栅介质层。
在一个实施例的纳米线器件中，所述栅极结构包括：全包围所述沟道区的栅极；位于所述沟道区表面、栅极侧壁及栅极底部的界面氧化层；位于所述界面氧化层上的高K栅介质层。
在一个实施例的纳米线器件中，所述纳米线的材料具体为锗或III-V族半导体材料，所述栅极的材料具体为金属、多晶硅锗、多晶硅、非晶硅或非晶硅锗；或者，所述纳米线的材料具体为单晶硅，所述栅极的材料具体为金属、多晶硅锗或者非晶硅锗。
在一个实施例的纳米线器件中，所述纳米线为两根以上时，其中若干根纳米线的材料为锗或III-V族半导体材料，其余纳米线的材料为单晶硅，伪栅材料为多晶硅锗或者非晶硅锗。
在一个实施例的纳米线器件中，所述源区和漏区包括掺杂剂。
在一个实施例的纳米线器件中，还包括：位于所述源区和漏区周围、栅极的侧面、以及衬底上的氮化硅层；位于所述氮化硅层上的层间介质层。
基于本发明上述实施例纳米线器件及其制造方法，定义栅极区域后以栅极区域为掩模刻蚀去除栅极区域以外的纳米线，之后再外延形成源区和漏区，与现有技术相比，所形成的纳米线以下的栅极轮廓和纳米线以上的栅极轮廓一致，从而可以达到栅极轮廓的要求。
通过以下参照附图对本发明的示例性实施例的详细描述，本发明的其它特征及其优点将会变得清楚。
附图说明
构成说明书的一部分的附图描述了本发明的实施例，并且连同说明书一起用于解释本发明的原理。
根据下面参照附图的详细描述，可以更加清楚地理解本发明，在附图中：
图1是本发明一个实施例纳米线器件的制造方法的流程图；
图2a是本发明实施例中衬底的结构示意图；
图2b是本发明实施例中衬底的结构俯视图；
图3是本发明实施例中在衬底上悬置的纳米线表面形成第一绝缘层后的示意图；
图4是本发明实施例中在衬底上形成伪栅材料后的示意图；
图5a是本发明实施例中形成伪栅结构和伪栅结构全包围的沟道区后的示意图；
图5b是图5a所示结构的剖面图；
图6是本发明实施例中在伪栅的两侧表面形成第一氧化层后的示意图；
图7是本发明实施例中形成源区和漏区后的示意图；
图8是本发明另一个实施例中同时在沟道区两侧形成第二氧化层后的示意图；
图9是本发明另一个实施例中去除部分第一氧化层和全部第二氧化层后的示意图；
图10是本发明另一个实施例中形成硅化物后的示意图；
图11是本发明再一个实施例纳米线器件的制造方法的流程图；
图12是本发明另一个实施例中形成氮化硅层后的示意图；
图13是本发明另一个实施例中进行化学机械抛光露出伪栅后的示意图；
图14是本发明另一个实施例中形成沟槽后的示意图；
图15是本发明再一个实施例中形成栅极结构后的示意图；
图16是本发明再一个实施例中形成栅极结构后的示意图；
图17是本发明实施例形成的纳米线器件的结构示意图。
具体实施方式
现在将参照附图来详细描述本发明的各种示例性实施例。应理解，除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不应被理解为对本发明范围的限制。
此外，应当理解，为了便于描述，附图中所示出的各个部件的尺寸并不必然按照实际的比例关系绘制。
以下对示例性实施例的描述仅仅是说明性的，决不作为对本发明及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和装置可能不作详细讨论，但在适用这些技术、方法和装置情况下，这些技术、方法和装置应当被视为本说明书的一部分。
在这里示出和讨论的所有示例中，任何具体值都应被解释为仅仅是示例性的，而不是作为限制。因此，示例性实施例的其它示例可以具有不同的值。
应注意，相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图的说明中将不需要对其进行进一步讨论。
图1是本发明一个实施例纳米线器件的制造方法的流程图。如图1所示，该实施例纳米线器件的制造方法包括：
在步骤101中，在衬底100上悬置的纳米线122表面形成第一绝缘层210。
示例性地，可以通过原子层沉积（Atomic Layer Deposition，ALD）或化学气相沉积（Chemical Vapor Deposition，CVD）等工艺在衬底100上悬置的纳米线122表面形成第一绝缘层210。
如图2a和图2b所示，分别是本发明实施例中衬底的结构示意图和俯视图。参见图2a和图2b，该衬底100可以示例性包括：两个支撑垫110和两个支撑垫110之间的凹槽120，两个支撑垫110上分别具有第二绝缘层111，凹槽120的底面上具有第三绝缘层121，在凹槽120的上方通过两个支撑垫110悬置有至少一根纳米线122。示例性地，第二绝缘层111具体可以是氮化硅层，第三绝缘层121具体可以是氧化硅层。
图2a和图2b仅示例性地示出了一根纳米线122，但本发明实施例并不限于此，例如，衬底100的凹槽120上方可以悬置有多根平行的纳米线（未示出），组成纳米线阵列。该纳米线阵列中的纳米线可以是，例如在图2a和图2b中示出的纳米线122的上下方与其平行排列，或者，可以是在图2a和图2b中示出的纳米线122的相同高度上与其平行地排列。此外，纳米线的形状不限于圆柱形，例如，还可以是柱形等。
如图3所示，为本发明实施例中在衬底上悬置的纳米线表面形成第一绝缘层后的示意图。
在步骤102中，在衬底100上沉积伪栅材料211并图案化该伪栅材料211，形成伪栅结构213和被伪栅结构213全包围的沟道区132。
如图4所示，为本发明实施例中在衬底上形成伪栅材料后的示意图。
图5a和图5b分别是本发明实施例中形成伪栅结构和伪栅结构全包围的沟道区后的示意图和剖面图。如图5a和图5b所示，伪栅结构213包括伪栅211、和伪栅211与沟道区132之间的第一绝缘层210。
在步骤103中，氧化伪栅211，在伪栅211的两侧表面形成第一氧化层310。示例性地，第一氧化层310具体可以是氧化硅层。如图6所示，为本发明实施例中在伪栅的两侧表面形成第一氧化层后的示意图。
在步骤104中，分别对沟道区132的两侧进行纳米线外延至支撑垫110，形成源区142和漏区152。
示例性地，进行纳米线外延以后，可以去除或者保留第一氧化层310。
通过图1所示流程，形成纳米线以上的栅极轮廓与纳米线以下的栅极轮廓一致的纳米线器件。如图7所示，为本发明实施例中形成源区和漏区后的示意图。通过刻蚀去除栅极区域以外的纳米线，之后再外延形成源区和漏区，所形成的纳米线以下的栅极轮廓和纳米线以上的栅极轮廓一致，能够达到栅极轮廓的要求。
根据本发明上述纳米线器件的制造方法实施例的一个具体示例而非限制，步骤102中图案化伪栅材料211具体可以通过以下操作实现：在伪栅材料211上形成硬掩膜层（未示出），该硬掩膜例如可以是氮化硅（SiN）、氧化硅（SiO2）、氮碳化硅（SiCN）等；图案化该硬掩膜层，以定义栅极区域；然后通过各向异性刻蚀刻蚀伪栅材料211、纳米线122、以及纳米线122周围的第一绝缘层210直至去除部分第三绝缘层121，形成图5a中所示的伪栅结构213和被该伪栅结构213全包围的沟道区132。
根据本发明纳米线器件的制造方法实施例的一个具体示例而非限制，纳米线122的材料具体可以采用锗或III-V族半导体材料，相应地，伪栅材料211具体可以为多晶硅锗（SiGe）、多晶硅、非晶硅或非晶SiGe。
此外，根据本发明纳米线器件的制造方法的另一个具体示例而非限制，纳米线122的材料也可以采用单晶硅（Si），相应地，伪栅材料211具体可以为多晶SiGe或者非晶SiGe。
在本发明另一个实施例纳米线器件的制造方法中，与图1所示的实施例相比，步骤103中氧化伪栅还可以包括：在沟道区132的两侧表面形成第二氧化层320。示例性地，第一氧化层310的厚度大于第二氧化层320的厚度，例如，第一氧化层310的厚度为第二氧化层320的厚度的1.5倍。如图8所示，为本发明另一个实施例中在沟道区两侧形成第二氧化层后的示意图。相应地，该实施例中，在氧化伪栅之后，还可以采用湿法清洗去除部分第一氧化层310和全部第二氧化层320，以暴露出沟道区132侧面。如图9所示，为本发明另一个实施例中去除部分第一氧化层和全部第二氧化层后的示意图。
在本发明上述各实施例纳米线器件的制造方法中，纳米线为两根以上时，不同纳米线可以采用不同的材料，例如，其中若干根纳米线采用材料为锗或III-V族半导体材料，其余纳米线采用单晶硅，伪栅材料采用多晶SiGe或者非晶SiGe。
在本发明又一个实施例纳米线器件的制造方法中，对沟道区132的两侧进行纳米线外延时，还可以对沟道区132两侧的纳米线外延部分进行原位掺杂。例如，可以在NMOS中原位掺杂P；可以在PMOS中原位掺杂B。应理解，本发明并不限于此。
在本发明又一个实施例纳米线器件的制造方法中，形成源区142和漏区152之后，还可以包括至少进行一次离子注入的操作。其中的离子注入可以是漏轻掺杂（LDD）注入和/或源区/漏区掺杂注入。示例性地，对于NMOS，LDD可以注入砷离子，源区/漏区掺杂注入可以注入磷离子；对于POS，LDD可以注入BF2 +，源区/漏区掺杂注入可以注入硼离子。然而，本发明不限于此，可以根据器件的类型选择合适的离子进行注入。
在本发明另一个实施例纳米线器件的制造方法中，形成源区142和漏区152之后，还包括：通过自对准硅化物工艺，在伪栅211、源区142和漏区152分别形成相应的硅化物510。示例性地，可以在伪栅211、源区142和漏区152上沉积Ti或Co，退火形成自对准的金属硅化物510，然后湿法刻蚀去除未反应的金属。如图10所示，为本发明另一个实施例中形成硅化物后的示意图。
图11是本发明再一个实施例纳米线器件的制造方法的流程图。如图11所示，该实施例在图1所示实施例的流程之后，还包括：
步骤105，分别在源区142和漏区152的表面、伪栅211的侧面、和衬底100上形成氮化硅层330。
如图12所示，为本发明另一个实施例中形成氮化硅层后的示意图。
步骤106，在氮化硅层330上形成ILD340；进行化学机械抛光以露出伪栅211。
如图13所示，为本发明另一个实施例中进行化学机械抛光露出伪栅后的示意图。
步骤107，采用干法刻蚀去除伪栅211和第一绝缘层210，形成沟槽610。
如图14所示，为本发明另一个实施例中形成沟槽后的示意图。
步骤108，形成栅极结构。
示例性地，可以通过如下方式形成栅极结构：在沟道区132表面形成界面氧化层410；采用ALD等方法在界面氧化层410上、沟槽610侧壁及沟槽610底部形成高K栅介质层420；形成全包围沟道区132并覆盖高K栅介质层420的栅极430，例如金属栅极；进行化学机械抛光以露出栅极430。如图15所示，为本发明再一个实施例中形成栅极结构后的示意图。
另外，也可以通过如下方式形成栅极结构：在沟道区132表面、沟槽610侧壁及沟槽610底部形成界面氧化层410；在界面氧化层410上形成高K栅介质层420；形成全包围沟道区132并覆盖高K栅介质层420的栅极430；进行化学机械抛光以露出栅极430。如图16所示，为本发明再一个实施例中形成栅极结构后的示意图。
示例性地，界面氧化层410可以是SiO2，高K栅介质层420可以是氧化铪、氧化铝、氧化钽、氧化钛或氧化锆，栅极430可以是金属栅极。
本发明实施例还提供了一种纳米线器件，该纳米线器件可以示例性地通过上述实施例的制造方法形成，如图17所示，为本发明实施例形成的纳米线器件的结构示意图，其包括：
衬底100，衬底100包括两个支撑垫110和两个支撑垫110之间的凹槽120，两个支撑垫110上分别具有第二绝缘层111，凹槽120底面上具有第三绝缘层121；
在凹槽120内的上方通过两个支撑垫110悬置的纳米线形成的沟道区132；
由沟道区132两侧至支撑垫110的纳米线外延形成的源区142和漏区152；和
位于第三绝缘层121上的栅极结构，该栅极结构全包围沟道区132。
参见图15，在本发明另一个实施例的纳米线器件中，栅极结构具体可以包括：
全包围沟道区132的栅极430；
位于栅极430与沟道区132之间的界面氧化层410；和
位于界面氧化层410上、栅极430侧壁及栅极430底部的高K栅介质层420。
参见图16，在本发明又一个实施例的纳米线器件中，栅极结构具体也可以包括：
全包围沟道区132的栅极430；
位于沟道区132表面、栅极430侧壁及栅极430底部的界面氧化层410；和
位于界面氧化层410上的高K栅介质层420。
根据本发明上述纳米线器件实施例的一个具体示例而非限制，纳米线的材料具体可以采用锗或III-V族半导体材料，相应地，栅极的材料可以为金属、或者诸如多晶SiGe、多晶硅、非晶硅或非晶SiGe的伪栅材料。
根据本发明上述纳米线器件实施例的另一个具体示例而非限制，纳米线的材料可以采用为单晶Si，相应地，栅极的材料可以为金属、或者诸如多晶SiGe或者非晶SiGe的伪栅材料。
在本发明上述各实施例纳米线器件中，纳米线为两根以上时，不同纳米线可以采用不同的材料，例如，其中若干根纳米线采用材料为锗或III-V族半导体材料，其余纳米线采用单晶硅，栅极材料采用金属、或者诸如多晶SiGe或非晶SiGe的伪栅材料。
在本发明另一个实施例纳米线器件中，源区142和漏区152包括掺杂剂。应明白，这里的掺杂剂可以根据不同器件的类型进行选择。
在本发明另一个实施例纳米线器件中，参见图15或图16，还可以包括：
位于源区142和漏区152周围、栅极430的侧面、以及衬底100上的氮化硅层330；和
位于氮化硅层330上的ILD340。
至此，已经详细描述了根据本发明实施例纳米线器件及其制造方法。为了避免遮蔽本发明的构思，没有描述本领域所公知的一些细节，本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。另外，本说明书公开所教导的各实施例可以自由组合。
本说明书中各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其它实施例的不同之处，各个实施例之间相同或相似的部分相互参见即可。由于纳米线器件实施例与其制造方法实施例基本对应，相关之处相互参见对应实施例部分的说明即可。
除非另有说明，诸如“第一”和“第二”的术语用于任意区分这些术语所描述的元素。因此，这些术语并不必然旨在表示这些元素的时间的或其它的优先次序。
本领域的技术人员应该理解，可以对上面说明的实施例进行多种修改而不脱离如所附权利要求限定的本发明的精神和范围。

Claims (20)

1.一种纳米线器件的制造方法，其特征在于，包括：
在衬底上悬置的纳米线表面形成第一绝缘层；所述衬底包括两个支撑垫和两个支撑垫之间的凹槽，两个支撑垫上分别具有第二绝缘层，凹槽的底面上具有第三绝缘层，在所述凹槽的上方通过两个支撑垫悬置有至少一根纳米线；
在所述衬底上沉积伪栅材料并图案化所述伪栅材料，形成伪栅结构和被所述伪栅结构全包围的沟道区，所述伪栅结构包括伪栅、和伪栅与沟道区之间的第一绝缘层；
氧化伪栅，在伪栅的两侧表面形成第一氧化层；以及
分别对沟道区的两侧进行纳米线外延至支撑垫，形成源区和漏区；
其中，在图案化所述伪栅材料的步骤中，所述纳米线除所述沟道区以外的区域、包围该区域的第一绝缘层、以及包围该区域的伪栅材料被去除。
2.根据权利要求1所述的方法，其特征在于，图案化所述伪栅材料包括：
在所述伪栅材料上形成硬掩膜层；
图案化所述硬掩膜层，定义栅极区域；
各向异性刻蚀所述伪栅材料、纳米线、以及纳米线周围的第一绝缘层直至去除部分所述第三绝缘层。
3.根据权利要求2所述的方法，其特征在于，所述纳米线的材料具体为锗或III-V族半导体材料，所述伪栅材料具体为多晶硅锗、多晶硅、非晶硅或非晶硅锗。
4.根据权利要求2所述的方法，其特征在于，所述纳米线的材料具体为单晶硅，所述伪栅材料具体为多晶硅锗或者非晶硅锗。
5.根据权利要求4所述的方法，其特征在于，所述氧化伪栅还包括：在沟道区的两侧表面形成第二氧化层；
所述氧化伪栅之后，还包括：去除部分第一氧化层和全部第二氧化层，以暴露出沟道区侧面。
6.根据权利要求5所述的方法，其特征在于，所述第一氧化层的厚度大于所述第二氧化层的厚度。
7.根据权利要求2所述的方法，其特征在于，所述纳米线为两根以上时，其中若干根纳米线的材料为锗或III-V族半导体材料，其余纳米线的材料为单晶硅，伪栅材料为多晶硅锗或者非晶硅锗。
8.根据权利要求2所述的方法，其特征在于，对沟道区的两侧进行纳米线外延时，还对沟道区两侧的纳米线外延部分进行原位掺杂。
9.根据权利要求2所述的方法，其特征在于，形成源区和漏区之后，还包括：
至少进行一次离子注入；所述离子注入包括漏轻掺杂注入或源区/漏区掺杂注入。
10.根据权利要求1至9任意一项所述的方法，其特征在于，形成源区和漏区之后，还包括：
通过自对准硅化物工艺，在伪栅、源区和漏区分别形成硅化物。
11.根据权利要求1至9任意一项所述的方法，其特征在于，还包括：
分别在源区和漏区的表面、伪栅的侧面、和衬底上形成氮化硅层；
在所述氮化硅层上形成层间介质层；
进行化学机械抛光以露出伪栅；去除伪栅和第一绝缘层，形成沟槽；
形成栅极结构。
12.根据权利要求11所述的方法，其特征在于，所述形成栅极结构包括：
在沟道区表面形成界面氧化层；
在所述界面氧化层上、沟槽侧壁及沟槽底部形成高K栅介质层；
形成全包围沟道区并覆盖所述高K栅介质层的栅极；
进行化学机械抛光以露出栅极。
13.根据权利要求12所述的方法，其特征在于，所述形成栅极结构包括：
在沟道区表面、沟槽侧壁及沟槽底部形成界面氧化层；
在所述界面氧化层上形成高K栅介质层；
形成全包围沟道区并覆盖所述高K栅介质层的栅极；
进行化学机械抛光以露出栅极。
14.一种基于权利要求1至13任意一项方法制造的纳米线器件，其特征在于，包括：
衬底，所述衬底包括两个支撑垫和两个支撑垫之间的凹槽，两个支撑垫上分别具有第二绝缘层，凹槽底面上具有第三绝缘层；
在所述凹槽内的上方通过两个支撑垫悬置的纳米线形成的沟道区；
由所述沟道区两侧至支撑垫的纳米线外延部分形成的源区和漏区；
位于第三绝缘层上的栅极结构，所述栅极结构全包围所述沟道区。
15.根据权利要求14所述的器件，其特征在于，所述栅极结构包括：
全包围所述沟道区的栅极；
位于所述栅极与所述沟道区之间的界面氧化层；
位于所述界面氧化层上、栅极侧壁及栅极底部的高K栅介质层。
16.根据权利要求14所述的器件，其特征在于，所述栅极结构包括：
全包围所述沟道区的栅极；
位于所述沟道区表面、栅极侧壁及栅极底部的界面氧化层；
位于所述界面氧化层上的高K栅介质层。
17.根据权利要求14所述的器件，其特征在于，所述纳米线的材料具体为锗或III-V族半导体材料，所述栅极的材料具体为金属、多晶硅锗、多晶硅、非晶硅或非晶硅锗；或者
所述纳米线的材料具体为单晶硅(Si)，所述栅极的材料具体为金属、多晶硅锗或者非晶硅锗。
18.根据权利要求14所述的器件，其特征在于，所述纳米线为两根以上时，其中若干根纳米线的材料为锗或III-V族半导体材料，其余纳米线的材料为单晶硅，栅极材料为金属、多晶硅锗或者非晶硅锗。
19.根据权利要求14至18任意一项所述的器件，其特征在于，所述源区和漏区包括掺杂剂。
20.根据权利要求19所述的器件，其特征在于，还包括：
位于所述源区和漏区周围、栅极的侧面、以及衬底上的氮化硅层；
位于所述氮化硅层上的层间介质层。
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