CN107660311B - 在替代沟道finfet中的子鳍状物侧壁钝化 - Google Patents
在替代沟道finfet中的子鳍状物侧壁钝化 Download PDFInfo
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- Crystallography & Structural Chemistry (AREA)
Abstract
公开了通过使用子鳍状物钝化层来减少基于鳍状物的晶体管的截止状态泄漏的技术。在一些情况下,所述技术可以包括在体硅衬底中形成牺牲鳍状物以及沉积和平坦化浅沟槽隔离(STI)材料,去除并用替代材料(例如,SiGe或III‑V族材料)替代牺牲硅鳍状物,去除STI材料的至少部分以暴露出替代鳍状物的子鳍状物区域,向暴露出的子鳍状物应用钝化层/处理/剂,以及再沉积和平坦化附加的STI材料。然后可以执行标准晶体管形成工艺以完成晶体管器件。该技术总体上提供为基于STI的沟槽中生长的结构添加任意钝化层的能力。钝化层抑制子鳍状物源极‑漏极(和漏极‑源极)电流泄漏。
Description
背景技术
FinFET是围绕半导体材料的薄带(通常被称为鳍状物)构建的晶体管。晶体管包括标准场效应晶体管(FET)节点,包括栅极、栅极电介质、源极区和漏极区。器件的导电沟道位于栅极电介质下面的鳍状物的外侧。具体而言,电流沿着鳍状物的两个侧壁(垂直于衬底表面的侧面)/在两个侧壁内以及沿着鳍状物的顶部(平行于衬底表面的侧面)流动。因为这种配置的导电沟道基本上沿着鳍状物的三个不同的外部平面区域存在,所以这种FinFET设计有时被称为三栅极晶体管。其它类型的FinFET配置也是可用的,例如所谓的双栅极FinFET,其中导电沟道主要仅沿着鳍状物的两个侧壁(而不沿着鳍状物的顶部)存在。存在与基于鳍状物的晶体管相关联的许多重大的性能问题。
附图说明
图1示出了根据本公开内容的各个实施例的形成集成电路的方法。
图2A-L示出了根据本公开内容的各个实施例在执行图1的方法时形成的示例性结构。
图3A-C示出了根据本公开内容的各个实施例的使用图1的方法形成的图2L的结构的变型。
图4示出了根据本公开内容的实施例的借助于使用本文公开的技术形成的集成电路结构或器件实现的计算系统。
具体实施方式
公开了通过使用子鳍状物钝化层来减少基于鳍状物的晶体管的截止状态泄漏的技术。所述技术可以包括例如将通过纵横比俘获(ART)或其中非硅沟道材料替代牺牲硅鳍状物的类似集成方案形成的晶体管中的子鳍状物侧壁钝化。根据实施例,所述技术包括在衬底中形成牺牲鳍状物以及沉积和平坦化浅沟槽隔离(STI)材料,去除并用替代材料来替代牺牲鳍状物,去除STI材料的至少部分以暴露出替代鳍状物的子鳍状物区域,向暴露出的子鳍状物(以及结构的可能的其它区域)应用钝化层/处理/剂,以及再沉积和平坦化附加STI材料。然后可以执行标准晶体管形成工艺(例如,STI凹陷、栅极叠置体形成、源极/漏极形成、接触部形成)以完成晶体管器件。如根据本公开内容将意识到的,该技术总体上提供了为基于STI的沟槽中生长的结构添加任意钝化层的能力。例如,在硅(Si)衬底的情况下,可以使用非硅材料(例如,硅锗、锗和III-V族材料)来替代牺牲Si鳍状物,同时仍然允许替代鳍状物的钝化以降低界面陷阱密度(Dit)并改善源极-漏极泄漏。根据本公开内容,许多变型和构造将是显而易见的。
总体概述
硅(Si)具有使其保持大量生产用于半导体器件的有用性质。一个这样的性质是二氧化硅钝化Si表面的能力。在Si背景下的钝化包括界面陷阱密度(固定电荷)和杂质感应电荷(通常是移动的)都可以保持较低,例如在1E11个电荷每cm2的数量级。最近,对非Si沟道半导体器件的兴趣增加。例如,Si沟道区被硅锗(SiGe)和III-V族材料替代。然而,这种SiGe和III-V替代材料沟道的固定和移动电荷密度可能比原生Si沟道材料用于Si衬底时高数百倍甚至上千倍。这可能会由于高的源极-漏极泄漏而导致非常大的截止状态电流,从而降低性能或使得包括替代材料沟道的器件不可行。更详细地说,FinFET或三栅极器件具有与鳍状物连续的子沟道区。这允许FinFET的寄生截止状态源极-漏极(以及漏极-源极)电流泄露的导电路径以及沟道-衬底寄生电容。
因此,并且根据本公开内容的一个或多个实施例,公开了用于减少包括替代材料沟道的基于鳍状物的晶体管中的子鳍状物泄漏的技术。漏电流的这种减少是通过使用子鳍状物钝化层来实现的。所述技术可以包括例如将通过纵横比俘获(ART)或其中非硅沟道材料替代牺牲硅鳍状物的类似集成方案形成的晶体管中的子鳍状物侧壁钝化。注意,如本文所使用的,“纵横比俘获”和“ART”通常包括当材料垂直生长时导致材料中的缺陷在侧表面上终止的技术,例如非晶态/电介质侧壁,其中侧壁相对于生长区域的尺寸足够高,以便俘获大部分(如果不是全部)的缺陷。换言之,ART通常使用替代沟道技术,其包括形成鳍状物,移除鳍状物以形成大致为单个鳍状物宽度的STI沟槽,然后将替代材料沉积在大致单个鳍状物宽度的STI沟槽中。因此,ART工艺可以允许标称无缺陷沟道层(其可以包括稍后成为晶体管的源极/漏极和沟道部分的区域)的生长。但是,子鳍状物泄漏的问题依然存在。为此,本文以不同方式描述的技术通过(完全地或部分地)去除替代沟道材料的沉积后的STI材料来解决这个问题,由此提供在再处理STI层之前在替代沟道材料鳍状物上执行钝化的机会。例如,钝化技术可用于化学中和和/或物理保护替代材料鳍状物。例如,钝化材料层可以降低允许电流流动的移动电荷密度,特别是关于通过沟道区中的,具体而言,在晶体管沟道(晶体管沟道是替代材料与栅极接触的部分)下方的,ART子鳍状物侧壁的源极-漏极(或漏极-源极)泄漏。换言之,在一些实施例中,钝化层位于替代材料和STI侧壁的界面处。
在一些实施例中,替代材料可以是Si,并且钝化层材料可以是二氧化硅和氮化硅中的至少一种。在一些实施例中,替代材料可以是SiGe和锗(Ge)中的一种,并且钝化层材料可以是Si、氧化铝、氮化铝和钇中的至少一种。在一些实施例中,替代材料可以是至少一种III-V族材料并且钝化层材料可以是氧化铝、氧化铪和硫中的至少一种。在任何这样的实施例中,衬底可以是例如体硅衬底或一些其它合适的体衬底。在一些实施例中,最初沉积的钝化层材料被设计为在随后的氧化过程中消耗掉(或以其它方式被氧化),例如在用Si或钇钝化SiGe替代材料的情况下。在一些实施例中,钝化层材料旨在作为防止进一步氧化的保护层而是鲁棒的,例如在氧化铝、氧化铪、氧化铪硅、氧化镧、氧化镧铝、氧化锆、氧化锆硅、氧化钽、氧化钛、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化钇、氧化铝、氧化铅钪钽和铌酸铅锌用于钝化SiGe、Ge或III-V族替代材料的情况下。在一些实施例中,可以选择钝化层材料,使得界面陷阱密度(Dit)在沟道区中减小,具体而言,在晶体管沟道(晶体管沟道是替代材料与栅极接触的部分)下方减小。换言之,在一些实施例中,钝化层位于替代材料和STI侧壁的界面处。在这样的示例中,钝化层可以改善通过子鳍状物侧壁的源极-漏极(或漏极-源极)泄漏。在一些实施例中,可以选择钝化层材料来解决替代材料鳍状物的断键和/或杂质的问题。在一些实施例中,可以仅替代所形成的鳍状物的沟道区,并且可以使用本文中以不同方式描述的技术来仅钝化这样的沟道区。
在标准的ART流程中,通常没有机会在替代沟道材料和STI材料之间添加钝化材料。因此,本文以不同方式描述的技术通过在形成替代材料鳍状物之后(完全地或部分地)去除STI材料以允许钝化替代材料而提供了该机会。在没有钝化层/处理的情况下,使用ART处理和替代材料沟道区形成的晶体管可能具有高的源极-漏极(或漏极-源极)泄漏。这种泄漏会导致截止状态电流显著地高(例如,比在包括钝化材料层的结构中高至少三个数量级)。此外,如果不存在钝化剂/层/处理,则ART几何结构晶体管中的子鳍状物部分将具有与STI材料直接接触的半导体沟道区,从而导致不可接受的高截止状态漏电流。没有钝化材料层的结构中的这种泄漏由于高截止状态电流相对于导通状态电流没有提供足够的变化而可能导致不可行性或性能降低。
在分析(例如,使用扫描/透射电子显微镜法(SEM/TEM)、复合映射、二次离子质谱分析(SIMS)、原子探针成像、3D断层摄影等)时,根据一个或多个实施例配置的结构或器件将有效地示出如本文以不同方式描述的钝化层。例如,在一些情况下,钝化层可以位于替代沟道材料和浅沟槽隔离(STI)材料之间,根据本文所讨论的结构将是显而易见的。此外,在一些情况下,钝化层可以位于衬底和STI材料之间,并且在一些情况下,钝化层的部分可以夹在两个STI材料层之间,如下面将更详细描述的。另外,在一些情况下,钝化层可以位于使用本文描述的技术形成的晶体管的沟道区和源极/漏极区中。在其它情况下,钝化层可以仅位于使用本文描述的技术形成的晶体管的沟道区中。在一些情况下,可以通过观察由于源极-漏极(或漏极-源极)泄漏减少而获得的截止状态电流的改善来检测该技术,该源极-漏极(或漏极-源极)泄漏减少是包括本文以不同方式描述的钝化层的结果。根据本公开内容,许多构造和变型将是显而易见的。
架构和方法
图1示出了根据本公开内容的一个或多个实施例的形成集成电路的方法100。图2A-L示出了根据各个实施例在执行图1的方法100时形成的示例性集成电路结构。根据所形成的结构将显而易见,方法100公开了用于在晶体管的沟道区中形成钝化层的技术。钝化层可以提供许多益处,如本文以不同方式描述的。为便于说明,图2A-L的结构在本文中主要在形成鳍式晶体管构造(例如,FinFET或三栅极)的背景下示出和描述。然而,取决于最终用途或目标应用,可以使用这些技术来形成任何合适的几何结构或构造的晶体管。例如,图3A示出了包括纳米线构造的示例性集成电路结构,如将在下面更详细讨论的。可受益于本文所述技术的各种示例性晶体管几何结构包括但不限于场效应晶体管(FET)、金属氧化物半导体FET(MOSFET)、隧道FET(TFET)、平面构造、鳍式构造(例如,鳍式FET(fin-FET)、三栅极)和纳米线(或纳米带或环栅)构造。此外,该技术可用于形成CMOS晶体管/器件/电路,其中例如所包括的p-MOS晶体管和n-MOS晶体管中的任一者或两者可受益于本文以不同方式描述的钝化层。
如在图1可以看出,根据实施例,方法100包括在图案化102衬底200上的硬掩模210以形成图2A中所示的示例性所得结构。在一些实施例中,衬底200可以是:体衬底,包括例如Si、SiGe、Ge和/或至少一种III-V族材料;绝缘体上X(XOI)结构,其中X是Si、SiGe、Ge和/或至少一种III-V族材料,绝缘体材料是氧化物材料或电介质材料或一些其它电绝缘材料;或一些其它合适的多层结构,其中顶层包括Si、SiGe、Ge和/或至少一种III-V族材料。衬底200上的硬掩模210可以使用任何合适的技术来沉积。例如,硬掩模210可以使用化学气相沉积(CVD)、原子层沉积(ALD)、物理气相沉积(PVD)、旋涂处理和/或任何其它合适的工艺来均厚沉积或生长在衬底200上以在衬底200上形成硬掩模210。在一些情况下,可以在沉积硬掩模210之前处理(例如,化学处理、热处理等)待沉积的衬底200的表面。可以使用任何合适的技术来图案化102硬掩模210,例如一个或多个光刻和蚀刻工艺。硬掩模210可以由任何合适的材料组成,例如各种氧化物或氮化物材料。具体的氧化物和氮化物材料可以包括氧化硅、氧化钛、氧化铪、氧化铝或氮化钛,仅举几个示例。在一些情况下,可以基于所使用的衬底200材料来选择硬掩模210材料。
根据实施例,图1的方法100继续执行104浅沟槽凹陷(STR)蚀刻以从衬底200形成鳍状物202,由此形成图2B中所示的所得的示例性结构。例如,用于形成沟槽215和鳍状物202的STR蚀刻104可以包括任何合适的技术,例如各种掩模工艺和湿法和/或干法蚀刻工艺。在一些情况下,STR蚀刻104可以在原位/没有空气断路(air break)地执行,而在其它情况下,STR蚀刻104可以非原位执行。基于最终用途或目标应用,沟槽215可以形成为具有不同的宽度和深度。例如,可以执行多个硬掩模图案化102及蚀刻104工艺以实现STR沟槽215中不同的深度。鳍状物202可以形成为具有不同的宽度和高度。例如,在纵横比俘获(ART)集成方案中,鳍状物可以被形成为具有特定的高宽比,使得当它们稍后被去除或凹陷时,所形成的所得沟槽允许沉积的替代材料中的缺陷在材料垂直生长时在侧表面上终止,例如非晶态/电介质侧壁,其中侧壁相对于生长区域的尺寸足够高以便俘获大部分(如果不是全部)缺陷。在这样的示例情况下,鳍状物的高宽比(h/w)可以大于1,例如1.5至3。注意,为便于说明,在此示例性结构中,将沟槽215和鳍状物202示出为具有相同的宽度和深度/高度;然而,本公开内容并非旨在限制于此。还要注意的是,虽然在示例性结构中示出了四个鳍状物202,但是取决于最终用途或目标应用,可以形成任意数量的鳍状物,例如一个、两个、十个、几百个、几千个、几百万个等。
根据实施例,图1的方法100继续沉积106浅沟槽隔离(STI)材料220并平坦化以形成图2C所示的所得的示例性结构。在一些实施例中,STI材料220的沉积106可以包括本文描述的任何沉积工艺(例如,CVD、ALD、PVD等)或任何其它合适的沉积工艺。STI材料220可以包括任何合适的绝缘材料,例如一种或多种电介质、氧化物(例如,二氧化硅)或氮化物(例如,氮化硅)材料。在一些实施例中,可以基于衬底材料200来选择STI材料220。例如,在Si衬底200的情况下,STI材料220可以是二氧化硅或氮化硅。想到本文以不同方式描述的钝化技术包括第一STI材料沉积,去除或凹陷(例如,部分去除)第一STI材料,用钝化材料涂覆,然后沉积第二STI材料以再处理STI层。因此,在该示例性实施例中,沉积106是第一STI材料沉积,其将随后被去除或凹陷,如下面更详细讨论的。注意,尽管钝化技术包括第一和第二STI材料沉积,但是取决于具体构造,用于每个沉积的STI材料可以包括相同材料或不同材料。
根据实施例,图1的方法100继续蚀刻108鳍状物202以形成沟槽230,从而形成图2D中所示的所得的示例性结构。蚀刻108可以使用任何合适的技术来执行,例如各种掩模工艺和湿法和/或干法蚀刻工艺。在该示例性实施例中执行的蚀刻108导致鳍状物202的凹陷,使得具有高度H的鳍状物202(由衬底200形成并且由相同的原生材料构成)的底部的部分仍然存在于STI材料220之间。在一些实施例中,蚀刻108可以导致整个鳍状物202的去除,使得H为0,或者例如可以执行蚀刻108,使得其去除STI层220的底部下方的材料并进入衬底200。沟槽230可以用于沉积替代材料,如将在下面更详细讨论的。注意,在ART处理期间,沟槽230可以包括高纵横比开口,以俘获位错,例如防止位错到达外延膜表面,并且大大降低沟槽230内的表面位错密度。
根据实施例,图1的方法100继续在沟槽230中沉积110替代材料240并平坦化以形成图2E中所示的所得的示例性结构。在沉积110之后可以进行平坦化工艺以例如解决存在的凸出小面的问题。沉积110可以使用本文所述的任何沉积工艺(例如,CVD、ALD、LPE、PVD、MBE等)或任何其它合适的沉积工艺来执行。在一些情况下,沉积110可以在原位/没有空气断路地执行,而在其它情况下,沉积110可以非原位执行。在一些情况下,所使用的沉积110技术可以取决于所沉积的材料240。如在图2E的结构中可以看出,沉积110形成包括替代材料240的鳍状物。如下面将更详细讨论的,替代材料240鳍状物可以用于形成一个或多个晶体管,其中鳍状物240用于形成晶体管的沟道区,并且在一些情况下还用于形成晶体管的源极和漏极区。
在一些实施例中,替代材料240可以包括与衬底材料200不同的任何合适的半导体材料。例如,替代材料240可以是Si、SiGe、Ge和/或至少一种III-V族材料。在一些实施例中,衬底200可以是Si,并且替代材料240可以是SiGe、Ge和/或至少一种III-V族材料。例如,在替代材料240是Si1-xGex的实施例中,x可以在0.01到1的范围内(例如,0.2<x<0.8,提供示例性范围)。因此,在一些实施例中,替代材料可以是Ge本身或者作为SiGe材料的层(例如,如果SiGe以Ge含量增大的渐变方式沉积)。在另一个示例性实施例中,替代材料240可以是一种或多种III-V族材料。如本文中以不同方式使用的,示例性III-V族材料可以包括砷化镓(GaAs)、磷化铟(InP)、砷化铟(InAs)、砷化铟镓(InGaAs)、砷化铝(AlAs)或砷化铟铝(InAlAs)或任何其它合适的III-V族材料。在一些实施例中,如果替代材料240是一种或多种III-V族替代材料,则材料可以包括III-V族材料的单层或多层叠置体,例如InP/InGaAs/InAs、GaAs/InP/InAs、GaAs/InGaAs/InAs、GaAs/InAlAs/InAs、InP/InGaAs/InP、GaAs/InAs、GaAs/InGaAs或InP/InGaAs或者包括两种或更多种III-V族材料的任何其它合适的多层叠置体。在替代材料240是III-V族多层叠置体的一些这样的实施例中,可以在叠置体的底部附近使用高带隙III-V族材料(例如,以帮助减少到地的漏电流),例如GaAs、InP、InAlAs或AlAs。此外,在一些这样的实施例中,例如,III-V族多层叠置体可以在叠置体的顶部附近采用低带隙III-V族材料(例如,以帮助与叠置体接触),例如InAs或InGaAs。根据最终用途或目标应用,本文讨论的材料可以以任何合适的方式应变和/或掺杂。
根据实施例,图1的方法100继续蚀刻112STI材料220以形成沟槽250,由此形成图2F中所示的所得的示例性结构。例如,蚀刻112可以包括任何合适的技术,例如各种掩模工艺和湿法和/或干法蚀刻工艺。在一些情况下,蚀刻112可以在原位/没有空气断路地执行,而在其它情况下,蚀刻112可以非原位执行。在一些实施例中,蚀刻112可以完全去除沉积的第一STI材料220,如图2F的结构所示的示例性实施例的情况。在其它实施例中,例如,蚀刻112可以仅凹陷或部分地去除第一STI材料220,在沟槽250的底部处留下一部分材料,如将参考图2K'更详细地讨论的。
根据实施例,图1的方法100继续应用114钝化层260以形成图2G中所示的所得的示例性结构。应用114可以使用本文所述的任何沉积工艺(例如,CVD、ALD、LPE、PVD、MBE等)、热蒸发技术或任何其它合适的沉积工艺来执行。在一些情况下,应用114可以在原位/没有空气断路地执行,而在其它情况下,应用114可以非原位执行。在一些情况下,所使用的应用114技术可以取决于所沉积的材料260。注意,虽然应用114在本文中被描述为沉积钝化层260,但是应用114可以包括其它钝化技术和/或可替代地由其它钝化技术组成,例如将钝化剂或处理应用于图2F的结构。因此,尽管钝化层260在图2G的示例性实施例中被示出为不同的层,但是应用114(或所使用的特定钝化工艺)可以仅仅或者还可以在暴露出的层的表面处(例如,在替代材料鳍状物240和/或衬底200的表面处)引起物理和/或化学变化。换言之,例如,钝化层260可以被检测为替代材料鳍状物240的外壁的部分,而不是如图2G中所示的不同层。然而,在图2G中,钝化层260被示出为单层,并且这样的单层可以在整个层中包括相同的材料,或者在整个层中具有从第一浓度到第二浓度渐变的一种或多种组分。还要注意的是,虽然钝化层260被示出为单层,但取决于最终用途或目标应用,钝化应用114可以包括多个钝化层260。
根据实施例,图1的方法100继续沉积116第二STI材料222并平坦化,以形成图2H所示的所得的示例性结构。可以看出,第二STI材料填充在沉积钝化层260之后仍然存在的沟槽250的部分。可以使用本文所述的任何沉积工艺(例如,CVD、ALD、PVD、旋涂处理等)或任何其它合适的沉积工艺来执行沉积116。在一些情况下,沉积116可以在原位/没有空气断路地执行,而在其它情况下,沉积116可以非原位执行。想到虽然将STI材料222称为第二STI材料,但是其可以包括与第一STI材料220相同的材料。因此,第一和第二标示旨在表示它们在方法100期间沉积的顺序。因此,如果第二STI材料222与第一STI材料220相同,则STI材料可以被再沉积116。然而,在一些实施例中,第一STI材料220和第二STI材料222可以是不同的。同样如在图2H中可以看到的,在平坦化工艺之后,替代材料240鳍状物的至少一个表面可以被暴露出(例如,在该示例性情况下的顶面),并且钝化层260位于替代材料鳍状物240的至少部分与第二STI材料222之间。还要注意,钝化层260位于衬底200与第二STI材料222之间。
在一些实施例中,取决于最终用途或目标应用,钝化层260可以具有任意的或期望的厚度,例如1-10nm的厚度,或者一些其它合适的厚度。在一些实施例中,钝化层260可以被沉积为具有基本共形的生长图案。例如,这样基本共形的生长图案可以包括钝化层260在替代材料鳍状物240和第二STI材料222之间的部分的厚度可以与钝化层在衬底200和第二STI材料222之间的部分的厚度基本相同(例如,在1或2nm的公差内)。
在一些实施例中,钝化层260可以包括与第二STI材料222不同的任何合适的材料。在一些实施例中,可以基于所使用的第二STI材料222来选择所使用的钝化层260材料。在一些实施例中,可以基于在工艺110期间沉积的替代材料240来选择钝化层260。例如,钝化层260可以被选择为使得界面陷阱密度(Dit)在使用本文所述的技术形成的所得晶体管的子沟道(或者子鳍状物)区域中减小。在这样的示例中,钝化层可以改善通过沟道区中的,具体而言,在晶体管沟道(晶体管沟道是替代材料与栅极接触的部分)下方的子鳍状物侧壁的源极-漏极(或漏极-源极)泄漏。换言之,在一些实施例中,钝化层位于替代材料和STI侧壁的界面处。因此,可以选择钝化层260材料以解决替代材料鳍状物240的断键和/或杂质的问题。在替代材料240是Si的实施例中,钝化材料260可以包括氮化硅和/或二氧化硅。在替代材料240是SiGe或Ge的实施例中,钝化材料260可以包括Si、氧化铝、氮化铝和/或钇。在替代材料240是一种或多种III-V族材料的实施例中,钝化材料260可以包括氧化铝、氧化铪和/或硫(例如,InGaAs替代材料和硫钝化材料)。根据本公开内容,许多其它替代材料240和钝化材料260组合将是显而易见的。在一些实施例中,最初沉积的钝化层材料260被设计为在随后的氧化过程中消耗掉(或以其它方式被氧化),例如在SiGe替代材料上施加Si或钇的情况下。在一些实施例中,钝化层材料260旨在作为防止进一步氧化的保护层而是鲁棒的,例如在用于III-V族替代材料的氧化铝或氧化铪(或具有高介电常数K的其它合适的材料)的情况下。
根据实施例,图1的方法100可选地继续蚀刻118STI材料222和钝化层260,以形成图2I中所示的所得的示例性结构。例如,蚀刻118可以使用任何合适的技术来执行,例如各种掩模工艺和湿法和/或干法蚀刻工艺。在一些情况下,蚀刻118可以在原位/没有空气断路地执行,而在其它情况下,蚀刻118可以非原位执行。在该示例性实施例中,蚀刻118去除第二STI材料222和钝化层260,使得替代材料鳍状物240从平面突出,例如其可以被执行用于制造具有非平面构造(例如,鳍式或纳米线/纳米带构造)的晶体管。注意,尽管在替代材料鳍状物240和钝化层260之间存在重叠,但是这种重叠可以比所示出的量更大或更小。此外,在一些情况下,可以不存在重叠,使得钝化层260和第二STI材料222被蚀刻/凹陷118到低于位于鳍状物的原生材料部分与替代材料部分之间的Y界面的水平。在制造具有平面构造的晶体管的情况下,可以不执行刻蚀118,并且可以使用图2H所示的结构作为形成一个或多个晶体管的集成电路结构。
根据一些实施例,图1的方法100继续完成120一个或多个晶体管的形成以形成图2J-L的示例性所得结构。可以执行各种不同的工艺以完成使用图2H的集成电路结构(例如,用于平面晶体管构造)和2I的集成电路结构(例如,用于非平面晶体管构造)形成一个或多个晶体管。根据实施例,从图2I的结构继续,一些这样的过程可以包括在替代材料鳍状物240上形成栅极叠置体270,以形成图2J所示的所得的示例性结构。在一些实施例中,栅极叠置体270的形成可以包括虚设栅极氧化物沉积,虚设栅电极(例如,多晶硅)沉积以及图案化硬掩模沉积。另外的处理可以包括图案化虚设栅极和沉积/蚀刻间隔物材料。在这样的过程之后,该方法可以继续进行绝缘体沉积、平坦化,然后去除虚设栅电极和栅极氧化物以暴露出晶体管的沟道区,例如针对取代金属栅极(RMG)工艺所做的。在打开沟道区之后,可以分别用例如高k电介质和替代金属栅极来替代虚设栅极氧化物和电极。其它实施例可以包括通过任何合适的工艺形成的标准栅极叠置体。还可以执行任意数量的标准后端工艺来帮助完成120一个或多个晶体管的形成。
在图2K所示的示例性结构中,栅极叠置体270包括栅电极272和形成在栅电极272正下方的栅极电介质(为了便于说明而未示出)。栅极电介质和栅电极可以使用任何合适的技术并且由任何合适的材料形成。例如,栅极叠置体可以如前所述在替代金属栅极工艺期间形成,并且这样的工艺可以包括任何合适的沉积技术(例如,CVD、PVD等)。栅极电介质可以是例如任何合适的氧化物,例如二氧化硅或高k栅极电介质材料。高k栅极电介质材料的示例包括例如氧化铪、氧化铪硅、氧化镧、氧化镧铝、氧化锆、氧化锆硅、氧化钽、氧化钛、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化钇、氧化铝、氧化铅钪钽、铌酸铅锌。在一些实施例中,当使用高k材料时,可以在栅极电介质层上执行退火工艺以提高其质量。通常,栅极电介质的厚度应该足以将栅电极与源极和漏极接触部电隔离。此外,栅电极272可以包括宽范围的材料,例如多晶硅、氮化硅、碳化硅或各种合适的金属或金属合金,例如铝(Al)、钨(W)、钛(Ti)、钽(Ta)、铜(Cu)、氮化钛(TiN)或氮化钽(TaN)。还可以看出,间隔物274可以形成为例如在后续处理期间保护栅极叠置体。硬掩模276也可以形成为保护栅极叠置体免受后续处理的影响。
可以使用栅极叠置体270来限定随后形成的晶体管的沟道区以及源极区和漏极区,其中沟道区位于栅极叠置体下方,并且源极/漏极(S/D)区位于沟道区的两侧上(即,S/D区与沟道区相邻)。例如,图2J中的栅极叠置体270下方的鳍状物240的部分可以用于晶体管沟道区,而栅极叠置体270的两侧上被示为242和244的鳍状物的部分可以用于晶体管S/D区。注意,基于所得的构造,242可以用于源极区或漏极区,244可以用于另一区域。因此,一旦制造了栅极叠置体,就可以处理S/D区242和244。如通常那样(例如,离子注入,或者蚀刻和沉积以及原位掺杂,或者任何其它合适的源极/漏极形成工艺),在栅极叠置体的两侧上的鳍状物区域中形成鳍状物的S/D区242和244。可以使用例如硅化工艺(通常是接触部金属的沉积和随后的退火)在那些源极/漏极区上形成接触部。典型的S/D区材料包括例如Si、SiGe、Ge和/或III-V族化合物,仅举几个示例性材料,其可根据需要掺杂以提供期望的极性。示例性源极漏极接触部材料包括例如钨、钛、银、金、铝、铜、钴及其合金。
提供图2K'以示出根据实施例的在蚀刻112期间未完全去除第一STI材料220情况下的可替代示例性结构。如前所述,在一些情况下,蚀刻112可以是部分蚀刻,其在STR沟槽中留下一些第一STI材料220。在这样的示例性情况下,钝化层260'沉积在STR沟槽中的凹陷的第一STI材料220上,而不是直接沉积在衬底200上(例如,比较图2K'的结构与图2K的结构)。注意,钝化层260'与如本文以不同方式描述的钝化层260类似,除了钝化层260'被沉积在包括第一STI材料220的结构上之外,如刚才所述的。可以取决于最终用途或目标应用根据需要而使用保留第一STI材料220的部分并在第一STI材料220和第二STI材料222之间形成钝化层260'作为夹层结构的这种示例性结构。
提供图2L以示出根据示例性实施例的在栅极下方的沟道区246之一。如在图2L的示例性结构中可以看出,在沟道区246中保持最初的鳍式构造。然而,图2L的结构也可以通过在替代栅极工艺(例如,RMG工艺)期间用鳍式结构替代沟道区来实现。在这种也被称为三栅极和鳍式FET构造的鳍式构造中,如本领域中已知的,存在三个有效栅极:两个在两侧上,一个在顶部。如在图2L中还可以看出,沟道区包括具有与栅极接触的侧面的第一部分(在该示例性情况下为上部部分)和具有与钝化层260接触的侧面的第二部分。第二部分有时被称为子鳍状物部分,并且这个部分通常与STI材料接触。然而,由于本文描述的钝化技术,钝化层260被包括在该子鳍状物部分的两侧上,提供本文以不同方式描述的益处(例如,减少界面陷阱的密度,减少源极-漏极泄漏等)。
根据本公开内容将显而易见的是,取决于那些区域中的材料和期望的最终用途或目标应用,可以在沟道和/或S/D区中执行合适的掺杂。例如,包括Si或至少一种III-V族材料的沟道区可以是p型掺杂的(例如,以形成n-MOS晶体管),并且包括SiGe和/或Ge的沟道区可以是n型掺杂的(例如,以形成p-MOS晶体管)。在一些实施例中,例如,可以组合n-MOS和p-MOS晶体管以形成CMOS器件。如本文以不同方式描述的,掺杂可以使用任何合适的技术和掺杂剂来执行,这取决于例如掺杂的材料、期望的n型或p型掺杂结果、和/或目标应用。根据本公开内容,许多不同的掺杂方案是显而易见的。注意,为了便于描述,方法100的过程102-120在图1中以特定顺序示出。然而,过程102-120中的一个或多个可以以不同的顺序执行,或者可以根本不执行。例如,框118是可选的过程,如果所得的期望的晶体管架构是平面的,则可以不执行该过程。根据本公开内容,方法100的许多变型将是显而易见的。
图3A-C示出了根据一些实施例的使用图1的方法100形成的图2L的结构的变型。具体而言,提供图3A以示出包括具有纳米线构造的晶体管的集成电路结构。可以看出,图2L的结构中最前面(或最右侧)的鳍状物的沟道区形成为两个纳米线346。纳米线晶体管(有时被称为环栅或纳米带晶体管)类似地配置为基于鳍状物的晶体管,但是代替栅极位于三侧(因此存在三个有效栅极)上的鳍式沟道区,而使用一个或多个纳米线,并且栅极材料通常在所有侧上围绕每个纳米线。取决于具体的设计,一些纳米线晶体管具有例如四个有效栅极。如在图3A的示例性结构中可以看出,每个沟道区具有两个纳米线346,但是其它实施例可以具有任何数量的纳米线。例如,在去除虚设栅极之后,在替代栅极工艺(例如,RMG工艺)期间可以形成纳米线346,同时暴露出沟道区。如在图3B的示例性结构中还可以看出,碳基界面区域240位于沟道区404和S/D区252之间。注意,取决于最终用途或目标应用,晶体管构造的任何组合可以用于单个集成电路,包括平面、双栅极、鳍式(或三栅极或FinFET)、纳米线(或纳米带或环栅),和/或任何其它合适的晶体管构造。
提供图3B以示出根据一些实施例的图2L的集成电路结构中的另外的变型。如在图3B中可以看出,只有最右侧的鳍状物的沟道部分被替代材料240替代,产生与图2L中所示的相同的沟道区246,其中S/D区342和344包括原生衬底材料(并如图所示从衬底延伸)。本文以不同方式描述的钝化层260的益处仍然可以在这样的构造中实现,因为使用钝化层260来钝化晶体管沟道区中的替代材料,这仍是沟道区246的情况。类似地,第二最左侧的鳍状物示出S/D区可以被替代/外延生长(形成S/D区442和444),但仍然可以实现本文以不同方式描述的钝化层260的益处,因为钝化层260仍然为对应的替代沟道区446提供钝化。提供图3C以示出根据一些实施例的在替代栅极工艺期间仅在沟道区中执行钝化技术的示例性集成电路结构。如在这种示例情况下最右侧的鳍状物中可以看到的,钝化层260仅位于沟道区246中,因为其在沉积替代栅极之前仅被沉积在该区域中。相应地,鳍状物的S/D区342和344包括原生衬底材料(并如图所示从衬底延伸)。而且,仅在沟道区中替代第一STI材料220,留下围绕S/D区的第一STI材料。在此示例性结构中,可以替代/外延生长一个或多个S/D区,如第二最左侧的鳍状物S/D区442和444。本文以不同方式描述的钝化技术可适用于许多不同的构造,例如使用具有替代沟道区的ART工艺形成的晶体管。根据本公开内容,许多变型和构造将是显而易见的。
示例性系统
图4示出了根据示例性实施例的借助于使用本文公开的技术形成的集成电路结构或器件实现的计算系统1000。如可见的,计算系统1000容纳母板1002。母板1002可以包括多个部件,包括但不限于,处理器1004和至少一个通信芯片1006,其中的每一个都可以物理且电耦合到母板1002,或以其它方式集成在其中。可以理解的是,母板1002可以是例如任何印刷电路板,无论是主板、安装在主板上的子板,还是系统1000唯一的板等。
取决于其应用,计算系统1000可以包括一个或多个其它部件,其可以或可以不物理且电耦合到母板1002。这些其它部件可以包括但不限于,易失性存储器(例如,DRAM)、非易失性存储器(例如,ROM)、图形处理器、数字信号处理器、密码处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编码解码器、视频编码解码器、功率放大器、全球定位系统(GPS)设备、指南针、加速度计、陀螺仪、扬声器、相机和大容量储存设备(例如,硬盘驱动器、光盘(CD)、数字多用途盘(DVD)等等)。包括在计算系统1000中的任何部件可以包括使用根据示例性实施例的所公开的技术形成的一个或多个集成电路结构或器件。在一些实施例中,可以将多个功能集成到一个或多个芯片中(例如,注意通信芯片1006可以是处理器1004的一部分或以其它方式集成到处理器1004中)。
通信芯片1006实现了无线通信,用于向计算系统1000传送数据并传送来自计算系统1000的数据。术语“无线”及其派生词可以用于描述可以通过使用经过非固态介质的经调制电磁辐射来传输数据的电路、设备、系统、方法、技术、通信信道等。该术语并非暗示相关联的设备不包含任何引线,尽管在一些实施例中它们可以不包含。通信芯片1006可以实施多个无线标准或协议中的任意一个,包括但不限于,Wi-Fi(IEEE 802.11族)、WiMAX(IEEE802.16族)、IEEE 802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、其派生物,以及被指定为3G、4G、5G及更高的任何其它无线协议。计算系统1000可以包括多个通信芯片1006。例如,第一通信芯片1006可以专用于近距离无线通信,例如Wi-Fi和蓝牙,第二通信芯片1006可以专用于远距离无线通信,例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等。
计算系统1000的处理器1004包括封装在处理器1004内的集成电路管芯。在一些实施例中,处理器的集成电路管芯包括借助于使用所公开的技术形成的一个或多个集成电路结构或器件实现的板载电路,如本文不同地描述的。术语“处理器”可以指代任何设备或设备的部分,其处理来自寄存器和/或存储器的电子数据,将该电子数据转变为可以存储在寄存器和/或存储器中的其它电子数据。
通信芯片1006还可以包括被封装在通信芯片1006内的集成电路管芯。根据一些这样的示例性实施例,通信芯片的集成电路管芯包括使用所公开的技术形成的一个或多个集成电路结构或器件,如本文不同地描述的。如根据本公开内容将理解的,注意,多标准无线能力可以直接集成到处理器1004中(例如,其中任何芯片1006的功能被集成到处理器1004中而不是具有单独的通信芯片)。另外注意,处理器1004可以是具有这种无线能力的芯片组。简言之,可以使用任何数量的处理器1004和/或通信芯片1006。同样,任何一个芯片或芯片组都可以具有集成在其中的多个功能。
在各个实施方式中,计算设备1000可以是膝上型电脑、上网本电脑、笔记本电脑、超级本电脑、智能电话、平板电脑、个人数字助理(PDA)、超移动PC、移动电话、台式计算机、服务器、打印机、扫描器、监视器、机顶盒、娱乐控制单元、数码相机、便携式音乐播放器、或数码摄像机或处理数据或采用使用所公开的技术形成的一个或多个集成电路结构或晶体管器件的任何其它电子设备,如本文不同地描述的。
其它示例性实施例
以下示例涉及其它实施例,根据其许多变换和构造将是显而易见的。
示例1是一种集成电路,包括:由衬底材料构成的衬底;由不同于衬底材料的替代材料构成的晶体管沟道区,该沟道区位于衬底的部分上且位于栅极下方,其中,沟道区包括具有与栅极接触的一个或多个侧面的第一部分和具有不与栅极接触的一个或多个侧面的第二部分;以及由钝化材料构成并且位于沟道区的第二部分和浅沟槽隔离(STI)材料之间的层,其中,钝化材料不同于STI材料。
示例2包括示例1的主题,其中,所述钝化材料层降低沟道区中的界面陷阱的密度。
示例3包括示例1-2中任一项的主题,其中,所述衬底是体硅衬底。
示例4包括示例1-2中任一项的主题,其中,所述替代材料是硅,并且所述钝化材料是二氧化硅和氮化硅中的至少一种。
示例5包括示例1-3中任一项的主题,其中,所述替代材料是硅锗和锗中的一种,并且所述钝化材料是硅、氧化铝、氮化铝和钇中的至少一种。
示例6包括示例1-3中任一项的主题,其中,所述替代材料包括至少一种III-V族材料,并且所述钝化材料是以下各项中的至少一种:氧化铝、氧化铪、硫、氧化铪硅、氧化镧、氧化镧铝、氧化锆、氧化锆硅、氧化钽、氧化钛、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化钇、氧化铝、氧化铅钪钽和铌酸铅锌。
示例7包括示例1-6中任一项的主题,其中,所述钝化材料层具有1-10nm的厚度。
示例8包括示例1-7中任一项的主题,还包括与沟道区相邻的源极和漏极(S/D)区,S/D区由所述衬底材料构成。
示例9包括示例1-7中任一项的主题,还包括与沟道区相邻的源极和漏极(S/D)区,S/D区由所述替代材料构成。
示例10包括示例8-9中任一项的主题,其中,所述钝化材料层位于S/D区和所述STI材料之间。
示例11包括示例1-10中任一项的主题,其中,所述钝化材料层位于所述STI材料与所述衬底的至少部分之间。
示例12包括示例1-11中任一项的主题,其中,所述STI材料是氧化物、氮化物和电介质材料中的至少一种。
示例13包括示例1-12中任一项的主题,其中,晶体管几何结构包括以下各项中的中的至少一种:场效应晶体管(FET)、金属氧化物半导体FET(MOSFET)、隧道FET(TFET)、平面构造、鳍式构造、鳍式FET构造、三栅极构造、纳米线构造和纳米带构造。
示例14是包括示例1-13中任一项的主题的互补金属氧化物半导体(CMOS)器件。
示例15是包括示例1-14中任一项的主题的计算系统。
示例16是一种晶体管,包括:由衬底材料构成的衬底;由不同于所述衬底材料的替代材料构成的沟道区,沟道区位于衬底的部分上且位于栅极下方,其中,沟道区包括具有与栅极接触的一个或多个侧面的第一部分和具有不与栅极接触的一个或多个侧面的第二部分;与沟道区相邻的源极和漏极(S/D)区;以及由钝化材料构成并且位于沟道区的第二部分和浅沟槽隔离(STI)材料之间的钝化层,所述钝化层还位于所述STI材料与所述衬底的至少部分之间,并且还位于S/D区和STI材料之间,其中,钝化材料不同于STI材料。
示例17包括示例16的主题,其中,所述钝化材料层降低沟道区中的界面陷阱的密度。
示例18包括示例16-17中任一项的主题,其中,所述衬底是体硅衬底。
示例19包括示例16-17中任一项的主题,其中,所述替代材料是硅,并且所述钝化材料是二氧化硅和氮化硅中的至少一种。
示例20包括示例16-18中任一项的主题,其中,所述替代材料是硅锗和锗中的一种,并且所述钝化材料是硅、氧化铝、氮化铝和钇中的至少一种。
示例21包括示例16-18中任一项的主题,其中,所述替代材料包括至少一种III-V族材料,并且所述钝化材料是以下各项中的至少一种:氧化铝、氧化铪、硫、氧化铪硅、氧化镧、氧化镧铝、氧化锆、氧化锆硅、氧化钽、氧化钛、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化钇、氧化铝、氧化铅钪钽和铌酸铅锌。
示例22包括示例16-21中任一项的主题,其中,所述钝化材料层具有1-10nm的厚度。
示例23包括示例16-22中任一项的主题,其中,S/D区由所述衬底材料构成。
示例24包括示例16-22中任一项的主题,其中,S/D区由所述替代材料构成。
示例25包括示例16-24中任一项的主题,其中,所述STI材料是氧化物、氮化物和电介质材料中的至少一种。
示例26包括示例16-25中任一项的主题,其中,晶体管几何结构包括以下各项中的至少一种:场效应晶体管(FET)、金属氧化物半导体FET(MOSFET)、隧道FET(TFET)、平面构造、鳍式构造、鳍式FET构造、三栅极构造、纳米线构造和纳米带构造。
示例27是包括示例16-26中任一项的主题的互补金属氧化物半导体(CMOS)器件。
示例28是包括示例16-27中任一项的主题的计算系统。
示例29是一种形成集成电路的方法,所述方法包括:在衬底中形成鳍状物,所述衬底由衬底材料构成;在鳍状物的两侧上沉积浅沟槽隔离(STI)材料;执行第一蚀刻以至少部分地去除所述鳍状物并形成沟槽;在沟槽中沉积替代材料以形成替代鳍状物,替代材料不同于衬底材料;执行第二蚀刻以至少部分地去除所述STI材料以暴露出所述替代鳍状物;将由钝化材料构成的钝化层应用于暴露出的替代鳍状物;以及在钝化层上沉积和平坦化附加STI材料,其中,钝化材料不同于第二STI材料。
示例30包括示例29的主题,其中,第二蚀刻完全去除STI材料。
示例31包括示例29的主题,其中,第二蚀刻部分地去除STI材料。
示例32包括示例29-31中任一项的主题,其中,应用钝化层包括沉积钝化材料,使得钝化层具有1-10nm的厚度。
示例33包括示例29-32中任一项的主题,其中,应用钝化材料包括处理替代材料的至少部分的一个或多个表面以化学和/或物理地改变所述一个或多个表面。
示例34包括示例29-33中任一项的主题,还包括形成晶体管,所述晶体管包括由所述替代材料形成的沟道区。
示例35包括示例29-34中任一项的主题,其中,STI材料和附加STI材料是相同的材料。
示例36包括示例29-35中任一项的主题,其中,在替代栅极工艺期间,仅在集成电路上形成的晶体管的沟道区中执行沉积替代材料和应用钝化层。
已经出于示例和描述的目的给出了对示例性实施例的上述描述。这并非旨在是穷尽性的或将本公开内容限制于所公开的准确形式。鉴于本公开内容,许多修改和变型是可能的。旨在本公开内容的范围并非由具体实施方式限定,而是由所附权利要求书限定。要求本申请优先权的未来提交的申请可以以不同的方式要求保护所公开的主题,并且一般可以包括在本文不同地公开的或以其它方式说明的一个或多个限制的任何集合。
Claims (24)
1.一种包括至少一个晶体管的集成电路,所述集成电路包括:
衬底;
包括不同于所述衬底的材料的主体,所述主体位于所述衬底的部分上并且位于栅极结构下方,其中,所述主体包括位于所述栅极结构的部分之间的第一部分;
位于所述衬底之上的第一区域和第二区域,所述主体的第二部分位于所述第一区域与所述第二区域之间,其中,所述第一区域和所述第二区域包括第一电介质材料;以及
位于所述主体的所述第二部分与所述第一区域之间的层,所述层还位于所述主体的所述第二部分与所述第二区域之间,其中,所述层包括不同于所述第一电介质材料的第二电介质材料,
其中,所述层不与所述主体的所述第一部分接触,所述第一区域和所述第二区域的面向所述栅极结构的第一表面以及所述第一区域和所述第二区域的相对的第二表面都包括所述第一电介质材料,所述层的部分位于所述衬底与所述第一区域和所述第二区域之间并且与所述第一区域和所述第二区域直接接触。
2.根据权利要求1所述的集成电路,其中,所述层降低所述主体中的界面陷阱的密度。
3.根据权利要求1所述的集成电路,其中,所述衬底是体硅衬底。
4.根据权利要求1所述的集成电路,其中,所述主体包括硅,并且所述第二电介质材料包括硅。
5.根据权利要求1所述的集成电路,其中,所述主体包括锗,并且所述第二电介质材料包括硅、铝或钇中的一种或多种。
6.根据权利要求1所述的集成电路,其中,所述主体包括至少一种III-V族半导体材料,并且所述第二电介质材料包括以下中的一种或多种:铝、铪、硫、硅、镧、锆、钽、钛、钡、锶、钇、铅、钪、锌或铌。
7.根据权利要求1所述的集成电路,其中,所述层具有1-10纳米的厚度。
8.根据权利要求1所述的集成电路,还包括源极区和漏极区,所述主体的所述第一部分位于所述源极区与所述漏极区之间,其中,所述源极区和所述漏极区原生于所述衬底。
9.根据权利要求1所述的集成电路,还包括源极区和漏极区,所述主体的所述第一部分位于所述源极区与所述漏极区之间,其中,所述源极区和所述漏极区包括所述主体中所包含的半导体材料。
10.根据权利要求9所述的集成电路,其中,所述层还位于:所述源极区与所述第一区域之间,所述源极区与所述第二区域之间,所述漏极区与所述第一区域之间,以及所述漏极区与所述第二区域之间。
11.根据权利要求1所述的集成电路,其中,所述层位于所述衬底的所述部分与所述第一区域之间,并且所述层还位于所述衬底的所述部分与所述第二区域之间。
12.根据权利要求1所述的集成电路,其中,所述第一电介质材料包括氧或氮中的一种或两种。
13.根据权利要求1所述的集成电路,其中,所述主体的所述第一部分为鳍状物。
14.一种包括权利要求1所述的集成电路的互补金属氧化物半导体(CMOS)电路。
15.一种包括权利要求1所述的集成电路的计算系统。
16.一种包括至少一个晶体管的集成电路,所述集成电路包括:
衬底;
包括不同于所述衬底的材料的第一主体,所述第一主体位于所述衬底的部分上并且位于栅极结构之下;
位于所述第一主体与所述栅极结构之间的第二主体,所述栅极结构围绕所述第二主体;
位于所述衬底之上的第一区域和第二区域,所述第一主体位于所述第一区域与所述第二区域之间,其中,所述第一区域和所述第二区域包括第一电介质材料;以及
位于所述第一主体与所述第一区域之间的层,所述层还位于所述第一主体与所述第二区域之间,其中,所述层包括不同于所述第一电介质材料的第二电介质材料,
其中,所述层不与所述第二主体接触,所述第一区域和所述第二区域的面向所述栅极结构的第一表面以及所述第一区域和所述第二区域的相对的第二表面都包括所述第一电介质材料,所述层的部分位于所述衬底与所述第一区域和所述第二区域之间并且与所述第一区域和所述第二区域直接接触。
17.根据权利要求16所述的集成电路,其中,所述第一主体包括锗,并且所述层包括硅、铝或钇中的一种或多种。
18.根据权利要求16所述的集成电路,其中,所述第一主体包括至少一种III-V族半导体材料,并且所述层包括以下中的一种或多种:铝、铪、硫、硅、镧、锆、钽、钛、钡、锶、钇、铅、钪、锌或铌。
19.根据权利要求16所述的集成电路,其中,所述第二主体为纳米线或纳米带。
20.一种形成集成电路的方法,所述方法包括:
在衬底中形成鳍状物,所述衬底由衬底材料构成;
在所述鳍状物的两侧上沉积浅沟槽隔离(STI)材料;
执行第一蚀刻以至少部分地去除所述鳍状物并形成沟槽;
在所述沟槽中沉积替代材料以形成替代鳍状物,所述替代材料不同于所述衬底材料;
执行第二蚀刻以去除所述浅沟槽隔离材料以暴露出所述替代鳍状物;
将由钝化材料构成的钝化层应用于暴露出的替代鳍状物;以及
在所述钝化层上沉积并平坦化附加浅沟槽隔离材料,其中,所述钝化材料不同于所述浅沟槽隔离材料,
其中,所述钝化层的部分与所述衬底直接接触。
21.根据权利要求20所述的方法,其中,应用所述钝化层包括沉积所述钝化材料,使得所述钝化层具有1-10nm的厚度。
22.根据权利要求20所述的方法,其中,应用所述钝化材料包括处理所述替代材料的至少部分的一个或多个表面以化学和/或物理地改变所述一个或多个表面。
23.根据权利要求20-22中任一项所述的方法,还包括形成晶体管,所述晶体管包括由所述替代材料形成的沟道区。
24.一种包括至少一个晶体管的集成电路,所述集成电路包括:
衬底;
包括不同于所述衬底的材料的主体,所述主体位于所述衬底的部分上方并且位于栅极结构下方,其中,所述主体的部分位于所述栅极结构的部分之间;
位于所述衬底之上的第一区域和第二区域,所述第一区域和所述第二区域包括第一电介质材料;以及
位于所述衬底的所述部分与所述第一区域之间的层,所述层还位于所述衬底的所述部分与所述第二区域之间,其中,所述层包括不同于所述第一电介质材料的第二电介质材料,
其中,所述层不与所述主体接触,所述第一区域和所述第二区域的面向所述栅极结构的第一表面以及所述第一区域和所述第二区域的相对的第二表面都包括所述第一电介质材料,所述层的部分位于所述衬底与所述第一区域和所述第二区域之间并且与所述第一区域和所述第二区域直接接触。
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