JP5670681B2 - 3次元半導体メモリ装置及びその製造方法 - Google Patents
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
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Description
図1〜図6は、本発明の技術的思想に基づいた第1実施形態に係る3次元半導体装置の製造方法を示す斜視図である。
図8〜図14は、本発明の技術的思想に基づいた第2実施形態に係る3次元半導体装置の製造方法を示す斜視図である。説明の便宜のために、図1〜図7を参照して説明した本発明の第1実施形態と重複する内容は省略可能である。
図16〜図20は、本発明の第1及び第2実施形態から変形される実施形態を例示的に説明するための断面図である。説明の便宜のために、図1〜図15を参照して説明した実施形態と重複される技術的特徴に対する説明は省略する。また、別途に説明されない図16〜図20に示した構成要素は、同一の参照番号が与えられる上述の第1及び第2実施形態の構成要素と同一の方法を通じて形成され得る。
図25〜図31は、本発明の技術的思想に基づいた第3実施形態に係る半導体装置の製造方法を説明するための断面図である。説明の便宜のために、上述の実施形態と重複される技術的特徴に対する説明は省略する。
図32〜図34は、上述の第3実施形態の変形例に係る半導体装置を説明するための斜視図である。具体的に、図32及び図33は2つの異なる方向から見た第3実施形態に係る半導体装置の斜視図であり、図34は、この装置でのワードライン配置を説明するための斜視図である。
50 下部導電パターン
100 下部薄膜構造体
120 下部絶縁膜
130 下部犠牲膜
140 下部貫通ホール
150 半導体パターン
Claims (16)
- 3次元半導体装置の製造方法において、
前記3次元半導体装置は積層された導電パターン、前記導電パターンを貫通する活性パターン及び前記導電パターンと前記活性パターンとの間に介在される情報貯蔵膜を含む少なくとも1つのメモリ構造体を含み、前記活性パターンは積層された下部及び上部貫通ホールを各々満たす下部及び上部半導体パターンを含み、
1つのメモリ構造体を構成する前記情報貯蔵膜は同一の工程段階を利用して同時に形成され、1つのメモリ構造体を構成する前記下部及び上部貫通ホールは互いに異なる工程段階を利用して順に形成され、
前記活性パターンを形成する段階は、
下部薄膜構造体を形成する段階と、
前記下部薄膜構造体を貫通する前記下部貫通ホールを形成する段階と、
前記下部貫通ホールを満たす前記下部半導体パターンを形成する段階と、
前記下部半導体パターン上に上部薄膜構造体を形成する段階と、
前記上部薄膜構造体を貫通して前記下部半導体パターンを露出させる前記上部貫通ホールを形成する段階と、
前記上部貫通ホールを満たす前記上部半導体パターンを形成する段階とを含む
ことを特徴とする3次元半導体装置の製造方法。 - 前記上部半導体パターンを形成する前に、前記下部半導体パターンの上部に中間導電パターンを形成する段階をさらに含む
ことを特徴とする請求項1に記載の3次元半導体装置の製造方法。 - 前記導電パターン及び前記情報貯蔵膜を形成する段階は、
交互に、且つ繰り返して積層された下部絶縁膜及び下部犠牲膜を含む下部薄膜構造体を形成する段階と、
交互に、且つ繰り返して積層された上部絶縁膜及び上部犠牲膜を含む上部薄膜構造体を形成する段階と、
前記上部及び下部犠牲膜を同時に除去し、前記下部絶縁膜の間及び前記上部絶縁膜の間に各々下部リセス領域及び上部リセス領域を形成する段階と、
前記上部及び下部リセス領域の各々を満たす情報貯蔵膜及び導電パターンを形成する段階とを含む
ことを特徴とする請求項1に記載の3次元半導体装置の製造方法。 - 前記下部及び上部リセス領域を形成する前に、前記活性パターンから離隔されて前記下部及び上部薄膜構造体の全部を貫通するトレンチを形成する段階をさらに含み、
前記トレンチは一回のパターニング段階を利用して形成される
ことを特徴とする請求項3に記載の3次元半導体装置の製造方法。 - 前記上部薄膜構造体を形成する前に、前記下部薄膜構造体を貫通する下部分離パターンを形成する段階と、
前記下部及び上部リセス領域を形成する前に、前記下部分離パターンの上部面を露出させる上部分離領域を形成する段階と、
前記下部及び上部リセス領域を形成する前に、前記露出した下部分離パターンを除去する段階と、をさらに含む
ことを特徴とする請求項3に記載の3次元半導体装置の製造方法。 - 前記少なくとも1つのメモリ構造体は順に積層された複数のメモリ構造体を含み、
前記積層されたメモリ構造体を形成する段階は前記メモリ構造体を形成する段階を繰り返して実施する過程を含む
ことを特徴とする請求項1に記載の3次元半導体装置の製造方法。 - 交互に、且つ繰り返して積層された下部絶縁膜及び下部犠牲膜を含む下部薄膜構造体を形成する段階と、
前記下部薄膜構造体を貫通する下部パターンを形成する段階と、
前記下部パターン上に交互に、且つ繰り返して積層された上部絶縁膜及び上部犠牲膜を含む上部薄膜構造体を形成する段階と、
前記上部及び下部犠牲膜を同時に除去し、下部リセス領域及び上部リセス領域を各々前記下部絶縁膜の間及び前記上部絶縁膜の間に形成する段階と、
前記上部及び下部リセス領域を満たす情報貯蔵膜及び導電パターンを形成する段階と、を含む
ことを特徴とする3次元半導体装置の製造方法。 - 前記情報貯蔵膜は前記上部リセス領域内に形成される上部情報貯蔵膜及び前記下部リセス領域内に形成される下部情報貯蔵膜を含み、
前記導電パターンは前記上部リセス領域内に形成される上部導電パターン及び前記下部リセス領域内に形成される下部導電パターンを含み、
前記上部及び下部情報貯蔵膜は同時に形成され、
前記上部及び下部導電パターンは同時に形成される
ことを特徴とする請求項7に記載の3次元半導体装置の製造方法。 - 積層された複数の導電パターンを含み、基板上に配置される電極構造体と、
順に積層された下部パターン及び上部パターンを含み、前記電極構造体を貫通する半導体パターンと、
前記電極構造体を貫通する絶縁性電極分離パターンを含み、
前記上部パターンは前記下部パターンの上部領域より狭い下部領域を有し、前記電極分離パターンは前記電極構造体より厚い厚さを有する一体であり、
前記電極分離パターンは、その内部に前記電極分離パターンを垂直に分離させる水平的境界面を有しない
ことを特徴とする3次元半導体装置。 - 前記下部パターン及び前記上部パターンが連続して連結されることによって、前記電極構造体を貫通する前記半導体パターンは、その内部に水平的境界面を有しない
ことを特徴とする請求項9に記載の3次元半導体装置。 - 前記下部パターン及び前記上部パターンのうちの少なくとも1つは満たされた柱形である
ことを特徴とする請求項9に記載の3次元半導体装置。 - 前記下部パターン及び前記上部パターンはどちらもパイプ形の前記側壁部を有し、
前記下部パターンはその下部入口を塞ぐ板型の底部をさらに含み、
前記上部パターンはその下部入口から前記下部パターンの上部入口に連続して延長されるリング型の底部をさらに含む
ことを特徴とする請求項9に記載の3次元半導体装置。 - 前記導電パターンの高さで測定される前記基板からの距離による前記半導体パターンの幅は少なくとも2つの極値を有し、
前記導電パターンの高さで測定される前記基板からの距離による前記電極分離パターンの幅は単調増加する
ことを特徴とする請求項9に記載の3次元半導体装置。 - 前記導電パターンの高さで測定される前記基板からの距離による前記半導体パターンの幅は少なくとも2つの極値を有し、
前記導電パターンの高さで測定される前記基板からの距離による前記電極分離パターンの幅は前記半導体パターンの幅が極値を有するのと同一の高さで極値を有する
ことを特徴とする請求項9に記載の3次元半導体装置。 - トンネル絶縁膜、ブロッキング絶縁膜及びこれらの間に介在される電荷貯蔵膜を含み、前記導電パターンと前記半導体パターンの側壁との間に介在される情報貯蔵膜をさらに含み、
前記情報貯蔵膜は前記導電パターンと前記半導体パターンとの間から水平に延長されて前記導電パターンの上部面及び下部面を覆う
ことを特徴とする請求項9に記載の3次元半導体装置。 - 前記下部パターン及び前記上部パターンの間に介在される中間導電パターンをさらに含む
ことを特徴とする請求項9に記載の3次元半導体装置。
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US10153262B2 (en) | 2017-03-16 | 2018-12-11 | Toshiba Memory Corporation | Semiconductor device and manufacturing method thereof |
US10957702B2 (en) | 2018-08-31 | 2021-03-23 | Toshiba Memory Corporation | Semiconductor memory device |
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US8284601B2 (en) * | 2009-04-01 | 2012-10-09 | Samsung Electronics Co., Ltd. | Semiconductor memory device comprising three-dimensional memory cell array |
US8541832B2 (en) | 2009-07-23 | 2013-09-24 | Samsung Electronics Co., Ltd. | Integrated circuit memory devices having vertical transistor arrays therein and methods of forming same |
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