JP5118347B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5118347B2 JP5118347B2 JP2007000733A JP2007000733A JP5118347B2 JP 5118347 B2 JP5118347 B2 JP 5118347B2 JP 2007000733 A JP2007000733 A JP 2007000733A JP 2007000733 A JP2007000733 A JP 2007000733A JP 5118347 B2 JP5118347 B2 JP 5118347B2
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- film
- semiconductor device
- oxide film
- silicon oxide
- gate electrode
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Description
102 ソース領域
103、105 絶縁層
104 ゲート電極
106 ボディ
107 ボイド
108 ゲート絶縁膜
110 ドレイン領域(配線)
Claims (4)
- 第1絶縁層に囲まれたソース領域と、
前記第1の絶縁層及び前記ソース領域上に形成された第2の絶縁層と、
前記第2の絶縁層上に交互に積層された複数の第3の絶縁層及びゲート電極と、
前記ソース領域と接続され、前記複数の第3の絶縁層、前記ゲート電極及び前記第2の絶縁層を貫き、ボイドを内包するボディ部と、
前記ボディ部を囲み、前記ゲート電極との間に形成された電荷蓄積機能を有する第4の絶縁層と、
前記ボディ部上に形成されたドレイン領域と、
を備えることを特徴とする半導体装置。 - 前記ボディ部は、前記第3の絶縁層部分における直径が前記ゲート電極部分における直径よりも大きいことを特徴とする請求項1に記載の半導体装置。
- 前記ボディ部は、前記ゲート電極部分における直径が前記第3の絶縁層部分における直径よりも大きいことを特徴とする請求項1に記載の半導体装置。
- 前記ボイドは絶縁膜によって満たされていることを特徴とする請求項1に記載の半導体装置。
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JP2007000733A JP5118347B2 (ja) | 2007-01-05 | 2007-01-05 | 半導体装置 |
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JP2007000733A JP5118347B2 (ja) | 2007-01-05 | 2007-01-05 | 半導体装置 |
Publications (2)
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JP2008171838A JP2008171838A (ja) | 2008-07-24 |
JP5118347B2 true JP5118347B2 (ja) | 2013-01-16 |
Family
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JP2007000733A Active JP5118347B2 (ja) | 2007-01-05 | 2007-01-05 | 半導体装置 |
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JP (1) | JP5118347B2 (ja) |
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JP5185061B2 (ja) * | 2008-10-20 | 2013-04-17 | 猛英 白土 | Mis電界効果トランジスタ及び半導体基板の製造方法 |
US8013389B2 (en) | 2008-11-06 | 2011-09-06 | Samsung Electronics Co., Ltd. | Three-dimensional nonvolatile memory devices having sub-divided active bars and methods of manufacturing such devices |
US7994011B2 (en) | 2008-11-12 | 2011-08-09 | Samsung Electronics Co., Ltd. | Method of manufacturing nonvolatile memory device and nonvolatile memory device manufactured by the method |
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JP5376976B2 (ja) * | 2009-02-06 | 2013-12-25 | 株式会社東芝 | 不揮発性半導体記憶装置及びその製造方法 |
US8644046B2 (en) | 2009-02-10 | 2014-02-04 | Samsung Electronics Co., Ltd. | Non-volatile memory devices including vertical NAND channels and methods of forming the same |
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KR20100107661A (ko) | 2009-03-26 | 2010-10-06 | 삼성전자주식회사 | 수직 구조를 갖는 비휘발성 메모리 소자의 제조방법 |
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JP2011029234A (ja) * | 2009-07-21 | 2011-02-10 | Toshiba Corp | 不揮発性半導体記憶装置 |
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KR101698193B1 (ko) | 2009-09-15 | 2017-01-19 | 삼성전자주식회사 | 3차원 반도체 메모리 장치 및 그 제조 방법 |
KR101584113B1 (ko) | 2009-09-29 | 2016-01-13 | 삼성전자주식회사 | 3차원 반도체 메모리 장치 및 그 제조 방법 |
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JP2011138945A (ja) * | 2009-12-28 | 2011-07-14 | Toshiba Corp | 不揮発性半導体記憶装置 |
US8803214B2 (en) * | 2010-06-28 | 2014-08-12 | Micron Technology, Inc. | Three dimensional memory and methods of forming the same |
KR101736982B1 (ko) | 2010-08-03 | 2017-05-17 | 삼성전자 주식회사 | 수직 구조의 비휘발성 메모리 소자 |
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KR101699515B1 (ko) | 2010-09-01 | 2017-02-14 | 삼성전자주식회사 | 3차원 반도체 장치 및 그 제조 방법 |
JP5422530B2 (ja) * | 2010-09-22 | 2014-02-19 | 株式会社東芝 | 半導体記憶装置及びその製造方法 |
US8759895B2 (en) | 2011-02-25 | 2014-06-24 | Micron Technology, Inc. | Semiconductor charge storage apparatus and methods |
JP2012204592A (ja) * | 2011-03-25 | 2012-10-22 | Toshiba Corp | 半導体装置の製造方法 |
JP5059989B1 (ja) * | 2011-06-28 | 2012-10-31 | パナソニック株式会社 | 半導体装置とその製造方法 |
US8563987B2 (en) | 2011-06-28 | 2013-10-22 | Panasonic Corporation | Semiconductor device and method for fabricating the device |
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JP2013183086A (ja) | 2012-03-02 | 2013-09-12 | Toshiba Corp | 半導体装置及びその製造方法 |
WO2013148393A1 (en) * | 2012-03-31 | 2013-10-03 | Cypress Semiconductor Corporation | Integration of non-volatile charge trap memory devices and logic cmos devices |
JP6400536B2 (ja) | 2015-08-04 | 2018-10-03 | 東芝メモリ株式会社 | 半導体記憶装置 |
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JPH1093083A (ja) * | 1996-09-18 | 1998-04-10 | Toshiba Corp | 半導体装置の製造方法 |
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JP3762136B2 (ja) * | 1998-04-24 | 2006-04-05 | 株式会社東芝 | 半導体装置 |
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