JP4409455B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP4409455B2 JP4409455B2 JP2005022478A JP2005022478A JP4409455B2 JP 4409455 B2 JP4409455 B2 JP 4409455B2 JP 2005022478 A JP2005022478 A JP 2005022478A JP 2005022478 A JP2005022478 A JP 2005022478A JP 4409455 B2 JP4409455 B2 JP 4409455B2
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- Prior art keywords
- electrode
- semiconductor chip
- chip
- semiconductor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/117—Shapes of semiconductor bodies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
- H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
- H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
- H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
- H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/0198—Manufacture or treatment batch processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07231—Techniques
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/241—Dispositions, e.g. layouts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
- H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005022478A JP4409455B2 (ja) | 2005-01-31 | 2005-01-31 | 半導体装置の製造方法 |
| US11/329,600 US7291929B2 (en) | 2005-01-31 | 2006-01-10 | Semiconductor device and method of manufacturing thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005022478A JP4409455B2 (ja) | 2005-01-31 | 2005-01-31 | 半導体装置の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2006210745A JP2006210745A (ja) | 2006-08-10 |
| JP2006210745A5 JP2006210745A5 (https=) | 2007-05-31 |
| JP4409455B2 true JP4409455B2 (ja) | 2010-02-03 |
Family
ID=36755672
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005022478A Expired - Fee Related JP4409455B2 (ja) | 2005-01-31 | 2005-01-31 | 半導体装置の製造方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US7291929B2 (https=) |
| JP (1) | JP4409455B2 (https=) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI495053B (zh) * | 2012-03-23 | 2015-08-01 | 東芝股份有限公司 | Semiconductor device |
Families Citing this family (86)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SG115456A1 (en) * | 2002-03-04 | 2005-10-28 | Micron Technology Inc | Semiconductor die packages with recessed interconnecting structures and methods for assembling the same |
| JP4263953B2 (ja) * | 2003-06-23 | 2009-05-13 | 三洋電機株式会社 | 半導体装置及びその製造方法 |
| WO2006059589A1 (ja) * | 2004-11-30 | 2006-06-08 | Kyushu Institute Of Technology | パッケージングされた積層型半導体装置及びその製造方法 |
| US7251160B2 (en) * | 2005-03-16 | 2007-07-31 | Sandisk Corporation | Non-volatile memory and method with power-saving read and program-verify operations |
| JP2006278906A (ja) * | 2005-03-30 | 2006-10-12 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
| JP4551255B2 (ja) * | 2005-03-31 | 2010-09-22 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP4577688B2 (ja) | 2005-05-09 | 2010-11-10 | エルピーダメモリ株式会社 | 半導体チップ選択方法、半導体チップ及び半導体集積回路装置 |
| US7331796B2 (en) * | 2005-09-08 | 2008-02-19 | International Business Machines Corporation | Land grid array (LGA) interposer utilizing metal-on-elastomer hemi-torus and other multiple points of contact geometries |
| US7390700B2 (en) * | 2006-04-07 | 2008-06-24 | Texas Instruments Incorporated | Packaged system of semiconductor chips having a semiconductor interposer |
| JP2007300488A (ja) * | 2006-05-01 | 2007-11-15 | Alps Electric Co Ltd | カメラモジュール |
| US7746661B2 (en) * | 2006-06-08 | 2010-06-29 | Sandisk Corporation | Printed circuit board with coextensive electrical connectors and contact pad areas |
| JP4916241B2 (ja) * | 2006-07-28 | 2012-04-11 | パナソニック株式会社 | 半導体装置及びその製造方法 |
| KR100737162B1 (ko) * | 2006-08-11 | 2007-07-06 | 동부일렉트로닉스 주식회사 | 반도체 소자 및 그 제조방법 |
| JP4793169B2 (ja) * | 2006-08-24 | 2011-10-12 | 日立電線株式会社 | 接続体および光送受信モジュール |
| US7952184B2 (en) | 2006-08-31 | 2011-05-31 | Micron Technology, Inc. | Distributed semiconductor device methods, apparatus, and systems |
| US7754532B2 (en) * | 2006-10-19 | 2010-07-13 | Micron Technology, Inc. | High density chip packages, methods of forming, and systems including same |
| TWI335070B (en) * | 2007-03-23 | 2010-12-21 | Advanced Semiconductor Eng | Semiconductor package and the method of making the same |
| JP2008258522A (ja) * | 2007-04-09 | 2008-10-23 | Renesas Technology Corp | 半導体装置の製造方法 |
| JP4937842B2 (ja) | 2007-06-06 | 2012-05-23 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| JP2009021433A (ja) * | 2007-07-12 | 2009-01-29 | Fujikura Ltd | 配線基板及びその製造方法 |
| US8350382B2 (en) * | 2007-09-21 | 2013-01-08 | Infineon Technologies Ag | Semiconductor device including electronic component coupled to a backside of a chip |
| JP2009181981A (ja) | 2008-01-29 | 2009-08-13 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
| EP2096115A1 (en) * | 2008-02-26 | 2009-09-02 | Nestec S.A. | Oligosaccharide ingredient |
| JP2009206429A (ja) * | 2008-02-29 | 2009-09-10 | Toshiba Corp | 記憶媒体 |
| JP2009239256A (ja) * | 2008-03-03 | 2009-10-15 | Panasonic Corp | 半導体装置及びその製造方法 |
| JP2009260284A (ja) * | 2008-03-25 | 2009-11-05 | Panasonic Corp | 半導体素子、および半導体素子の製造方法 |
| TWI473553B (zh) * | 2008-07-03 | 2015-02-11 | 日月光半導體製造股份有限公司 | 晶片封裝結構 |
| US7872332B2 (en) | 2008-09-11 | 2011-01-18 | Micron Technology, Inc. | Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods |
| JP5331427B2 (ja) | 2008-09-29 | 2013-10-30 | 株式会社日立製作所 | 半導体装置 |
| KR20100037300A (ko) * | 2008-10-01 | 2010-04-09 | 삼성전자주식회사 | 내장형 인터포저를 갖는 반도체장치의 형성방법 |
| US20100085607A1 (en) * | 2008-10-02 | 2010-04-08 | Silverbrook Research Pty Ltd | Method of encoding coding pattern |
| US7776655B2 (en) | 2008-12-10 | 2010-08-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming conductive pillars in recessed region of peripheral area around the device for electrical interconnection to other devices |
| US8012797B2 (en) * | 2009-01-07 | 2011-09-06 | Advanced Semiconductor Engineering, Inc. | Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries |
| TWI499024B (zh) * | 2009-01-07 | 2015-09-01 | 日月光半導體製造股份有限公司 | 堆疊式多封裝構造裝置、半導體封裝構造及其製造方法 |
| US20100171206A1 (en) * | 2009-01-07 | 2010-07-08 | Chi-Chih Chu | Package-on-Package Device, Semiconductor Package, and Method for Manufacturing The Same |
| JP4853530B2 (ja) * | 2009-02-27 | 2012-01-11 | 株式会社豊田中央研究所 | 可動部を有するマイクロデバイス |
| WO2010106732A1 (ja) * | 2009-03-17 | 2010-09-23 | パナソニック株式会社 | 半導体装置 |
| EP2244291A1 (en) | 2009-04-20 | 2010-10-27 | Nxp B.V. | Multilevel interconnection system |
| EP2273545B1 (en) * | 2009-07-08 | 2016-08-31 | Imec | Method for insertion bonding and kit of parts for use in said method |
| TWI469283B (zh) * | 2009-08-31 | 2015-01-11 | 日月光半導體製造股份有限公司 | 封裝結構以及封裝製程 |
| US8803332B2 (en) * | 2009-09-11 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Delamination resistance of stacked dies in die saw |
| US8237278B2 (en) | 2009-11-16 | 2012-08-07 | International Business Machines Corporation | Configurable interposer |
| US8198131B2 (en) * | 2009-11-18 | 2012-06-12 | Advanced Semiconductor Engineering, Inc. | Stackable semiconductor device packages |
| US9027239B2 (en) | 2009-12-18 | 2015-05-12 | Aerocrine Ab | Method for plugging a hole |
| TWI408785B (zh) * | 2009-12-31 | 2013-09-11 | 日月光半導體製造股份有限公司 | 半導體封裝結構 |
| US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
| TWI419283B (zh) | 2010-02-10 | 2013-12-11 | 日月光半導體製造股份有限公司 | 封裝結構 |
| JP2011187771A (ja) * | 2010-03-10 | 2011-09-22 | Omron Corp | 電極部の構造 |
| TWI411075B (zh) | 2010-03-22 | 2013-10-01 | 日月光半導體製造股份有限公司 | 半導體封裝件及其製造方法 |
| US8624374B2 (en) | 2010-04-02 | 2014-01-07 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof |
| US8278746B2 (en) | 2010-04-02 | 2012-10-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages including connecting elements |
| US8202797B2 (en) | 2010-06-22 | 2012-06-19 | Stats Chippac Ltd. | Integrated circuit system with recessed through silicon via pads and method of manufacture thereof |
| US8598695B2 (en) * | 2010-07-23 | 2013-12-03 | Tessera, Inc. | Active chip on carrier or laminated chip having microelectronic element embedded therein |
| TWI451546B (zh) | 2010-10-29 | 2014-09-01 | 日月光半導體製造股份有限公司 | 堆疊式封裝結構、其封裝結構及封裝結構之製造方法 |
| JP2012134270A (ja) * | 2010-12-21 | 2012-07-12 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
| KR101828386B1 (ko) * | 2011-02-15 | 2018-02-13 | 삼성전자주식회사 | 스택 패키지 및 그의 제조 방법 |
| JP5396415B2 (ja) * | 2011-02-23 | 2014-01-22 | 株式会社東芝 | 半導体装置 |
| US9171792B2 (en) | 2011-02-28 | 2015-10-27 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages having a side-by-side device arrangement and stacking functionality |
| US9418876B2 (en) | 2011-09-02 | 2016-08-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of three dimensional integrated circuit assembly |
| US9245773B2 (en) | 2011-09-02 | 2016-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device packaging methods and structures thereof |
| ITMI20111777A1 (it) * | 2011-09-30 | 2013-03-31 | St Microelectronics Srl | Sistema elettronico per saldatura ad onda |
| JP6075825B2 (ja) * | 2012-04-26 | 2017-02-08 | 新光電気工業株式会社 | パッド形成方法 |
| US9362197B2 (en) * | 2012-11-02 | 2016-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Molded underfilling for package on package devices |
| JP6215544B2 (ja) * | 2013-03-18 | 2017-10-18 | 株式会社ディスコ | ウエーハの加工方法 |
| KR102033789B1 (ko) | 2013-07-25 | 2019-10-17 | 에스케이하이닉스 주식회사 | 적층형 패키지 및 그 제조방법 |
| JP6210777B2 (ja) * | 2013-07-26 | 2017-10-11 | 新光電気工業株式会社 | バンプ構造、配線基板及び半導体装置並びにバンプ構造の製造方法 |
| KR102077608B1 (ko) * | 2013-09-26 | 2020-02-17 | 에스케이하이닉스 주식회사 | 반도체 칩 및 이를 갖는 스택 패키지 |
| CN103633078B (zh) * | 2013-11-01 | 2016-06-08 | 南车株洲电力机车研究所有限公司 | 用于平板式功率半导体器件的压装装置 |
| JP2015185754A (ja) | 2014-03-25 | 2015-10-22 | 株式会社東芝 | 半導体装置 |
| US12068231B2 (en) * | 2014-05-24 | 2024-08-20 | Broadpak Corporation | 3D integrations and methods of making thereof |
| US9786643B2 (en) | 2014-07-08 | 2017-10-10 | Micron Technology, Inc. | Semiconductor devices comprising protected side surfaces and related methods |
| CN105575924B (zh) * | 2014-10-15 | 2018-07-03 | 台达电子工业股份有限公司 | 功率模块 |
| US10679866B2 (en) | 2015-02-13 | 2020-06-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structure for semiconductor package and method of fabricating the interconnect structure |
| JP2017022352A (ja) | 2015-07-15 | 2017-01-26 | 富士通株式会社 | 半導体装置 |
| FR3041625B1 (fr) * | 2015-09-29 | 2021-07-30 | Tronics Microsystems | Dispositif de fixation de deux elements tels qu'une puce, un interposeur et un support |
| JP7079648B2 (ja) | 2018-04-24 | 2022-06-02 | 富士フイルムヘルスケア株式会社 | 超音波探触子の製造方法、超音波探触子、超音波検査装置、スマートフォン、および、タブレット |
| US10535644B1 (en) * | 2018-06-29 | 2020-01-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Manufacturing method of package on package structure |
| US11127706B2 (en) | 2018-09-28 | 2021-09-21 | Intel Corporation | Electronic package with stud bump electrical connections |
| JP7353748B2 (ja) * | 2018-11-29 | 2023-10-02 | キヤノン株式会社 | 半導体装置の製造方法および半導体装置 |
| JP2020150145A (ja) | 2019-03-14 | 2020-09-17 | キオクシア株式会社 | 半導体装置 |
| FR3104315B1 (fr) * | 2019-12-04 | 2021-12-17 | St Microelectronics Tours Sas | Procédé de fabrication de puces électroniques |
| US11616019B2 (en) * | 2020-12-21 | 2023-03-28 | Nvidia Corp. | Semiconductor assembly |
| US11869872B2 (en) | 2021-08-05 | 2024-01-09 | Institute of semiconductors, Guangdong Academy of Sciences | Chip stack packaging structure and chip stack packaging method |
| FR3126540A1 (fr) | 2021-08-31 | 2023-03-03 | Stmicroelectronics (Tours) Sas | Procédé de fabrication de puces électroniques |
| US20230326843A1 (en) * | 2022-04-07 | 2023-10-12 | Chun-hsia Chen | Electric contact structure for three-dimensional chip package module |
| CN119757809B (zh) * | 2023-09-28 | 2025-11-28 | 芯卓科技(浙江)有限公司 | 弹性中介层及其导电装置 |
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| TWI495053B (zh) * | 2012-03-23 | 2015-08-01 | 東芝股份有限公司 | Semiconductor device |
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| US20060170112A1 (en) | 2006-08-03 |
| US7291929B2 (en) | 2007-11-06 |
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