JP3517080B2 - 半導体材料薄層の製造方法 - Google Patents

半導体材料薄層の製造方法

Info

Publication number
JP3517080B2
JP3517080B2 JP12600597A JP12600597A JP3517080B2 JP 3517080 B2 JP3517080 B2 JP 3517080B2 JP 12600597 A JP12600597 A JP 12600597A JP 12600597 A JP12600597 A JP 12600597A JP 3517080 B2 JP3517080 B2 JP 3517080B2
Authority
JP
Japan
Prior art keywords
wafer
heat treatment
thin layer
dose amount
semiconductor material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP12600597A
Other languages
English (en)
Other versions
JPH1050628A (ja
Inventor
アスパル ベルナール
ブリュエル ミシェル
プメイロル ティエリー
Original Assignee
コミツサリア タ レネルジー アトミーク
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=9492177&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=JP3517080(B2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by コミツサリア タ レネルジー アトミーク filed Critical コミツサリア タ レネルジー アトミーク
Publication of JPH1050628A publication Critical patent/JPH1050628A/ja
Application granted granted Critical
Publication of JP3517080B2 publication Critical patent/JP3517080B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
    • G03F7/70541—Tagging, i.e. hardware or software tagging of features or components, e.g. using tagging scripts or tagging identifier codes for identification of chips, shots or wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24479—Structurally defined web or sheet [e.g., overall dimension, etc.] including variation in thickness
    • Y10T428/24612—Composite web or sheet

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、半導体材料の薄層
の製造方法に関する。製造される薄層には必要に応じて
電子部品を備えることができる。
【０００２】本発明は、単結晶でも多結晶でも、また更
には非結晶（アモルファス）の半導体の薄層を製造で
き、例えば、絶縁体上のケイ素（ＳＯＩ）型の基板の製
造や、単結晶半導体の自己保持型薄層の製造ができる。
これらの薄層または基板に電子回路および（または）マ
イクロストラクチャアを完全にまたは部分的に形成する
ことができる。
【０００３】
【従来の技術】半導体材料内への希ガスまたは水素のイ
オンの注入によって、それらイオンの浸透の平均深さに
近い深さの所に微小キャビティが形成されることは知ら
れている。仏国特許ＦＲ−Ａ−２６８１４７２号は、こ
の特性を利用した半導体材料の薄膜の製造方法を開示し
ている。この方法は、平らな表面を有する所望の半導体
材料のウェーハに下記の処理を施すものである。すなわ
ちそれら処理とは、−第１段階、ウェーハの平らな表面
をイオンで衝撃することによるイオン注入の段階。この
イオン注入によりウェーハ内のイオン浸透深さに近い深
さの所に微小キャビティの層が形成される。この微小キ
ャビティ層はウェーハを、基板になる下側区域と薄膜に
なる上側区域とに分ける。イオンは希ガスまたは水素ガ
スのイオンから選ばれ、そしてウェーハの温度は、注入
されたイオンが拡散によって半導体から逃げることので
きる温度より低く保持される。−第２段階、ウェーハの
平らな表面を、硬質材料の少なくとも１つの層で構成さ
れる支持サポートに密着接触させる段階。この密着接触
は例えば、接着剤によって、あるいは、場合によっては
支持サポートとウェーハとの間の原子間結合を良好にす
る熱的または（および）静電気的処理を用いた両表面の
前処理を施すことによって行われる。−第３段階、ウェ
ーハと支持サポートとの組立体の熱処理段階。この熱処
理は、イオン注入のときの温度より高く、そして、ウェ
ーハ内の結晶の再配列と微小キャビティの圧力との作用
によって薄膜と基板との間の分離を生じせるに充分な温
度で行われる。この温度は例えばケイ素の場合５００℃
である。
【０００４】イオン注入はガスの微小泡の層を形成する
のに適している。こうしてウェーハ内の、イオン浸透の
平均深さに近い深さの所に形成された微小泡層はウェー
ハ内に、その層で分離される２つの区域、すなわち、薄
膜を構成する区域と残余の基板を構成する区域とを形成
する。
【０００５】例えば水素のようなガスの打込みの後、そ
の打込みの条件によって、微小キャビティまたは微小泡
は透過型電子顕微鏡で観察できることもあり、できない
こともある。ケイ素の場合、得られる微小キャビティの
寸法は数ｎｍから数１０ｎｍまで様々である。特に打込
み温度が低い場合、それら微小キャビティは熱処理段階
の過程においてでしか観察することができず、その過程
において集合化し、熱処理の最後には微小キャビティ相
互は隔合する。
【０００６】仏国特許ＦＲ−Ａ−２６８１４７２号に記
載の方法は、イオン注入後のウェーハの平らな表面およ
びその内部に電子回路を作ることができない。そのよう
な回路を形成するためには、ケイ素の場合幾つかの熱処
理段階（典型的には４００°から７００℃）を必要とす
るマイクロエレクトロニクスの通常的な操作（拡散、蒸
着等）を行うことになる。ところでそのような温度で
は、イオン注入されたウェーハの平らな表面にふくれ
（ｂｌｉｓｔｅｒｓ）が形成される。例えばシリコンウ
ェーハに水素イオンを５・１０16陽子／ｃｍ2 のドーズ
量で１００ｋｅＶのエネルギで打込んだ場合、５００℃
で３０分間の熱処理によりウェーハの平らな表面の５０
％が劣化（ｄｅｇｒａｄａｔｉｏｎ）し、ふくれの出現
と破裂（ｂｕｒｓｔｉｎｇ）をもたらす。こうなった場
合には、もはや、半導体層をウェーハの残余部から剥離
するために、ウェーハの平らな表面を支持サポート（以
下、アプリケータと称する）に密着接触させることを正
確に行うことはできない。
【０００７】水素イオン打込み後のシリコンウェーハの
表面に加熱（ａｎｎｅａｌｉｎｇ）後ふくれとクレータ
が形成されるその現象は、Ｙ．ミシマとＴ．ヤギシタの
論文「フーリエ変換赤外線マイクロスペクトロスコピに
よるＳｉ：Ｈ膜内の泡形成機構の研究」（Ｊ．Ａｐｐ
ｌ．Ｐｈｅｓ．６４（８）、１９８８年１０月１５日、
ｐｐ．３９７２−３９７４）の中で論じられている。
【０００８】
【発明が解決しようとする課題】本発明は、仏国特許Ｆ
Ｒ−Ａ−２６８１４７２号に記載の方法を改良しようと
するものである。本発明では、ある適当なドーズ量のイ
オン注入段階の後で、かつ分離段階の前に、ウェーハの
平らな表面の状態の劣化と薄層の分離とを起こすこと無
しに、ウェーハの薄層となる部分を、特にケイ素の場合
では４００℃から７００℃で熱処理する。この中間熱処
理は、電子部品形成操作の一部とすることができ、ある
いはその他の目的のために挿入することもできる。
【０００９】本発明はまた、薄層が大きい機械的強度を
備えるに充分な厚さを有する場合にも適用できる。この
場合には薄層をウェーハの残余部から分離させるための
アプリケータを使用する必要はないが、いずれにしても
平らな表面の欠陥は全く無くすることが望ましい。
【００１０】
【課題を解決するための手段】本発明はそこで、次のよ
うな平らな表面を有する半導体材料のウェーハから同材
料の薄層を提供することを目的とする。この方法はイオ
ン注入の段階を備え、このイオン注入段階は、希ガスま
たは水素のイオンから選ばれるイオンを所定の温度と所
定のドーズ量で平らな表面を衝撃することより成り、こ
れによって、イオン浸透の平均的な深さに近い深さの所
に位置する指標面（ｒｅｆｅｒｅｎｃｅｐｌａｎｅ）と
称される平面内に微小キャビティを形成し、さらにこの
方法はまた後の熱処理の段階を備え、この熱処理段階
は、ウェーハを指標面において２つの部分に分離させる
に充分な温度で行われ、平らな表面の側の部分が薄層を
構成する半導体材料薄層製造方法であって、 −イオン注入段階が最少ドーズ量と最大ドーズ量との間
のあるドーズ量で行われるが、最少ドーズ量とは、ウェ
ーハを指標面に沿って脆弱化する微小キャビティを充分
に形成できる最少限のドーズ量であり、また最大ドーズ
量、または臨界ドーズ量とは、これ以上であれば、熱処
理段階のときにウェーハの分離が生じるようなドーズ量
であり、 −熱処理段階の後またはその間に、ウェーハを指標面に
おいて２つの部分に分離させる段階が備えられ、この分
離段階は、ウェーハのそれら２つの部分の間に機械的な
力を加えることを含む方法である。
【００１１】それら機械的力は、単独でまたは組合せて
加えられる引張力、剪断力、および撓曲力とされよう。
【００１２】微小キャビティである限りにおいて、それ
らキャビティは様々な形状とすることができる。例えば
キャビティは偏平な形状、すなわち高さが小さい（数原
子間距離）形状、またはほぼ球形な形状、あるいはその
他のあらゆる形状にすることができる。それらキャビテ
ィは、自由ガス相、および（または）、キャビティの壁
を形成する材料の原子に固定された注入イオンから出て
くるガスの原子を容れることができる。それらキャビテ
ィは英語の用語で一般的に、「プレートレット（ｐｌａ
ｔｅｌｅｔｓ）」、「マイクロブリスタ（ｍｉｃｒｏｂ
ｌｉｓｔｅｒｓ）」、あるいは「バブル（ｂｕｂｂｌｅ
ｓ）」と称される。
【００１３】薄層をウェーハから分離させるための熱処
理は微小キャビティを安定状態にする。実際、温度の作
用により微小キャビティは相互に合着し、固定状態にな
る。そこで温度はその状態が得られるように選択され
る。
【００１４】仏国特許ＦＲ−Ａ−２６８１４７２号にお
いて、打込みドーズ量は、熱処理によって、直接分離を
行える微小キャビティ層を形成するようなものにされて
いる。
【００１５】本発明において、ドーズ量は、熱処理の過
程で分離を行わせるのには不充分なものにされ、そのド
ーズ量は単にウェーハの指標面の個所を脆弱にするだけ
であり、分離は機械的力を加えるという別の段階によっ
て行われるのである。さらに本発明で定義するようなそ
の臨界ドーズ量は、イオン注入段階と熱処理段階の過程
でウェーハの平らな表面上にふくれを形成するようなド
ーズ量より少ないものである。よって、ふくれの問題は
本発明では生じない。
【００１６】本発明の方法は、熱処理段階と分離段階と
の間に、薄層を構成する前にウェーハに電子部品（ｃｏ
ｍｐｏｎｅｎｔ）の少なくとも一部または全部を形成す
る段階を備えることができる。
【００１７】その電子部品形成段階が様々な相（ｐｈａ
ｓｅｓ）の熱処理を必要とする場合には、それら熱処理
は好適には熱処理段階での温度より低い温度で行われ
る。
【００１８】必要な場合には、分離段階の直前に、ウェ
ーハの平らな表面を支持サポートに密着接触させて固定
する追加の段階が備えられ、その支持を介して引張力お
よび（または）剪断力のような機械力が加えられる。
【００１９】その支持は可撓性のある支持、例えばカプ
トン（Ｋａｐｔｏｎ登録商標）のシートとすることがで
きる。また支持は酸化ケイ素のウェーハのような堅固な
支持とすることができる。
【００２０】以下に添付図面と関連して行う本発明の制
約的でない実施形態の記述から本発明はさらによく理解
され、そして他の長所と特徴が明らかにされよう。
【００２１】
【発明の実施形態】本発明の１つの重要な点は、水素ま
たは希ガスのイオンの注入が、熱処理において分離、剥
離（ｓｅｐａｒａｔｉｏｎ）を起させるようなドーズ量
よりも低いかまたは等しいドーズ量で行われることであ
る。その使用されるドーズ量は、ウェーハの材料内への
イオンの平均的な到達距離に対応する深さＲｐの部位の
材料を脆弱化するが、しかし電子回路を作るための全て
の熱処理段階には耐えるに充分な機械的強度をウェーハ
が保持することができるようなドーズ量である。換言す
ると、イオン注入されたウェーハは、その微小キャビテ
ィの区域に、ウェーハの薄膜を構成する部分とウェーハ
の残余部分との間を結合するブリッジを備えている。
【００２２】以下の記述は、平らな表面を有する厚い基
板から半導体材料の薄層を製造することについて行う。
素材の基板は、その平らな表面が、例えば誘電体の被覆
材料のような材料の１つまたは複数の層を被せられても
よいし、またそうでなくてもよい。
【００２３】図１は、半導体材料でできたウェーハ１へ
のイオンの注入段階を示す。ウェーハの平らな表面２
は、矢印で図示されるイオンの衝撃（ボンバード）を受
ける。ウェーハの表面２が１つまたは複数の非半導体材
料で被覆されている場合、注入されるイオンのエネルギ
は、それらイオンを半導体材料のマスの中まで浸透、貫
通させることができるように充分強くなければならな
い。
【００２４】いずれにしてもイオン注入される半導体材
料の厚さは、薄層に電子部品および（または）マイクロ
ストラクチュアの全部または一部が形成できるような厚
さでなければならない。例えばケイ素への水素イオンの
平均浸透深さ（ｐｅｎｅｔｒａｔｉｏｎ）は２００ｋｅ
Ｖで２μｍである。
【００２５】その種類のイオンの半導体基板内へのイオ
ン注入は、平らな表面２に対し直角に進むイオンの平均
到達距離Ｒｐに対応する深さに近い深さの所に、微小キ
ャビティを生じさせる原子の集中した高い密度の区域３
を形成する。例えば１００ｋｅＶでの２・１０16Ｈ+ ／
ｃｍ2 のドーズ量の場合、水素の最高密度は１０21Ｈ +
／ｃｍ3 になる。このイオン注入段階は、注入されるガ
スのイオンが注入段階の間に拡散することがないような
温度で行わなければならない。そのような拡散は微小キ
ャビティの形成を攪乱または不能にする。例えばケイ素
に水素イオンを注入する場合、そのイオン注入は３５０
℃以下の温度で行われる。
【００２６】注入ドーズ量（注入中の単位面積当りのイ
オンの数）は、臨界ドーズ量と等しいかまたはそれ以下
となるように選択される。臨界ドーズ量とは、それ以上
であれば後続の熱処理段階において薄層がウェーハから
分離するような量である。水素イオンの注入の場合、そ
の臨界ドーズ量は、１６０ｋｅＶのエネルギに対し４・
１０16Ｈ+ ／ｃｍ2 のオーダである。
【００２７】注入ドーズ量はまた、最小ドーズ量より多
くなるように選択されている。最小ドーズ量とは、それ
以上であれば後続の熱処理段階において微小キャビティ
の形成とそれらキャビティ間の相互作用とが充分に行わ
れる、すなわち微小キャビティ区域３の材料を脆弱にす
ることができるような量である。そのことは、微小キャ
ビティ間になお半導体材料のソリッド（ｓｏｌｉｄ）ブ
リッジが存在していることを意味している。水素ガスの
イオン注入の場合、最少ドーズ量は、１００ｋｅＶのエ
ネルギで１・１０16／ｃｍ2 のオーダである。
【００２８】本発明の方法における次の段階は、指標面
に沿って微小キャビティを相互に隔着させるに充分な温
度でウェーハを熱処理することである。ケイ素の基板内
へ、１００ｋｅＶのエネルギで３・１０16Ｈ+ ／ｃｍ2
のドーズ量の水素ガスのイオンが３５０℃以下の温度で
打込まれた場合、５５０℃で３０分間の熱処理した後、
断面を走査顕微鏡で検査したところで、高さ数分の１ナ
ノメートル、指標面に沿った幅数ナノメートルから数１
０ナノメートルにもなるキャビティが観察される。その
熱処理は、打ち込まれたガス原子の、微小キャビティと
しての析出（ｐｒｅｃｉｐｉｔａｔｉｏｎ）と安定化を
同時に行う。
【００２９】微小キャビティ４（図２参照）は指標面に
おいて、イオン注入面積とほぼ等しい面積を占める。そ
れらキャビティは全てが正確に同一平面内にあるわけで
はない。それらキャビティは、指標面から数ナノメート
ルあるいは数１０ナノメートル離れた指標面に平行な複
数の平面内に散在する。このことによって、平らな表面
２と指標面との間の基板の上側部分は全体としては基板
のマスから分離されない（ここで基板マスとは、平らな
表面２以外の基板の面と指標面との間にある基板残余分
をいう）。上側部分と基板マスとの間以外の他の結合
は、集積回路を作るためのいろいろな技術的段階におけ
る取扱いと熱処理（ａｎｎｅａｌｉｎｇ）に耐える充分
な強度をもっている。しかし上側部分と基板マスとの間
の結合はキャビティ間の半導体材料のブリッジによって
のみ行われるから非常に弱くなっている。
【００３０】次に平らな表面２（その表面および表面の
下）に電子部品、電子回路、およびマイクロストラクチ
ュアの一部または全部が形成される。
【００３１】第１段階の水素または希ガスのイオンの注
入エネルギは、イオン注入によって形成されるキャビテ
ィの区域の深さが、電子部品、電子回路、および（また
は）マイクロストラクチュアの形成によって攪乱される
ことのない充分な深さになるように選択される。さら
に、電子部品、電子回路、またはマイクロストラクチュ
アを作るのに伴なう様々な熱処理操作は、注入されたイ
オンの拡散を最少限にするように選択される。例えば単
結晶ケイ素のウェーハの場合、プロセスのいろいろな相
における最高温度は好適には９００℃までに限定され
る。
【００３２】図３は、ウェーハ１の平らな表面２と薄層
を構成する部分内とに、符号５で指示される複数個の電
子部品を形成した場合を示している。
【００３３】次に分離段階が来る。この分離段階は、ウ
ェーハまたは基板の指標面の両側の２つの部分の間を分
離させる機械的な力、例えば引張力を加えることより成
る。その機械力によって現存する堅いブリッジを破壊す
るのである。この操作によって、上記した場合であれば
電子部品５を備えた、半導体材料の薄層が作られる。図
４はこの分離段階を示し、この分離段階において、図面
に矢印で示される相互に反対方向に作用する力によって
薄層６が基板の残余マス７から分離される。
【００３４】経験的に知られているところでは、上側部
分を基板のマスから分離させるに要する引張力は、特に
上側部分と基板マスとの間に剪断力、すなわち指標面に
沿った方向の分力を含む力加えた場合には小さくて済
む。このことは単純に、剪断力が指標面内のキャビティ
間の破断の伝播に好都合であるということで説明でき
る。
【００３５】基板の上側部分は元より薄いものであるか
ら、多くの場合それに対して直接に引張力および（また
は）剪断力を加えるのは適切でない。そこで好適には、
分離段階の前にウェーハの平らな表面２に支持またはア
プリケータが固定され、これを介して機械力がウェーハ
の上側部分に加えられる。そのアプリケータは図４に符
号８で指示される。
【００３６】アプリケータは硬質または軟質の支持とす
ることができ、そして任意の接着剤により、または表面
処理の上密着接触させることによりウェーハに固定され
る。この固定はウェーハの表面とアプリケータとの間に
充分な結合エネルギが確保され、これにより分離段階の
引張および（または）剪断および（または）撓曲の操作
に耐えるように行われる。
【００３７】アプリケータ８は例えば、基板１の平らな
表面２に接着されるカプトン（Ｋａｐｔｏｎ商品名）の
ようなプラスチック材料のシートとすることができる。
この場合、本発明の方法を適用したとき、カプトンのシ
ート上に付けられた単結晶半導体薄層が製造されること
になる。
【００３８】上側薄層の全体に力を正確に伝達するた
め、電子部品形成段階において、上側薄層の表面とこれ
の中に作られる回路に、必要に応じて表面を平らにする
役目も持った保護層を被覆してもよい。この場合アプリ
ケータはその保護層を介在してウェーハの上側薄層に固
定される。
【００３９】アプリケータはまた例えばシリコンウェー
ハのような硬質の支持とすることができ、これの表面に
誘電体層を被せたものにしてもよい。この場合、ウェー
ハの平らな表面および（または）アプリケータの表面
（誘電体層を持っているかまたは持っていない）に適当
な物理−化学的処理を施し、場合によっては熱処理を伴
なって密着接触を行わせることによりウェーハ表面とア
プリケータ表面との固定が行われよう。
【００４０】アプリケータが表面に酸化物層を持ったシ
リコンウェーハであり、そして半導体基板が単結晶シリ
コンウェーハである上記実施形態の場合、本発明の方法
を適用したとき、表面ケイ素層が基板上側部分で作られ
る薄層である、絶縁体上に付けられたシリコンウェーハ
が製造される。
【００４１】さらに薄層をウェーハから分離した後、そ
の薄層の自由面に追加の基板を積み重ねることも可能
で、その追加基板はこれに全部または一部が形成された
電子部品を備えるものとすることもできる。そのような
積層は電子回路の「３次元」集合体を形成することがで
きる。その補強材（ｓｔｉｆｆｅｎｅｒ）自体にも電子
部品を備えることも備えないこともできる。
【図面の簡単な説明】
【図１】一方の表面が本発明の方法を行うためのイオン
の衝撃を受ける半導体材料のウェーハを概略的に示す。
【図２】本発明に従って微小キャビティを合着させる熱
処理段階の終了時のウェーハを概略的に示す。
【図３】所要の薄層となる部分に電子部品を形成された
後のウェーハを概略的に示す。
【図４】本発明に従ってウェーハを２つの部分に分離す
る段階を概略的に示す。
【符号の説明】
１ 半導体ウェーハ ２ 表面 ３ 微小キャビティ区域 ４ 微小キャビティ ５ 電子部品 ６ 薄層 ７ 残余マス ８ アプリケータ Ｒｐ イオン浸透深さ
───────────────────────────────────────────────────── フロントページの続き (72)発明者 ティエリー プメイロル フランス国ヌワヤレイ，シュマン ドュ ディデイ，159 (56)参考文献 特開 平８−97389（ＪＰ，Ａ) 特開 平５−211128（ＪＰ，Ａ) 特開 平７−254690（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/265 H01L 27/12

Claims (2)

    (57)【特許請求の範囲】
  1. 【請求項１】 平らな表面を有する半導体材料のウェー
    ハから同材料の薄層を製造する方法であって、この方法
    はイオン注入段階を備え、このイオン注入段階は、希ガ
    スまたは水素のイオンから選ばれるイオンによって所定
    の温度と所定のドーズ量で前記平らな表面を衝撃するこ
    とより成り、これによって、イオン浸透の平均的な深さ
    に近い深さの所に位置する指標面と称される平面内に微
    小キャビティを形成し、更にこの方法は後の熱処理の段
    階を備え、この熱処理の段階は、前記ウェーハを前記指
    標面において２つの部分に分離させるに充分な温度で行
    われ、そこでその前記平らな表面の側の部分が前記薄層
    を構成する如き、半導体材料薄層製造方法において、 −前記イオン注入段階が最少のイオンドーズ量と最大の
    イオンドーズ量との間のあるイオンドーズ量を以って行
    われ、しかして該最少ドーズ量とは、前記ウェーハを前
    記指標面に沿って脆弱化する微小キャビティを充分に形
    成できる最少限のドーズ量であり、また該最大ドーズ
    量、または臨界ドーズ量とは、これ以上であれば、前記
    熱処理段階のときにウェーハの分離が生じるようなドー
    ズ量であり、 −前記熱処理段階の後またはその間に、前記ウェーハを
    前記指標面において２つの部分に分離させる段階が備え
    られ、この分離段階は、ウェーハのそれら２つの部分の
    間に機械的な力を加えることを含み、 前記熱処理段階と前記分離段階との間に、前記薄層を構
    成するより前にウェーハの前記部分に電子部品の少なく
    とも一部または全部を形成する段階を有する、 半導体材
    料薄層製造方法。
  2. 【請求項２】 前記電子部品形成段階が、前記熱処理段
    階の温度より低い温度で行われる様々な相の熱処理を必
    要とする請求項１の半導体材料薄層製造方法。
JP12600597A 1996-05-15 1997-05-15 半導体材料薄層の製造方法 Expired - Lifetime JP3517080B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9606086 1996-05-15
FR9606086A FR2748851B1 (fr) 1996-05-15 1996-05-15 Procede de realisation d'une couche mince de materiau semiconducteur

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2003297987A Division JP4220332B2 (ja) 1996-05-15 2003-08-21 半導体材料の薄層の製造方法

Publications (2)

Publication Number Publication Date
JPH1050628A JPH1050628A (ja) 1998-02-20
JP3517080B2 true JP3517080B2 (ja) 2004-04-05

Family

ID=9492177

Family Applications (2)

Application Number Title Priority Date Filing Date
JP12600597A Expired - Lifetime JP3517080B2 (ja) 1996-05-15 1997-05-15 半導体材料薄層の製造方法
JP2003297987A Expired - Lifetime JP4220332B2 (ja) 1996-05-15 2003-08-21 半導体材料の薄層の製造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2003297987A Expired - Lifetime JP4220332B2 (ja) 1996-05-15 2003-08-21 半導体材料の薄層の製造方法

Country Status (9)

Country Link
US (7) US6020252A (ja)
EP (2) EP0807970B1 (ja)
JP (2) JP3517080B2 (ja)
KR (1) KR100704107B1 (ja)
DE (1) DE69738608T2 (ja)
FR (1) FR2748851B1 (ja)
MY (1) MY125679A (ja)
SG (1) SG52966A1 (ja)
TW (1) TW366527B (ja)

Families Citing this family (430)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW374196B (en) 1996-02-23 1999-11-11 Semiconductor Energy Lab Co Ltd Semiconductor thin film and method for manufacturing the same and semiconductor device and method for manufacturing the same
FR2748851B1 (fr) * 1996-05-15 1998-08-07 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
US8018058B2 (en) * 2004-06-21 2011-09-13 Besang Inc. Semiconductor memory device
US20050280155A1 (en) * 2004-06-21 2005-12-22 Sang-Yun Lee Semiconductor bonding and layer transfer method
US7052941B2 (en) * 2003-06-24 2006-05-30 Sang-Yun Lee Method for making a three-dimensional integrated circuit structure
US8058142B2 (en) * 1996-11-04 2011-11-15 Besang Inc. Bonded semiconductor structure and method of making the same
FR2755537B1 (fr) * 1996-11-05 1999-03-05 Commissariat Energie Atomique Procede de fabrication d'un film mince sur un support et structure ainsi obtenue
SG71094A1 (en) * 1997-03-26 2000-03-21 Canon Kk Thin film formation using laser beam heating to separate layers
US6033974A (en) * 1997-05-12 2000-03-07 Silicon Genesis Corporation Method for controlled cleaving process
US6582999B2 (en) 1997-05-12 2003-06-24 Silicon Genesis Corporation Controlled cleavage process using pressurized fluid
US6013563A (en) 1997-05-12 2000-01-11 Silicon Genesis Corporation Controlled cleaning process
US20070122997A1 (en) 1998-02-19 2007-05-31 Silicon Genesis Corporation Controlled process and resulting device
EP0889505B1 (en) * 1997-07-03 2005-06-08 STMicroelectronics S.r.l. Process for cutting trenches in a single crystal substrate
US6548382B1 (en) 1997-07-18 2003-04-15 Silicon Genesis Corporation Gettering technique for wafers made using a controlled cleaving process
US6534380B1 (en) * 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
US6686623B2 (en) 1997-11-18 2004-02-03 Semiconductor Energy Laboratory Co., Ltd. Nonvolatile memory and electronic apparatus
FR2773261B1 (fr) 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
TW437078B (en) 1998-02-18 2001-05-28 Canon Kk Composite member, its separation method, and preparation method of semiconductor substrate by utilization thereof
US7227176B2 (en) 1998-04-10 2007-06-05 Massachusetts Institute Of Technology Etch stop layer system
JP2000012864A (ja) * 1998-06-22 2000-01-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
US6054370A (en) * 1998-06-30 2000-04-25 Intel Corporation Method of delaminating a pre-fabricated transistor layer from a substrate for placement on another wafer
JP3395661B2 (ja) * 1998-07-07 2003-04-14 信越半導体株式会社 Ｓｏｉウエーハの製造方法
US6271101B1 (en) * 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
DE19837944A1 (de) * 1998-08-21 2000-02-24 Asea Brown Boveri Verfahren zur Fertigung eines Halbleiterbauelements
JP4476390B2 (ja) 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
FR2784795B1 (fr) * 1998-10-16 2000-12-01 Commissariat Energie Atomique Structure comportant une couche mince de materiau composee de zones conductrices et de zones isolantes et procede de fabrication d'une telle structure
FR2784794A1 (fr) * 1998-10-20 2000-04-21 Commissariat Energie Atomique Structure comportant une couche semiconducteur et/ou des elements electroniques sur un support isolant et son procede de fabrication
US6555443B1 (en) * 1998-11-11 2003-04-29 Robert Bosch Gmbh Method for production of a thin film and a thin-film solar cell, in particular, on a carrier substrate
DE19936941B4 (de) * 1998-11-11 2008-11-06 Robert Bosch Gmbh Verfahren zur Herstellung dünner Schichten, insbesondere Dünnschichtsolarzellen, auf einem Trägersubstrat
US20050124142A1 (en) * 1998-12-31 2005-06-09 Bower Robert W. Transposed split of ion cut materials
US6534381B2 (en) * 1999-01-08 2003-03-18 Silicon Genesis Corporation Method for fabricating multi-layered substrates
US6355541B1 (en) * 1999-04-21 2002-03-12 Lockheed Martin Energy Research Corporation Method for transfer of thin-film of silicon carbide via implantation and wafer bonding
JP2001015721A (ja) * 1999-04-30 2001-01-19 Canon Inc 複合部材の分離方法及び薄膜の製造方法
US6162702A (en) * 1999-06-17 2000-12-19 Intersil Corporation Self-supported ultra thin silicon wafer process
FR2795866B1 (fr) 1999-06-30 2001-08-17 Commissariat Energie Atomique Procede de realisation d'une membrane mince et structure a membrane ainsi obtenue
FR2797347B1 (fr) * 1999-08-04 2001-11-23 Commissariat Energie Atomique Procede de transfert d'une couche mince comportant une etape de surfragililisation
AU6905000A (en) * 1999-08-10 2001-03-05 Silicon Genesis Corporation A cleaving process to fabricate multilayered substrates using low implantation doses
US6263941B1 (en) 1999-08-10 2001-07-24 Silicon Genesis Corporation Nozzle for cleaving substrates
US6500732B1 (en) 1999-08-10 2002-12-31 Silicon Genesis Corporation Cleaving process to fabricate multilayered substrates using low implantation doses
FR2797713B1 (fr) 1999-08-20 2002-08-02 Soitec Silicon On Insulator Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
FR2802340B1 (fr) * 1999-12-13 2003-09-05 Commissariat Energie Atomique Structure comportant des cellules photovoltaiques et procede de realisation
JP2001189288A (ja) * 1999-12-20 2001-07-10 Ind Technol Res Inst イオン注入利用の基板ダイシング法
US7427526B2 (en) * 1999-12-20 2008-09-23 The Penn State Research Foundation Deposited thin films and their use in separation and sacrificial layer applications
US6544862B1 (en) 2000-01-14 2003-04-08 Silicon Genesis Corporation Particle distribution method and resulting structure for a layer transfer process
TW452866B (en) * 2000-02-25 2001-09-01 Lee Tien Hsi Manufacturing method of thin film on a substrate
KR100742790B1 (ko) * 2000-04-14 2007-07-25 에스. 오. 이. 떼끄 씰리꽁 오 냉쉴라또흐 떼끄놀로지 특히 반도체 재료(들)로 제조된 기판 또는 잉곳에서 적어도 하나의 박층을 절단하는 방법 및 장치
US6709955B2 (en) * 2000-04-17 2004-03-23 Stmicroelectronics S.R.L. Method of fabricating electronic devices integrated in semiconductor substrates provided with gettering sites, and a device fabricated by the method
FR2809867B1 (fr) 2000-05-30 2003-10-24 Commissariat Energie Atomique Substrat fragilise et procede de fabrication d'un tel substrat
JP3580227B2 (ja) * 2000-06-21 2004-10-20 三菱住友シリコン株式会社 複合基板の分離方法及び分離装置
FR2811807B1 (fr) * 2000-07-12 2003-07-04 Commissariat Energie Atomique Procede de decoupage d'un bloc de materiau et de formation d'un film mince
JP5066321B2 (ja) 2000-08-04 2012-11-07 台湾積體電路製造股▲ふん▼有限公司 モノリシックｏｅｉｃ用埋め込み光電子材料を備えたシリコンウエハ
WO2002015244A2 (en) * 2000-08-16 2002-02-21 Massachusetts Institute Of Technology Process for producing semiconductor article using graded expitaxial growth
FR2816445B1 (fr) * 2000-11-06 2003-07-25 Commissariat Energie Atomique Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible
FR2840731B3 (fr) * 2002-06-11 2004-07-30 Soitec Silicon On Insulator Procede de fabrication d'un substrat comportant une couche utile en materiau semi-conducteur monocristallin de proprietes ameliorees
FR2894990B1 (fr) * 2005-12-21 2008-02-22 Soitec Silicon On Insulator Procede de fabrication de substrats, notamment pour l'optique,l'electronique ou l'optoelectronique et substrat obtenu selon ledit procede
US8507361B2 (en) 2000-11-27 2013-08-13 Soitec Fabrication of substrates with a useful layer of monocrystalline semiconductor material
JP3957038B2 (ja) * 2000-11-28 2007-08-08 シャープ株式会社 半導体基板及びその作製方法
US7094667B1 (en) 2000-12-28 2006-08-22 Bower Robert W Smooth thin film layers produced by low temperature hydrogen ion cut
FR2821697B1 (fr) * 2001-03-02 2004-06-25 Commissariat Energie Atomique Procede de fabrication de couches minces sur un support specifique et une application
JP4749584B2 (ja) * 2001-03-30 2011-08-17 株式会社豊田中央研究所 半導体基板の製造方法
WO2002082514A1 (en) * 2001-04-04 2002-10-17 Massachusetts Institute Of Technology A method for semiconductor device fabrication
FR2823596B1 (fr) * 2001-04-13 2004-08-20 Commissariat Energie Atomique Substrat ou structure demontable et procede de realisation
FR2823599B1 (fr) 2001-04-13 2004-12-17 Commissariat Energie Atomique Substrat demomtable a tenue mecanique controlee et procede de realisation
EP1386349A1 (en) 2001-04-17 2004-02-04 California Institute Of Technology A method of using a germanium layer transfer to si for photovoltaic applications and heterostructure made thereby
US20050026432A1 (en) * 2001-04-17 2005-02-03 Atwater Harry A. Wafer bonded epitaxial templates for silicon heterostructures
US7238622B2 (en) * 2001-04-17 2007-07-03 California Institute Of Technology Wafer bonded virtual substrate and method for forming the same
US7045878B2 (en) * 2001-05-18 2006-05-16 Reveo, Inc. Selectively bonded thin film layer and substrate layer for processing of useful devices
US6956268B2 (en) * 2001-05-18 2005-10-18 Reveo, Inc. MEMS and method of manufacturing MEMS
DE10131249A1 (de) 2001-06-28 2002-05-23 Wacker Siltronic Halbleitermat Verfahren zur Herstellung eines Films oder einer Schicht aus halbleitendem Material
JP4102040B2 (ja) * 2001-07-31 2008-06-18 信越半導体株式会社 Ｓｏｉウェーハの製造方法およびウェーハ分離治具
FR2828762B1 (fr) * 2001-08-14 2003-12-05 Soitec Silicon On Insulator Procede d'obtention d'une couche mince d'un materiau semi-conducteur supportant au moins un composant et/ou circuit electronique
US20090065471A1 (en) * 2003-02-10 2009-03-12 Faris Sadeg M Micro-nozzle, nano-nozzle, manufacturing methods therefor, applications therefor
US6875671B2 (en) * 2001-09-12 2005-04-05 Reveo, Inc. Method of fabricating vertical integrated circuits
US7163826B2 (en) 2001-09-12 2007-01-16 Reveo, Inc Method of fabricating multi layer devices on buried oxide layer substrates
US7033910B2 (en) * 2001-09-12 2006-04-25 Reveo, Inc. Method of fabricating multi layer MEMS and microfluidic devices
US6555451B1 (en) 2001-09-28 2003-04-29 The United States Of America As Represented By The Secretary Of The Navy Method for making shallow diffusion junctions in semiconductors using elemental doping
FR2830983B1 (fr) 2001-10-11 2004-05-14 Commissariat Energie Atomique Procede de fabrication de couches minces contenant des microcomposants
US6593212B1 (en) 2001-10-29 2003-07-15 The United States Of America As Represented By The Secretary Of The Navy Method for making electro-optical devices using a hydrogenion splitting technique
US7309620B2 (en) * 2002-01-11 2007-12-18 The Penn State Research Foundation Use of sacrificial layers in the manufacture of high performance systems on tailored substrates
US6562127B1 (en) 2002-01-16 2003-05-13 The United States Of America As Represented By The Secretary Of The Navy Method of making mosaic array of thin semiconductor material of large substrates
FR2835097B1 (fr) * 2002-01-23 2005-10-14 Procede optimise de report d'une couche mince de carbure de silicium sur un substrat d'accueil
AU2003222003A1 (en) * 2002-03-14 2003-09-29 Amberwave Systems Corporation Methods for fabricating strained layers on semiconductor substrates
US6607969B1 (en) 2002-03-18 2003-08-19 The United States Of America As Represented By The Secretary Of The Navy Method for making pyroelectric, electro-optical and decoupling capacitors using thin film transfer and hydrogen ion splitting techniques
FR2837981B1 (fr) * 2002-03-28 2005-01-07 Commissariat Energie Atomique Procede de manipulation de couches semiconductrices pour leur amincissement
US6767749B2 (en) 2002-04-22 2004-07-27 The United States Of America As Represented By The Secretary Of The Navy Method for making piezoelectric resonator and surface acoustic wave device using hydrogen implant layer splitting
JP4277481B2 (ja) * 2002-05-08 2009-06-10 日本電気株式会社 半導体基板の製造方法、半導体装置の製造方法
US7459025B2 (en) * 2002-06-03 2008-12-02 Tien-Hsi Lee Methods for transferring a layer onto a substrate
US6995430B2 (en) * 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US7307273B2 (en) * 2002-06-07 2007-12-11 Amberwave Systems Corporation Control of strain in device layers by selective relaxation
US7335545B2 (en) * 2002-06-07 2008-02-26 Amberwave Systems Corporation Control of strain in device layers by prevention of relaxation
US20030227057A1 (en) * 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
FR2842650B1 (fr) * 2002-07-17 2005-09-02 Soitec Silicon On Insulator Procede de fabrication de substrats notamment pour l'optique, l'electronique ou l'opto-electronique
US6979630B2 (en) * 2002-08-08 2005-12-27 Isonics Corporation Method and apparatus for transferring a thin layer of semiconductor material
US8187377B2 (en) * 2002-10-04 2012-05-29 Silicon Genesis Corporation Non-contact etch annealing of strained layers
WO2004034453A1 (en) 2002-10-04 2004-04-22 Silicon Genesis Corporation Method for treating semiconductor material
FR2845518B1 (fr) * 2002-10-07 2005-10-14 Commissariat Energie Atomique Realisation d'un substrat semiconducteur demontable et obtention d'un element semiconducteur
FR2845517B1 (fr) * 2002-10-07 2005-05-06 Commissariat Energie Atomique Realisation d'un substrat semiconducteur demontable et obtention d'un element semiconducteur
JP4556158B2 (ja) * 2002-10-22 2010-10-06 株式会社Ｓｕｍｃｏ 貼り合わせｓｏｉ基板の製造方法および半導体装置
US7176108B2 (en) 2002-11-07 2007-02-13 Soitec Silicon On Insulator Method of detaching a thin film at moderate temperature after co-implantation
FR2847075B1 (fr) * 2002-11-07 2005-02-18 Commissariat Energie Atomique Procede de formation d'une zone fragile dans un substrat par co-implantation
US7056815B1 (en) * 2002-11-12 2006-06-06 The Regents Of The University Of Michigan Narrow energy band gap gallium arsenide nitride semi-conductors and an ion-cut-synthesis method for producing the same
FR2848336B1 (fr) 2002-12-09 2005-10-28 Commissariat Energie Atomique Procede de realisation d'une structure contrainte destinee a etre dissociee
US20100133695A1 (en) * 2003-01-12 2010-06-03 Sang-Yun Lee Electronic circuit with embedded memory
FR2850390B1 (fr) * 2003-01-24 2006-07-14 Soitec Silicon On Insulator Procede d'elimination d'une zone peripherique de colle lors de la fabrication d'un substrat composite
US7122095B2 (en) * 2003-03-14 2006-10-17 S.O.I.Tec Silicon On Insulator Technologies S.A. Methods for forming an assembly for transfer of a useful layer
JP4509488B2 (ja) 2003-04-02 2010-07-21 株式会社Ｓｕｍｃｏ 貼り合わせ基板の製造方法
EP1482548B1 (en) 2003-05-26 2016-04-13 Soitec A method of manufacturing a wafer
US8071438B2 (en) * 2003-06-24 2011-12-06 Besang Inc. Semiconductor circuit
FR2856844B1 (fr) 2003-06-24 2006-02-17 Commissariat Energie Atomique Circuit integre sur puce de hautes performances
FR2857953B1 (fr) 2003-07-21 2006-01-13 Commissariat Energie Atomique Structure empilee, et procede pour la fabriquer
FR2859312B1 (fr) * 2003-09-02 2006-02-17 Soitec Silicon On Insulator Scellement metallique multifonction
US8475693B2 (en) * 2003-09-30 2013-07-02 Soitec Methods of making substrate structures having a weakened intermediate layer
FR2861497B1 (fr) * 2003-10-28 2006-02-10 Soitec Silicon On Insulator Procede de transfert catastrophique d'une couche fine apres co-implantation
US7354815B2 (en) * 2003-11-18 2008-04-08 Silicon Genesis Corporation Method for fabricating semiconductor devices using strained silicon bearing material
US7772087B2 (en) 2003-12-19 2010-08-10 Commissariat A L'energie Atomique Method of catastrophic transfer of a thin film after co-implantation
US6992025B2 (en) * 2004-01-12 2006-01-31 Sharp Laboratories Of America, Inc. Strained silicon on insulator from film transfer and relaxation by hydrogen implantation
EP1569263B1 (de) * 2004-02-27 2011-11-23 OSRAM Opto Semiconductors GmbH Verfahren zum Verbinden zweier Wafer
US7390724B2 (en) 2004-04-12 2008-06-24 Silicon Genesis Corporation Method and system for lattice space engineering
WO2005104192A2 (en) * 2004-04-21 2005-11-03 California Institute Of Technology A METHOD FOR THE FABRICATION OF GaAs/Si AND RELATED WAFER BONDED VIRTUAL SUBSTRATES
EP2293326A3 (en) * 2004-06-10 2012-01-25 S.O.I.TEC Silicon on Insulator Technologies S.A. Method for manufacturing a SOI wafer
DE102004030612B3 (de) 2004-06-24 2006-04-20 Siltronic Ag Halbleitersubstrat und Verfahren zu dessen Herstellung
US7094666B2 (en) * 2004-07-29 2006-08-22 Silicon Genesis Corporation Method and system for fabricating strained layers for the manufacture of integrated circuits
WO2006015185A2 (en) * 2004-07-30 2006-02-09 Aonex Technologies, Inc. GaInP/GaAs/Si TRIPLE JUNCTION SOLAR CELL ENABLED BY WAFER BONDING AND LAYER TRANSFER
US7439152B2 (en) * 2004-08-27 2008-10-21 Micron Technology, Inc. Methods of forming a plurality of capacitors
US7202124B2 (en) * 2004-10-01 2007-04-10 Massachusetts Institute Of Technology Strained gettering layers for semiconductor processes
US7846759B2 (en) * 2004-10-21 2010-12-07 Aonex Technologies, Inc. Multi-junction solar cells and methods of making same using layer transfer and bonding techniques
DE102004054564B4 (de) * 2004-11-11 2008-11-27 Siltronic Ag Halbleitersubstrat und Verfahren zu dessen Herstellung
US7393733B2 (en) * 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
US20060113603A1 (en) * 2004-12-01 2006-06-01 Amberwave Systems Corporation Hybrid semiconductor-on-insulator structures and related methods
US7344957B2 (en) * 2005-01-19 2008-03-18 Texas Instruments Incorporated SOI wafer with cooling channels and a method of manufacture thereof
US10374120B2 (en) * 2005-02-18 2019-08-06 Koninklijke Philips N.V. High efficiency solar cells utilizing wafer bonding and layer transfer to integrate non-lattice matched materials
US8367524B2 (en) * 2005-03-29 2013-02-05 Sang-Yun Lee Three-dimensional integrated circuit structure
JP2008535232A (ja) * 2005-03-29 2008-08-28 エス． オー． アイ． テック シリコン オン インシュレーター テクノロジーズ 完全ハイブリッドｓｏｉ型多層構造
US20110143506A1 (en) * 2009-12-10 2011-06-16 Sang-Yun Lee Method for fabricating a semiconductor memory device
TW200707799A (en) * 2005-04-21 2007-02-16 Aonex Technologies Inc Bonded intermediate substrate and method of making same
US20060240275A1 (en) * 2005-04-25 2006-10-26 Gadkaree Kishor P Flexible display substrates
WO2006117900A1 (ja) * 2005-04-26 2006-11-09 Sharp Kabushiki Kaisha 半導体装置の製造方法及び半導体装置
FR2886051B1 (fr) 2005-05-20 2007-08-10 Commissariat Energie Atomique Procede de detachement d'un film mince
US7674687B2 (en) * 2005-07-27 2010-03-09 Silicon Genesis Corporation Method and structure for fabricating multiple tiled regions onto a plate using a controlled cleaving process
FR2889887B1 (fr) 2005-08-16 2007-11-09 Commissariat Energie Atomique Procede de report d'une couche mince sur un support
FR2891281B1 (fr) 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
JP5064695B2 (ja) * 2006-02-16 2012-10-31 信越化学工業株式会社 Ｓｏｉ基板の製造方法
FR2898431B1 (fr) * 2006-03-13 2008-07-25 Soitec Silicon On Insulator Procede de fabrication de film mince
FR2899378B1 (fr) 2006-03-29 2008-06-27 Commissariat Energie Atomique Procede de detachement d'un film mince par fusion de precipites
US20070243703A1 (en) * 2006-04-14 2007-10-18 Aonex Technololgies, Inc. Processes and structures for epitaxial growth on laminate substrates
FR2914110B1 (fr) 2007-03-20 2009-06-05 Soitec Silicon On Insulator Procede de fabrication d'un substrat hybride
US7811900B2 (en) 2006-09-08 2010-10-12 Silicon Genesis Corporation Method and structure for fabricating solar cells using a thick layer transfer process
US9362439B2 (en) 2008-05-07 2016-06-07 Silicon Genesis Corporation Layer transfer of films utilizing controlled shear region
US8293619B2 (en) 2008-08-28 2012-10-23 Silicon Genesis Corporation Layer transfer of films utilizing controlled propagation
US8993410B2 (en) 2006-09-08 2015-03-31 Silicon Genesis Corporation Substrate cleaving under controlled stress conditions
WO2008058252A2 (en) * 2006-11-08 2008-05-15 Silicon China (Hk) Limited System and method for a photovoltaic structure
JP2008153411A (ja) * 2006-12-18 2008-07-03 Shin Etsu Chem Co Ltd Ｓｏｉ基板の製造方法
FR2910179B1 (fr) 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
FR2910702B1 (fr) * 2006-12-26 2009-04-03 Soitec Silicon On Insulator Procede de fabrication d'un substrat mixte
WO2008123116A1 (en) * 2007-03-26 2008-10-16 Semiconductor Energy Laboratory Co., Ltd. Soi substrate and method for manufacturing soi substrate
WO2008123117A1 (en) * 2007-03-26 2008-10-16 Semiconductor Energy Laboratory Co., Ltd. Soi substrate and method for manufacturing soi substrate
SG178762A1 (en) * 2007-04-13 2012-03-29 Semiconductor Energy Lab Display device, method for manufacturing display device, and soi substrate
KR101447048B1 (ko) 2007-04-20 2014-10-06 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Ｓｏｉ 기판 및 반도체장치의 제조방법
US7732301B1 (en) 2007-04-20 2010-06-08 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
US7867805B2 (en) * 2007-05-13 2011-01-11 International Business Machines Corporation Structure replication through ultra thin layer transfer
US9059247B2 (en) * 2007-05-18 2015-06-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate and method for manufacturing semiconductor device
TWI335046B (en) * 2007-05-25 2010-12-21 Univ Nat Taiwan Flexible electronic device and process for the same
US20090278233A1 (en) * 2007-07-26 2009-11-12 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
JP5367330B2 (ja) * 2007-09-14 2013-12-11 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法及び半導体装置の作製方法
US8236668B2 (en) * 2007-10-10 2012-08-07 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
FR2922359B1 (fr) * 2007-10-12 2009-12-18 Commissariat Energie Atomique Procede de fabrication d'une structure micro-electronique impliquant un collage moleculaire
FR2922681A1 (fr) * 2007-10-23 2009-04-24 Soitec Silicon On Insulator Procede de detachement d'un substrat.
JP5548351B2 (ja) * 2007-11-01 2014-07-16 株式会社半導体エネルギー研究所 半導体装置の作製方法
US20090124038A1 (en) * 2007-11-14 2009-05-14 Mark Ewing Tuttle Imager device, camera, and method of manufacturing a back side illuminated imager
JP5464843B2 (ja) 2007-12-03 2014-04-09 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
FR2925221B1 (fr) 2007-12-17 2010-02-19 Commissariat Energie Atomique Procede de transfert d'une couche mince
US20090159111A1 (en) * 2007-12-21 2009-06-25 The Woodside Group Pte. Ltd Photovoltaic device having a textured metal silicide layer
US20090162966A1 (en) * 2007-12-21 2009-06-25 The Woodside Group Pte Ltd Structure and method of formation of a solar cell
US8481845B2 (en) * 2008-02-05 2013-07-09 Gtat Corporation Method to form a photovoltaic cell comprising a thin lamina
US8129613B2 (en) * 2008-02-05 2012-03-06 Twin Creeks Technologies, Inc. Photovoltaic cell comprising a thin lamina having low base resistivity and method of making
US8563352B2 (en) * 2008-02-05 2013-10-22 Gtat Corporation Creation and translation of low-relief texture for a photovoltaic cell
US20090212397A1 (en) * 2008-02-22 2009-08-27 Mark Ewing Tuttle Ultrathin integrated circuit and method of manufacturing an ultrathin integrated circuit
FR2930072B1 (fr) * 2008-04-15 2010-08-20 Commissariat Energie Atomique Procede de transfert d'une couche mince par echange protonique.
US7749884B2 (en) * 2008-05-06 2010-07-06 Astrowatt, Inc. Method of forming an electronic device using a separation-enhancing species
EP2294607A2 (en) * 2008-05-17 2011-03-16 Astrowatt, Inc. Method of forming an electronic device using a separation technique
EP2281302B1 (en) 2008-05-21 2012-12-26 Nxp B.V. A method of manufacturing a bipolar transistor semiconductor device
US8501522B2 (en) 2008-05-30 2013-08-06 Gtat Corporation Intermetal stack for use in a photovoltaic cell
US8049104B2 (en) * 2009-09-30 2011-11-01 Twin Creek Technologies, Inc. Intermetal stack for use in a photovoltaic cell
US8207590B2 (en) * 2008-07-03 2012-06-26 Samsung Electronics Co., Ltd. Image sensor, substrate for the same, image sensing device including the image sensor, and associated methods
US7902091B2 (en) * 2008-08-13 2011-03-08 Varian Semiconductor Equipment Associates, Inc. Cleaving of substrates
US8330126B2 (en) 2008-08-25 2012-12-11 Silicon Genesis Corporation Race track configuration and method for wafering silicon solar substrates
CN102099894B (zh) * 2008-08-27 2014-04-16 S.O.I.Tec绝缘体上硅技术公司 制造半导体结构或使用具有选择或受控晶格参数的半导体材料层的器件的方法
US8815618B2 (en) 2008-08-29 2014-08-26 Tsmc Solid State Lighting Ltd. Light-emitting diode on a conductive substrate
FR2935535B1 (fr) * 2008-09-02 2010-12-10 S O I Tec Silicon On Insulator Tech Procede de detourage mixte.
EP2329517A1 (en) * 2008-09-24 2011-06-08 S.O.I.Tec Silicon on Insulator Technologies Methods of forming relaxed layers of semiconductor materials, semiconductor structures, devices and engineered substrates including same
JP5907730B2 (ja) 2008-10-30 2016-04-26 エス・オー・アイ・テック・シリコン・オン・インシュレーター・テクノロジーズ 低減した格子ひずみを備えた半導体材料、同様に包含する半導体構造体、デバイス、および、加工された基板を製造する方法
US8637383B2 (en) 2010-12-23 2014-01-28 Soitec Strain relaxation using metal materials and related structures
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
FR2942073B1 (fr) * 2009-02-10 2011-04-29 Soitec Silicon On Insulator Procede de realisation d'une couche de cavites
US9711407B2 (en) * 2009-04-14 2017-07-18 Monolithic 3D Inc. Method of manufacturing a three dimensional integrated circuit by transfer of a mono-crystalline layer
US8362482B2 (en) 2009-04-14 2013-01-29 Monolithic 3D Inc. Semiconductor device and structure
US8405420B2 (en) * 2009-04-14 2013-03-26 Monolithic 3D Inc. System comprising a semiconductor device and structure
US8427200B2 (en) 2009-04-14 2013-04-23 Monolithic 3D Inc. 3D semiconductor device
US9577642B2 (en) 2009-04-14 2017-02-21 Monolithic 3D Inc. Method to form a 3D semiconductor device
US8384426B2 (en) 2009-04-14 2013-02-26 Monolithic 3D Inc. Semiconductor device and structure
US8378715B2 (en) 2009-04-14 2013-02-19 Monolithic 3D Inc. Method to construct systems
US8362800B2 (en) 2010-10-13 2013-01-29 Monolithic 3D Inc. 3D semiconductor device including field repairable logics
US8058137B1 (en) 2009-04-14 2011-11-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8373439B2 (en) 2009-04-14 2013-02-12 Monolithic 3D Inc. 3D semiconductor device
US9509313B2 (en) 2009-04-14 2016-11-29 Monolithic 3D Inc. 3D semiconductor device
US8258810B2 (en) 2010-09-30 2012-09-04 Monolithic 3D Inc. 3D semiconductor device
US8669778B1 (en) 2009-04-14 2014-03-11 Monolithic 3D Inc. Method for design and manufacturing of a 3D semiconductor device
US8395191B2 (en) * 2009-10-12 2013-03-12 Monolithic 3D Inc. Semiconductor device and structure
US7986042B2 (en) 2009-04-14 2011-07-26 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US20110031997A1 (en) * 2009-04-14 2011-02-10 NuPGA Corporation Method for fabrication of a semiconductor device and structure
US8754533B2 (en) * 2009-04-14 2014-06-17 Monolithic 3D Inc. Monolithic three-dimensional semiconductor device and structure
US8329557B2 (en) 2009-05-13 2012-12-11 Silicon Genesis Corporation Techniques for forming thin films by implantation with reduced channeling
US20110048517A1 (en) * 2009-06-09 2011-03-03 International Business Machines Corporation Multijunction Photovoltaic Cell Fabrication
US20100310775A1 (en) * 2009-06-09 2010-12-09 International Business Machines Corporation Spalling for a Semiconductor Substrate
US8633097B2 (en) 2009-06-09 2014-01-21 International Business Machines Corporation Single-junction photovoltaic cell
US8703521B2 (en) * 2009-06-09 2014-04-22 International Business Machines Corporation Multijunction photovoltaic cell fabrication
US8802477B2 (en) * 2009-06-09 2014-08-12 International Business Machines Corporation Heterojunction III-V photovoltaic cell fabrication
US7807570B1 (en) 2009-06-11 2010-10-05 International Business Machines Corporation Local metallization and use thereof in semiconductor devices
FR2947098A1 (fr) 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
US20110089429A1 (en) * 2009-07-23 2011-04-21 Venkatraman Prabhakar Systems, methods and materials involving crystallization of substrates using a seed layer, as well as products produced by such processes
US8361890B2 (en) * 2009-07-28 2013-01-29 Gigasi Solar, Inc. Systems, methods and materials including crystallization of substrates via sub-melt laser anneal, as well as products produced by such processes
US8148237B2 (en) * 2009-08-07 2012-04-03 Varian Semiconductor Equipment Associates, Inc. Pressurized treatment of substrates to enhance cleaving process
WO2011020124A2 (en) * 2009-08-14 2011-02-17 Gigasi Solar, Inc. Backside only contact thin-film solar cells and devices, systems and methods of fabricating same, and products produced by processes thereof
FR2949606B1 (fr) 2009-08-26 2011-10-28 Commissariat Energie Atomique Procede de detachement par fracture d'un film mince de silicium mettant en oeuvre une triple implantation
US20110073175A1 (en) * 2009-09-29 2011-03-31 Twin Creeks Technologies, Inc. Photovoltaic cell comprising a thin lamina having emitter formed at light-facing and back surfaces
US10366970B2 (en) 2009-10-12 2019-07-30 Monolithic 3D Inc. 3D semiconductor device and structure
US10910364B2 (en) 2009-10-12 2021-02-02 Monolitaic 3D Inc. 3D semiconductor device
US10157909B2 (en) 2009-10-12 2018-12-18 Monolithic 3D Inc. 3D semiconductor device and structure
US8581349B1 (en) 2011-05-02 2013-11-12 Monolithic 3D Inc. 3D memory semiconductor device and structure
US10354995B2 (en) 2009-10-12 2019-07-16 Monolithic 3D Inc. Semiconductor memory device and structure
US11018133B2 (en) 2009-10-12 2021-05-25 Monolithic 3D Inc. 3D integrated circuit
US8294159B2 (en) 2009-10-12 2012-10-23 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8476145B2 (en) 2010-10-13 2013-07-02 Monolithic 3D Inc. Method of fabricating a semiconductor device and structure
US10388863B2 (en) 2009-10-12 2019-08-20 Monolithic 3D Inc. 3D memory device and structure
US10043781B2 (en) 2009-10-12 2018-08-07 Monolithic 3D Inc. 3D semiconductor device and structure
US8742476B1 (en) 2012-11-27 2014-06-03 Monolithic 3D Inc. Semiconductor device and structure
US9099424B1 (en) 2012-08-10 2015-08-04 Monolithic 3D Inc. Semiconductor system, device and structure with heat removal
US8536023B2 (en) 2010-11-22 2013-09-17 Monolithic 3D Inc. Method of manufacturing a semiconductor device and structure
US8450804B2 (en) 2011-03-06 2013-05-28 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US11374118B2 (en) 2009-10-12 2022-06-28 Monolithic 3D Inc. Method to form a 3D integrated circuit
WO2011061580A1 (en) 2009-11-18 2011-05-26 S.O.I.Tec Silicon On Insulator Technologies Methods of fabricating semiconductor structures and devices using glass bonding layers, and semiconductor structures and devices formed by such methods
WO2011066485A2 (en) * 2009-11-25 2011-06-03 Gigasi Solar, Inc. Systems, methods and products including features of laser irradiation and/or cleaving of silicon with other substrates or layers
US8298908B2 (en) 2010-02-11 2012-10-30 International Business Machines Corporation Structure and method for forming isolation and buried plate for trench capacitor
US8026521B1 (en) 2010-10-11 2011-09-27 Monolithic 3D Inc. Semiconductor device and structure
US8541819B1 (en) 2010-12-09 2013-09-24 Monolithic 3D Inc. Semiconductor device and structure
US8492886B2 (en) 2010-02-16 2013-07-23 Monolithic 3D Inc 3D integrated circuit with logic
US8298875B1 (en) 2011-03-06 2012-10-30 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8373230B1 (en) 2010-10-13 2013-02-12 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8461035B1 (en) 2010-09-30 2013-06-11 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US9099526B2 (en) 2010-02-16 2015-08-04 Monolithic 3D Inc. Integrated circuit device and structure
US8349626B2 (en) * 2010-03-23 2013-01-08 Gtat Corporation Creation of low-relief texture for a photovoltaic cell
JP2011216543A (ja) * 2010-03-31 2011-10-27 Ube Industries Ltd 発光ダイオード、それに用いられる発光ダイオード用基板及びその製造方法
US8445358B2 (en) * 2010-03-31 2013-05-21 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device
FR2961515B1 (fr) 2010-06-22 2012-08-24 Commissariat Energie Atomique Procede de realisation d'une couche mince de silicium monocristallin sur une couche de polymere
FR2961948B1 (fr) * 2010-06-23 2012-08-03 Soitec Silicon On Insulator Procede de traitement d'une piece en materiau compose
KR101134819B1 (ko) 2010-07-02 2012-04-13 이상윤 반도체 메모리 장치의 제조 방법
US10217667B2 (en) 2011-06-28 2019-02-26 Monolithic 3D Inc. 3D semiconductor device, fabrication method and system
US8642416B2 (en) 2010-07-30 2014-02-04 Monolithic 3D Inc. Method of forming three dimensional integrated circuit devices using layer transfer technique
US8901613B2 (en) 2011-03-06 2014-12-02 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US9219005B2 (en) 2011-06-28 2015-12-22 Monolithic 3D Inc. Semiconductor system and device
US9953925B2 (en) 2011-06-28 2018-04-24 Monolithic 3D Inc. Semiconductor system and device
JP5917036B2 (ja) 2010-08-05 2016-05-11 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
US8273610B2 (en) 2010-11-18 2012-09-25 Monolithic 3D Inc. Method of constructing a semiconductor device and structure
US10497713B2 (en) 2010-11-18 2019-12-03 Monolithic 3D Inc. 3D semiconductor memory device and structure
US8163581B1 (en) 2010-10-13 2012-04-24 Monolith IC 3D Semiconductor and optoelectronic devices
US11482440B2 (en) 2010-12-16 2022-10-25 Monolithic 3D Inc. 3D semiconductor device and structure with a built-in test circuit for repairing faulty circuits
US11257867B1 (en) 2010-10-11 2022-02-22 Monolithic 3D Inc. 3D semiconductor device and structure with oxide bonds
US11018191B1 (en) 2010-10-11 2021-05-25 Monolithic 3D Inc. 3D semiconductor device and structure
US11158674B2 (en) 2010-10-11 2021-10-26 Monolithic 3D Inc. Method to produce a 3D semiconductor device and structure
US10290682B2 (en) 2010-10-11 2019-05-14 Monolithic 3D Inc. 3D IC semiconductor device and structure with stacked memory
US11227897B2 (en) 2010-10-11 2022-01-18 Monolithic 3D Inc. Method for producing a 3D semiconductor memory device and structure
US11024673B1 (en) 2010-10-11 2021-06-01 Monolithic 3D Inc. 3D semiconductor device and structure
US11315980B1 (en) 2010-10-11 2022-04-26 Monolithic 3D Inc. 3D semiconductor device and structure with transistors
US11600667B1 (en) 2010-10-11 2023-03-07 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US11469271B2 (en) 2010-10-11 2022-10-11 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US10896931B1 (en) 2010-10-11 2021-01-19 Monolithic 3D Inc. 3D semiconductor device and structure
US8114757B1 (en) 2010-10-11 2012-02-14 Monolithic 3D Inc. Semiconductor device and structure
US10978501B1 (en) 2010-10-13 2021-04-13 Monolithic 3D Inc. Multilevel semiconductor device and structure with waveguides
US11605663B2 (en) 2010-10-13 2023-03-14 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11404466B2 (en) 2010-10-13 2022-08-02 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11164898B2 (en) 2010-10-13 2021-11-02 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11043523B1 (en) 2010-10-13 2021-06-22 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US8283215B2 (en) 2010-10-13 2012-10-09 Monolithic 3D Inc. Semiconductor and optoelectronic devices
US11437368B2 (en) 2010-10-13 2022-09-06 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11869915B2 (en) 2010-10-13 2024-01-09 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11133344B2 (en) 2010-10-13 2021-09-28 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US10998374B1 (en) 2010-10-13 2021-05-04 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11855114B2 (en) 2010-10-13 2023-12-26 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US10679977B2 (en) 2010-10-13 2020-06-09 Monolithic 3D Inc. 3D microdisplay device and structure
US10943934B2 (en) 2010-10-13 2021-03-09 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11063071B1 (en) 2010-10-13 2021-07-13 Monolithic 3D Inc. Multilevel semiconductor device and structure with waveguides
US11694922B2 (en) 2010-10-13 2023-07-04 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11855100B2 (en) 2010-10-13 2023-12-26 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11929372B2 (en) 2010-10-13 2024-03-12 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11327227B2 (en) 2010-10-13 2022-05-10 Monolithic 3D Inc. Multilevel semiconductor device and structure with electromagnetic modulators
US8379458B1 (en) 2010-10-13 2013-02-19 Monolithic 3D Inc. Semiconductor device and structure
US10833108B2 (en) 2010-10-13 2020-11-10 Monolithic 3D Inc. 3D microdisplay device and structure
US11163112B2 (en) 2010-10-13 2021-11-02 Monolithic 3D Inc. Multilevel semiconductor device and structure with electromagnetic modulators
US9197804B1 (en) 2011-10-14 2015-11-24 Monolithic 3D Inc. Semiconductor and optoelectronic devices
US11901210B2 (en) 2010-11-18 2024-02-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11164770B1 (en) 2010-11-18 2021-11-02 Monolithic 3D Inc. Method for producing a 3D semiconductor memory device and structure
US11521888B2 (en) 2010-11-18 2022-12-06 Monolithic 3D Inc. 3D semiconductor device and structure with high-k metal gate transistors
US11784082B2 (en) 2010-11-18 2023-10-10 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11482439B2 (en) 2010-11-18 2022-10-25 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors
US11094576B1 (en) 2010-11-18 2021-08-17 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11355381B2 (en) 2010-11-18 2022-06-07 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11355380B2 (en) 2010-11-18 2022-06-07 Monolithic 3D Inc. Methods for producing 3D semiconductor memory device and structure utilizing alignment marks
US11923230B1 (en) 2010-11-18 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11482438B2 (en) 2010-11-18 2022-10-25 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11495484B2 (en) 2010-11-18 2022-11-08 Monolithic 3D Inc. 3D semiconductor devices and structures with at least two single-crystal layers
US11031275B2 (en) 2010-11-18 2021-06-08 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11107721B2 (en) 2010-11-18 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure with NAND logic
US11004719B1 (en) 2010-11-18 2021-05-11 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11569117B2 (en) 2010-11-18 2023-01-31 Monolithic 3D Inc. 3D semiconductor device and structure with single-crystal layers
US11508605B2 (en) 2010-11-18 2022-11-22 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11735462B2 (en) 2010-11-18 2023-08-22 Monolithic 3D Inc. 3D semiconductor device and structure with single-crystal layers
US11211279B2 (en) 2010-11-18 2021-12-28 Monolithic 3D Inc. Method for processing a 3D integrated circuit and structure
US11443971B2 (en) 2010-11-18 2022-09-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11862503B2 (en) 2010-11-18 2024-01-02 Monolithic 3D Inc. Method for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11018042B1 (en) 2010-11-18 2021-05-25 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11854857B1 (en) 2010-11-18 2023-12-26 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11610802B2 (en) 2010-11-18 2023-03-21 Monolithic 3D Inc. Method for producing a 3D semiconductor device and structure with single crystal transistors and metal gate electrodes
US11804396B2 (en) 2010-11-18 2023-10-31 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11615977B2 (en) 2010-11-18 2023-03-28 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11121021B2 (en) 2010-11-18 2021-09-14 Monolithic 3D Inc. 3D semiconductor device and structure
US8975670B2 (en) 2011-03-06 2015-03-10 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US10388568B2 (en) 2011-06-28 2019-08-20 Monolithic 3D Inc. 3D semiconductor device and system
FR2978600B1 (fr) 2011-07-25 2014-02-07 Soitec Silicon On Insulator Procede et dispositif de fabrication de couche de materiau semi-conducteur
US8841742B2 (en) 2011-09-27 2014-09-23 Soitec Low temperature layer transfer process using donor structure with material in recesses in transfer layer, semiconductor structures fabricated using such methods
US8673733B2 (en) * 2011-09-27 2014-03-18 Soitec Methods of transferring layers of material in 3D integration processes and related structures and devices
TWI573198B (zh) * 2011-09-27 2017-03-01 索泰克公司 在三度空間集積製程中轉移材料層之方法及其相關結構與元件
US8687399B2 (en) 2011-10-02 2014-04-01 Monolithic 3D Inc. Semiconductor device and structure
US9029173B2 (en) 2011-10-18 2015-05-12 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
FR2984597B1 (fr) * 2011-12-20 2016-07-29 Commissariat Energie Atomique Fabrication d’une structure souple par transfert de couches
AU2013222069A1 (en) 2012-02-26 2014-10-16 Solexel, Inc. Systems and methods for laser splitting and device layer transfer
US9000557B2 (en) 2012-03-17 2015-04-07 Zvi Or-Bach Semiconductor device and structure
US11410912B2 (en) 2012-04-09 2022-08-09 Monolithic 3D Inc. 3D semiconductor device with vias and isolation layers
US8557632B1 (en) 2012-04-09 2013-10-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US11881443B2 (en) 2012-04-09 2024-01-23 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11735501B1 (en) 2012-04-09 2023-08-22 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US10600888B2 (en) 2012-04-09 2020-03-24 Monolithic 3D Inc. 3D semiconductor device
US11088050B2 (en) 2012-04-09 2021-08-10 Monolithic 3D Inc. 3D semiconductor device with isolation layers
US11694944B1 (en) 2012-04-09 2023-07-04 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11476181B1 (en) 2012-04-09 2022-10-18 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11164811B2 (en) 2012-04-09 2021-11-02 Monolithic 3D Inc. 3D semiconductor device with isolation layers and oxide-to-oxide bonding
US11616004B1 (en) 2012-04-09 2023-03-28 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11594473B2 (en) 2012-04-09 2023-02-28 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
WO2014020387A1 (en) 2012-07-31 2014-02-06 Soitec Methods of forming semiconductor structures including mems devices and integrated circuits on opposing sides of substrates, and related structures and devices
US8686428B1 (en) 2012-11-16 2014-04-01 Monolithic 3D Inc. Semiconductor device and structure
US8574929B1 (en) 2012-11-16 2013-11-05 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US11784169B2 (en) 2012-12-22 2023-10-10 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11018116B2 (en) 2012-12-22 2021-05-25 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US11309292B2 (en) 2012-12-22 2022-04-19 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11916045B2 (en) 2012-12-22 2024-02-27 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US8674470B1 (en) 2012-12-22 2014-03-18 Monolithic 3D Inc. Semiconductor device and structure
US11063024B1 (en) 2012-12-22 2021-07-13 Monlithic 3D Inc. Method to form a 3D semiconductor device and structure
US11961827B1 (en) 2012-12-22 2024-04-16 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11967583B2 (en) 2012-12-22 2024-04-23 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11217565B2 (en) 2012-12-22 2022-01-04 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US9281233B2 (en) * 2012-12-28 2016-03-08 Sunedison Semiconductor Limited Method for low temperature layer transfer in the preparation of multilayer semiconductor devices
US10115663B2 (en) 2012-12-29 2018-10-30 Monolithic 3D Inc. 3D semiconductor device and structure
US10903089B1 (en) 2012-12-29 2021-01-26 Monolithic 3D Inc. 3D semiconductor device and structure
US10600657B2 (en) 2012-12-29 2020-03-24 Monolithic 3D Inc 3D semiconductor device and structure
US9871034B1 (en) 2012-12-29 2018-01-16 Monolithic 3D Inc. Semiconductor device and structure
US11430667B2 (en) 2012-12-29 2022-08-30 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11177140B2 (en) 2012-12-29 2021-11-16 Monolithic 3D Inc. 3D semiconductor device and structure
US10651054B2 (en) 2012-12-29 2020-05-12 Monolithic 3D Inc. 3D semiconductor device and structure
US11430668B2 (en) 2012-12-29 2022-08-30 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11087995B1 (en) 2012-12-29 2021-08-10 Monolithic 3D Inc. 3D semiconductor device and structure
US10892169B2 (en) 2012-12-29 2021-01-12 Monolithic 3D Inc. 3D semiconductor device and structure
US9385058B1 (en) 2012-12-29 2016-07-05 Monolithic 3D Inc. Semiconductor device and structure
US11004694B1 (en) 2012-12-29 2021-05-11 Monolithic 3D Inc. 3D semiconductor device and structure
US11935949B1 (en) 2013-03-11 2024-03-19 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US10325651B2 (en) 2013-03-11 2019-06-18 Monolithic 3D Inc. 3D semiconductor device with stacked memory
US11869965B2 (en) 2013-03-11 2024-01-09 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US8902663B1 (en) 2013-03-11 2014-12-02 Monolithic 3D Inc. Method of maintaining a memory state
US11088130B2 (en) 2014-01-28 2021-08-10 Monolithic 3D Inc. 3D semiconductor device and structure
US8994404B1 (en) 2013-03-12 2015-03-31 Monolithic 3D Inc. Semiconductor device and structure
US11398569B2 (en) 2013-03-12 2022-07-26 Monolithic 3D Inc. 3D semiconductor device and structure
US10840239B2 (en) 2014-08-26 2020-11-17 Monolithic 3D Inc. 3D semiconductor device and structure
US11923374B2 (en) 2013-03-12 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US9117749B1 (en) 2013-03-15 2015-08-25 Monolithic 3D Inc. Semiconductor device and structure
US10224279B2 (en) 2013-03-15 2019-03-05 Monolithic 3D Inc. Semiconductor device and structure
US9021414B1 (en) 2013-04-15 2015-04-28 Monolithic 3D Inc. Automation for monolithic 3D devices
US11574109B1 (en) 2013-04-15 2023-02-07 Monolithic 3D Inc Automation methods for 3D integrated circuits and devices
US11341309B1 (en) 2013-04-15 2022-05-24 Monolithic 3D Inc. Automation for monolithic 3D devices
US11270055B1 (en) 2013-04-15 2022-03-08 Monolithic 3D Inc. Automation for monolithic 3D devices
US11030371B2 (en) 2013-04-15 2021-06-08 Monolithic 3D Inc. Automation for monolithic 3D devices
US11720736B2 (en) 2013-04-15 2023-08-08 Monolithic 3D Inc. Automation methods for 3D integrated circuits and devices
US11487928B2 (en) 2013-04-15 2022-11-01 Monolithic 3D Inc. Automation for monolithic 3D devices
US9627287B2 (en) * 2013-10-18 2017-04-18 Infineon Technologies Ag Thinning in package using separation structure as stop
WO2015069452A1 (en) * 2013-11-05 2015-05-14 Applied Materials, Inc. Methods and apparatus for thin-film substrate formation
JP6131179B2 (ja) * 2013-12-06 2017-05-17 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
US11031394B1 (en) 2014-01-28 2021-06-08 Monolithic 3D Inc. 3D semiconductor device and structure
US10297586B2 (en) 2015-03-09 2019-05-21 Monolithic 3D Inc. Methods for processing a 3D semiconductor device
US11107808B1 (en) 2014-01-28 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure
WO2015119742A1 (en) 2014-02-07 2015-08-13 Sunedison Semiconductor Limited Methods for preparing layered semiconductor structures
US11011507B1 (en) 2015-04-19 2021-05-18 Monolithic 3D Inc. 3D semiconductor device and structure
US10381328B2 (en) 2015-04-19 2019-08-13 Monolithic 3D Inc. Semiconductor device and structure
US11056468B1 (en) 2015-04-19 2021-07-06 Monolithic 3D Inc. 3D semiconductor device and structure
US10825779B2 (en) 2015-04-19 2020-11-03 Monolithic 3D Inc. 3D semiconductor device and structure
US11956952B2 (en) 2015-08-23 2024-04-09 Monolithic 3D Inc. Semiconductor memory device and structure
CN106548972B (zh) * 2015-09-18 2019-02-26 胡兵 一种将半导体衬底主体与其上功能层进行分离的方法
WO2017053329A1 (en) 2015-09-21 2017-03-30 Monolithic 3D Inc 3d semiconductor device and structure
US11978731B2 (en) 2015-09-21 2024-05-07 Monolithic 3D Inc. Method to produce a multi-level semiconductor memory device and structure
US10522225B1 (en) 2015-10-02 2019-12-31 Monolithic 3D Inc. Semiconductor device with non-volatile memory
US11296115B1 (en) 2015-10-24 2022-04-05 Monolithic 3D Inc. 3D semiconductor device and structure
US10418369B2 (en) 2015-10-24 2019-09-17 Monolithic 3D Inc. Multi-level semiconductor memory device and structure
US11114464B2 (en) 2015-10-24 2021-09-07 Monolithic 3D Inc. 3D semiconductor device and structure
US10847540B2 (en) 2015-10-24 2020-11-24 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11114427B2 (en) 2015-11-07 2021-09-07 Monolithic 3D Inc. 3D semiconductor processor and memory device and structure
US11937422B2 (en) 2015-11-07 2024-03-19 Monolithic 3D Inc. Semiconductor memory device and structure
FR3051971B1 (fr) * 2016-05-30 2019-12-13 Soitec Procede de fabrication d'une structure semi-conductrice comprenant un interposeur
US11329059B1 (en) 2016-10-10 2022-05-10 Monolithic 3D Inc. 3D memory devices and structures with thinned single crystal substrates
US11711928B2 (en) 2016-10-10 2023-07-25 Monolithic 3D Inc. 3D memory devices and structures with control circuits
US11930648B1 (en) 2016-10-10 2024-03-12 Monolithic 3D Inc. 3D memory devices and structures with metal layers
US11251149B2 (en) 2016-10-10 2022-02-15 Monolithic 3D Inc. 3D memory device and structure
US11812620B2 (en) 2016-10-10 2023-11-07 Monolithic 3D Inc. 3D DRAM memory devices and structures with control circuits
US11869591B2 (en) 2016-10-10 2024-01-09 Monolithic 3D Inc. 3D memory devices and structures with control circuits
FR3074960B1 (fr) 2017-12-07 2019-12-06 Soitec Procede de transfert d'une couche utilisant une structure demontable
US20200194555A1 (en) 2018-12-18 2020-06-18 United Microelectronics Corp. Semiconductor device with reduced floating body effects and fabrication method thereof
US10892016B1 (en) 2019-04-08 2021-01-12 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11158652B1 (en) 2019-04-08 2021-10-26 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11018156B2 (en) 2019-04-08 2021-05-25 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11763864B2 (en) 2019-04-08 2023-09-19 Monolithic 3D Inc. 3D memory semiconductor devices and structures with bit-line pillars
US11296106B2 (en) 2019-04-08 2022-04-05 Monolithic 3D Inc. 3D memory semiconductor devices and structures
KR102271268B1 (ko) * 2019-09-20 2021-06-30 재단법인대구경북과학기술원 전자장치 제조방법
FR3108439B1 (fr) 2020-03-23 2022-02-11 Soitec Silicon On Insulator Procede de fabrication d’une structure empilee
FR3109016B1 (fr) 2020-04-01 2023-12-01 Soitec Silicon On Insulator Structure demontable et procede de transfert d’une couche mettant en œuvre ladite structure demontable

Family Cites Families (130)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3915757A (en) * 1972-08-09 1975-10-28 Niels N Engel Ion plating method and product therefrom
US3913520A (en) * 1972-08-14 1975-10-21 Precision Thin Film Corp High vacuum deposition apparatus
US3993909A (en) * 1973-03-16 1976-11-23 U.S. Philips Corporation Substrate holder for etching thin films
FR2245779B1 (ja) * 1973-09-28 1978-02-10 Cit Alcatel
US3901423A (en) * 1973-11-26 1975-08-26 Purdue Research Foundation Method for fracturing crystalline materials
US4170662A (en) * 1974-11-05 1979-10-09 Eastman Kodak Company Plasma plating
US4121334A (en) 1974-12-17 1978-10-24 P. R. Mallory & Co. Inc. Application of field-assisted bonding to the mass production of silicon type pressure transducers
US3957107A (en) * 1975-02-27 1976-05-18 The United States Of America As Represented By The Secretary Of The Air Force Thermal switch
US4039416A (en) * 1975-04-21 1977-08-02 White Gerald W Gasless ion plating
GB1542299A (en) 1976-03-23 1979-03-14 Warner Lambert Co Blade shields
US4028149A (en) * 1976-06-30 1977-06-07 Ibm Corporation Process for forming monocrystalline silicon carbide on silicon substrates
US4074139A (en) 1976-12-27 1978-02-14 Rca Corporation Apparatus and method for maskless ion implantation
JPS53104156A (en) 1977-02-23 1978-09-11 Hitachi Ltd Manufacture for semiconductor device
US4108751A (en) * 1977-06-06 1978-08-22 King William J Ion beam implantation-sputtering
US4179324A (en) 1977-11-28 1979-12-18 Spire Corporation Process for fabricating thin film and glass sheet laminate
DE2849184A1 (de) 1978-11-13 1980-05-22 Bbc Brown Boveri & Cie Verfahren zur herstellung eines scheibenfoermigen silizium-halbleiterbauelementes mit negativer anschraegung
JPS55104057A (en) 1979-02-02 1980-08-09 Hitachi Ltd Ion implantation device
CH640886A5 (de) * 1979-08-02 1984-01-31 Balzers Hochvakuum Verfahren zum aufbringen harter verschleissfester ueberzuege auf unterlagen.
US4244348A (en) * 1979-09-10 1981-01-13 Atlantic Richfield Company Process for cleaving crystalline materials
FR2506344B2 (fr) * 1980-02-01 1986-07-11 Commissariat Energie Atomique Procede de dopage de semi-conducteurs
FR2475068B1 (fr) 1980-02-01 1986-05-16 Commissariat Energie Atomique Procede de dopage de semi-conducteurs
US4342631A (en) 1980-06-16 1982-08-03 Illinois Tool Works Inc. Gasless ion plating process and apparatus
US4471003A (en) 1980-11-25 1984-09-11 Cann Gordon L Magnetoplasmadynamic apparatus and process for the separation and deposition of materials
FR2501727A1 (fr) * 1981-03-13 1982-09-17 Vide Traitement Procede de traitements thermochimiques de metaux par bombardement ionique
US4361600A (en) * 1981-11-12 1982-11-30 General Electric Company Method of making integrated circuits
US4412868A (en) 1981-12-23 1983-11-01 General Electric Company Method of making integrated circuits utilizing ion implantation and selective epitaxial growth
US4486247A (en) 1982-06-21 1984-12-04 Westinghouse Electric Corp. Wear resistant steel articles with carbon, oxygen and nitrogen implanted in the surface thereof
FR2529383A1 (fr) * 1982-06-24 1983-12-30 Commissariat Energie Atomique Porte-cible a balayage mecanique utilisable notamment pour l'implantation d'ioris
JPS5954217A (ja) 1982-09-21 1984-03-29 Nec Corp 半導体基板の製造方法
FR2537768A1 (fr) * 1982-12-08 1984-06-15 Commissariat Energie Atomique Procede et dispositif d'obtention de faisceaux de particules de densite spatialement modulee, application a la gravure et a l'implantation ioniques
FR2537777A1 (fr) * 1982-12-10 1984-06-15 Commissariat Energie Atomique Procede et dispositif d'implantation de particules dans un solide
DE3246480A1 (de) 1982-12-15 1984-06-20 Wacker-Chemitronic Gesellschaft für Elektronik-Grundstoffe mbH, 8263 Burghausen Verfahren zur herstellung von halbleiterscheiben mit getternder scheibenrueckseite
US4500563A (en) * 1982-12-15 1985-02-19 Pacific Western Systems, Inc. Independently variably controlled pulsed R.F. plasma chemical vapor processing
US4468309A (en) * 1983-04-22 1984-08-28 White Engineering Corporation Method for resisting galling
GB2144343A (en) * 1983-08-02 1985-03-06 Standard Telephones Cables Ltd Optical fibre manufacture
US4567505A (en) 1983-10-27 1986-01-28 The Board Of Trustees Of The Leland Stanford Junior University Heat sink and method of attaching heat sink to a semiconductor integrated circuit and the like
JPS6088535U (ja) * 1983-11-24 1985-06-18 住友電気工業株式会社 半導体ウエハ
SU1282757A1 (ru) 1983-12-30 2000-06-27 Институт Ядерной Физики Ан Казсср Способ изготовления тонких пластин кремния
FR2558263B1 (fr) 1984-01-12 1986-04-25 Commissariat Energie Atomique Accelerometre directif et son procede de fabrication par microlithographie
GB2155024A (en) 1984-03-03 1985-09-18 Standard Telephones Cables Ltd Surface treatment of plastics materials
FR2563377B1 (fr) 1984-04-19 1987-01-23 Commissariat Energie Atomique Procede de fabrication d'une couche isolante enterree dans un substrat semi-conducteur, par implantation ionique
US4542863A (en) * 1984-07-23 1985-09-24 Larson Edwin L Pipe-thread sealing tape reel with tape retarding element
US4566403A (en) * 1985-01-30 1986-01-28 Sovonics Solar Systems Apparatus for microwave glow discharge deposition
US4837172A (en) 1986-07-18 1989-06-06 Matsushita Electric Industrial Co., Ltd. Method for removing impurities existing in semiconductor substrate
US4717683A (en) 1986-09-23 1988-01-05 Motorola Inc. CMOS process
US4764394A (en) 1987-01-20 1988-08-16 Wisconsin Alumni Research Foundation Method and apparatus for plasma source ion implantation
JPS63254762A (ja) 1987-04-13 1988-10-21 Nissan Motor Co Ltd Ｃｍｏｓ半導体装置
US4847792A (en) 1987-05-04 1989-07-11 Texas Instruments Incorporated Process and apparatus for detecting aberrations in production process operations
SE458398B (sv) 1987-05-27 1989-03-20 H Biverot Ljusdetekterande och ljusriktningsbestaemmande anordning
FR2616590B1 (fr) 1987-06-15 1990-03-02 Commissariat Energie Atomique Procede de fabrication d'une couche d'isolant enterree dans un substrat semi-conducteur par implantation ionique et structure semi-conductrice comportant cette couche
US4956698A (en) 1987-07-29 1990-09-11 The United States Of America As Represented By The Department Of Commerce Group III-V compound semiconductor device having p-region formed by Be and Group V ions
US4846928A (en) 1987-08-04 1989-07-11 Texas Instruments, Incorporated Process and apparatus for detecting aberrations in production process operations
US4887005A (en) 1987-09-15 1989-12-12 Rough J Kirkwood H Multiple electrode plasma reactor power distribution system
US5015353A (en) 1987-09-30 1991-05-14 The United States Of America As Represented By The Secretary Of The Navy Method for producing substoichiometric silicon nitride of preselected proportions
US5138422A (en) 1987-10-27 1992-08-11 Nippondenso Co., Ltd. Semiconductor device which includes multiple isolated semiconductor segments on one chip
GB8725497D0 (en) 1987-10-30 1987-12-02 Atomic Energy Authority Uk Isolation of silicon
US5200805A (en) 1987-12-28 1993-04-06 Hughes Aircraft Company Silicon carbide:metal carbide alloy semiconductor and method of making the same
US4904610A (en) 1988-01-27 1990-02-27 General Instrument Corporation Wafer level process for fabricating passivated semiconductor devices
DE3803424C2 (de) 1988-02-05 1995-05-18 Gsf Forschungszentrum Umwelt Verfahren zur quantitativen, tiefendifferentiellen Analyse fester Proben
JP2666945B2 (ja) 1988-02-08 1997-10-22 株式会社東芝 半導体装置の製造方法
US4894709A (en) 1988-03-09 1990-01-16 Massachusetts Institute Of Technology Forced-convection, liquid-cooled, microchannel heat sinks
US4853250A (en) 1988-05-11 1989-08-01 Universite De Sherbrooke Process of depositing particulate material on a substrate
NL8802028A (nl) 1988-08-16 1990-03-16 Philips Nv Werkwijze voor het vervaardigen van een inrichting.
JP2670623B2 (ja) 1988-09-19 1997-10-29 アネルバ株式会社 マイクロ波プラズマ処理装置
US4952273A (en) 1988-09-21 1990-08-28 Microscience, Inc. Plasma generation in electron cyclotron resonance
US4996077A (en) 1988-10-07 1991-02-26 Texas Instruments Incorporated Distributed ECR remote plasma processing and apparatus
US4891329A (en) 1988-11-29 1990-01-02 University Of North Carolina Method of forming a nonsilicon semiconductor on insulator structure
JPH02302044A (ja) 1989-05-16 1990-12-14 Fujitsu Ltd 半導体装置の製造方法
US4929566A (en) 1989-07-06 1990-05-29 Harris Corporation Method of making dielectrically isolated integrated circuits using oxygen implantation and expitaxial growth
JPH0355822A (ja) 1989-07-25 1991-03-11 Shin Etsu Handotai Co Ltd 半導体素子形成用基板の製造方法
US4948458A (en) 1989-08-14 1990-08-14 Lam Research Corporation Method and apparatus for producing magnetically-coupled planar plasma
US5036023A (en) 1989-08-16 1991-07-30 At&T Bell Laboratories Rapid thermal processing method of making a semiconductor device
US5013681A (en) 1989-09-29 1991-05-07 The United States Of America As Represented By The Secretary Of The Navy Method of producing a thin silicon-on-insulator layer
US5310446A (en) 1990-01-10 1994-05-10 Ricoh Company, Ltd. Method for producing semiconductor film
JPH0650738B2 (ja) 1990-01-11 1994-06-29 株式会社東芝 半導体装置及びその製造方法
US5034343A (en) 1990-03-08 1991-07-23 Harris Corporation Manufacturing ultra-thin wafer using a handle wafer
CN1018844B (zh) 1990-06-02 1992-10-28 中国科学院兰州化学物理研究所 防锈干膜润滑剂
JPH0719739B2 (ja) 1990-09-10 1995-03-06 信越半導体株式会社 接合ウェーハの製造方法
US5198371A (en) 1990-09-24 1993-03-30 Biota Corp. Method of making silicon material with enhanced surface mobility by hydrogen ion implantation
US5618739A (en) * 1990-11-15 1997-04-08 Seiko Instruments Inc. Method of making light valve device using semiconductive composite substrate
US5300788A (en) 1991-01-18 1994-04-05 Kopin Corporation Light emitting diode bars and arrays and method of making same
GB2251546B (en) 1991-01-11 1994-05-11 Philips Electronic Associated An electrical kettle
JP2526317B2 (ja) 1991-01-25 1996-08-21 日本電子ロック株式会社 磁石カ―ド錠
DE4106288C2 (de) 1991-02-28 2001-05-31 Bosch Gmbh Robert Sensor zur Messung von Drücken oder Beschleunigungen
JP2812405B2 (ja) 1991-03-15 1998-10-22 信越半導体株式会社 半導体基板の製造方法
US5110748A (en) 1991-03-28 1992-05-05 Honeywell Inc. Method for fabricating high mobility thin film transistors as integrated drivers for active matrix display
US5442205A (en) 1991-04-24 1995-08-15 At&T Corp. Semiconductor heterostructure devices with strained semiconductor layers
US5256581A (en) 1991-08-28 1993-10-26 Motorola, Inc. Silicon film with improved thickness control
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JP3250673B2 (ja) * 1992-01-31 2002-01-28 キヤノン株式会社 半導体素子基体とその作製方法
JP3416163B2 (ja) 1992-01-31 2003-06-16 キヤノン株式会社 半導体基板及びその作製方法
JPH05235312A (ja) * 1992-02-19 1993-09-10 Fujitsu Ltd 半導体基板及びその製造方法
US5234535A (en) * 1992-12-10 1993-08-10 International Business Machines Corporation Method of producing a thin silicon-on-insulator layer
US5400458A (en) 1993-03-31 1995-03-28 Minnesota Mining And Manufacturing Company Brush segment for industrial brushes
FR2714524B1 (fr) 1993-12-23 1996-01-26 Commissariat Energie Atomique Procede de realisation d'une structure en relief sur un support en materiau semiconducteur
FR2715502B1 (fr) 1994-01-26 1996-04-05 Commissariat Energie Atomique Structure présentant des cavités et procédé de réalisation d'une telle structure.
FR2715503B1 (fr) 1994-01-26 1996-04-05 Commissariat Energie Atomique Substrat pour composants intégrés comportant une couche mince et son procédé de réalisation.
FR2715501B1 (fr) * 1994-01-26 1996-04-05 Commissariat Energie Atomique Procédé de dépôt de lames semiconductrices sur un support.
JP3293736B2 (ja) * 1996-02-28 2002-06-17 キヤノン株式会社 半導体基板の作製方法および貼り合わせ基体
JPH0851103A (ja) * 1994-08-08 1996-02-20 Fuji Electric Co Ltd 薄膜の生成方法
US5524339A (en) * 1994-09-19 1996-06-11 Martin Marietta Corporation Method for protecting gallium arsenide mmic air bridge structures
FR2725074B1 (fr) * 1994-09-22 1996-12-20 Commissariat Energie Atomique Procede de fabrication d'une structure comportant une couche mince semi-conductrice sur un substrat
US5567654A (en) * 1994-09-28 1996-10-22 International Business Machines Corporation Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging
EP0749500B1 (en) * 1994-10-18 1998-05-27 Koninklijke Philips Electronics N.V. Method of manufacturing a thin silicon-oxide layer
EP0717437B1 (en) * 1994-12-12 2002-04-24 Advanced Micro Devices, Inc. Method of forming buried oxide layers
FR2738671B1 (fr) * 1995-09-13 1997-10-10 Commissariat Energie Atomique Procede de fabrication de films minces a materiau semiconducteur
FR2744285B1 (fr) * 1996-01-25 1998-03-06 Commissariat Energie Atomique Procede de transfert d'une couche mince d'un substrat initial sur un substrat final
FR2748851B1 (fr) 1996-05-15 1998-08-07 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
US5863832A (en) * 1996-06-28 1999-01-26 Intel Corporation Capping layer in interconnect system and method for bonding the capping layer onto the interconnect system
US5897331A (en) * 1996-11-08 1999-04-27 Midwest Research Institute High efficiency low cost thin film silicon solar cell design and method for making
US6013563A (en) * 1997-05-12 2000-01-11 Silicon Genesis Corporation Controlled cleaning process
FR2773261B1 (fr) 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
FR2823596B1 (fr) 2001-04-13 2004-08-20 Commissariat Energie Atomique Substrat ou structure demontable et procede de realisation
FR2823599B1 (fr) 2001-04-13 2004-12-17 Commissariat Energie Atomique Substrat demomtable a tenue mecanique controlee et procede de realisation
FR2830983B1 (fr) 2001-10-11 2004-05-14 Commissariat Energie Atomique Procede de fabrication de couches minces contenant des microcomposants
KR100511656B1 (ko) * 2002-08-10 2005-09-07 주식회사 실트론 나노 에스오아이 웨이퍼의 제조방법 및 그에 따라 제조된나노 에스오아이 웨이퍼
FR2847075B1 (fr) 2002-11-07 2005-02-18 Commissariat Energie Atomique Procede de formation d'une zone fragile dans un substrat par co-implantation
FR2848336B1 (fr) 2002-12-09 2005-10-28 Commissariat Energie Atomique Procede de realisation d'une structure contrainte destinee a etre dissociee
FR2850487B1 (fr) 2002-12-24 2005-12-09 Commissariat Energie Atomique Procede de realisation de substrats mixtes et structure ainsi obtenue
FR2856844B1 (fr) 2003-06-24 2006-02-17 Commissariat Energie Atomique Circuit integre sur puce de hautes performances
FR2857953B1 (fr) 2003-07-21 2006-01-13 Commissariat Energie Atomique Structure empilee, et procede pour la fabriquer
FR2861497B1 (fr) 2003-10-28 2006-02-10 Soitec Silicon On Insulator Procede de transfert catastrophique d'une couche fine apres co-implantation
US7772087B2 (en) 2003-12-19 2010-08-10 Commissariat A L'energie Atomique Method of catastrophic transfer of a thin film after co-implantation
FR2889887B1 (fr) 2005-08-16 2007-11-09 Commissariat Energie Atomique Procede de report d'une couche mince sur un support
FR2891281B1 (fr) 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
FR2899378B1 (fr) 2006-03-29 2008-06-27 Commissariat Energie Atomique Procede de detachement d'un film mince par fusion de precipites
FR2910179B1 (fr) 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
FR2922359B1 (fr) 2007-10-12 2009-12-18 Commissariat Energie Atomique Procede de fabrication d'une structure micro-electronique impliquant un collage moleculaire
FR2925221B1 (fr) 2007-12-17 2010-02-19 Commissariat Energie Atomique Procede de transfert d'une couche mince
FR2947098A1 (fr) 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince

Also Published As

Publication number Publication date
US8101503B2 (en) 2012-01-24
US20040166651A1 (en) 2004-08-26
US7067396B2 (en) 2006-06-27
US20010007789A1 (en) 2001-07-12
EP1768176A3 (fr) 2007-04-04
US7498234B2 (en) 2009-03-03
DE69738608T2 (de) 2009-04-30
MY125679A (en) 2006-08-30
FR2748851A1 (fr) 1997-11-21
US6225192B1 (en) 2001-05-01
FR2748851B1 (fr) 1998-08-07
EP0807970A1 (fr) 1997-11-19
US20120133028A1 (en) 2012-05-31
US6020252A (en) 2000-02-01
KR970077700A (ko) 1997-12-12
US20060115961A1 (en) 2006-06-01
TW366527B (en) 1999-08-11
JP2004048038A (ja) 2004-02-12
JP4220332B2 (ja) 2009-02-04
EP1768176A2 (fr) 2007-03-28
JPH1050628A (ja) 1998-02-20
SG52966A1 (en) 1998-09-28
EP0807970B1 (fr) 2008-04-02
DE69738608D1 (de) 2008-05-15
US6809009B2 (en) 2004-10-26
US20090130392A1 (en) 2009-05-21
KR100704107B1 (ko) 2007-07-06

Similar Documents

Publication Publication Date Title
JP3517080B2 (ja) 半導体材料薄層の製造方法
KR100718783B1 (ko) 멤브레인 제조 방법 및 이를 이용한 멤브레인 구조물
JP4310503B2 (ja) イオン打込ステップを備えるとともに、イオンから保護された領域を具備した、特に半導体膜からなる、薄膜を得るための方法
KR100745700B1 (ko) 가압을 이용한 박막 제조방법
US6991995B2 (en) Method of producing a semiconductor structure having at least one support substrate and an ultrathin layer
JP4222644B2 (ja) 特に電子構成品を含む半導体材料薄膜の製法
JP5111713B2 (ja) 材料ブロックを切り取るための方法ならびに薄膜の形成方法
JPH09508493A (ja) ウェファ基板のキャビティを含む構造とその製造方法
JP4425631B2 (ja) 超小型構成部品を含む薄膜層を製造するための方法
JP2003506892A (ja) 過度の脆弱化ステップを有した薄層の移送方法
US20080064182A1 (en) Process for high temperature layer transfer
JP5588448B2 (ja) 埋め込み電気絶縁連続層を備えたハイブリッド基板を製造する方法
KR20010113684A (ko) 조절된 내부 응력을 가지는 다층 구조체 및, 그러한구조체를 제조하는 방법
JP2001503568A (ja) 基盤上に形成された薄層およびその製造方法
JPH05211128A (ja) 薄い半導体材料フィルムの製造方法
US7776714B2 (en) Method for production of a very thin layer with thinning by means of induced self-support
US9275892B2 (en) Method of high temperature layer transfer

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20030527

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20040106

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20040122

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090130

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100130

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110130

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110130

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120130

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130130

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140130

Year of fee payment: 10

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term