FR2935535B1 - Procede de detourage mixte. - Google Patents
Procede de detourage mixte.Info
- Publication number
- FR2935535B1 FR2935535B1 FR0855872A FR0855872A FR2935535B1 FR 2935535 B1 FR2935535 B1 FR 2935535B1 FR 0855872 A FR0855872 A FR 0855872A FR 0855872 A FR0855872 A FR 0855872A FR 2935535 B1 FR2935535 B1 FR 2935535B1
- Authority
- FR
- France
- Prior art keywords
- plate
- detouring
- joint
- trimming step
- trimming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title abstract 3
- 238000009966 trimming Methods 0.000 abstract 4
- 238000003754 machining Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
- Punching Or Piercing (AREA)
Abstract
L'invention concerne un procédé de détourage d'une structure (500) comprenant une première plaque (200) collée sur une deuxième plaque (300), la première plaque (200) présentant un bord chanfreiné. Le procédé comprend une première étape de détourage (S4) du bord de la première plaque (200) réalisée par usinage mécanique sur une profondeur (Pd1) déterminée dans la première plaque. Cette première étape de détourage est suivie d'une deuxième étape de détourage non mécanique (55) sur au moins l'épaisseur restante de la première plaque.
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0855872A FR2935535B1 (fr) | 2008-09-02 | 2008-09-02 | Procede de detourage mixte. |
KR1020107023257A KR101185426B1 (ko) | 2008-09-02 | 2009-07-31 | 복합 트리밍 방법 |
PCT/EP2009/059960 WO2010026006A1 (fr) | 2008-09-02 | 2009-07-31 | Procédé de finition mixte |
JP2011510009A JP2011523779A (ja) | 2008-09-02 | 2009-07-31 | 混合トリミング方法 |
CN2009801154790A CN102017090A (zh) | 2008-09-02 | 2009-07-31 | 混合冲切方法 |
US12/933,966 US20110117691A1 (en) | 2008-09-02 | 2009-07-31 | Mixed trimming method |
EP09811093A EP2321842A1 (fr) | 2008-09-02 | 2009-07-31 | Procédé de finition mixte |
TW098128543A TW201027608A (en) | 2008-09-02 | 2009-08-25 | A mixed trimming method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0855872A FR2935535B1 (fr) | 2008-09-02 | 2008-09-02 | Procede de detourage mixte. |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2935535A1 FR2935535A1 (fr) | 2010-03-05 |
FR2935535B1 true FR2935535B1 (fr) | 2010-12-10 |
Family
ID=40521695
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0855872A Expired - Fee Related FR2935535B1 (fr) | 2008-09-02 | 2008-09-02 | Procede de detourage mixte. |
Country Status (8)
Country | Link |
---|---|
US (1) | US20110117691A1 (fr) |
EP (1) | EP2321842A1 (fr) |
JP (1) | JP2011523779A (fr) |
KR (1) | KR101185426B1 (fr) |
CN (1) | CN102017090A (fr) |
FR (1) | FR2935535B1 (fr) |
TW (1) | TW201027608A (fr) |
WO (1) | WO2010026006A1 (fr) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2899594A1 (fr) | 2006-04-10 | 2007-10-12 | Commissariat Energie Atomique | Procede d'assemblage de substrats avec traitements thermiques a basses temperatures |
FR2935536B1 (fr) | 2008-09-02 | 2010-09-24 | Soitec Silicon On Insulator | Procede de detourage progressif |
FR2950734B1 (fr) * | 2009-09-28 | 2011-12-09 | Soitec Silicon On Insulator | Procede de collage et de transfert d'une couche |
FR2954585B1 (fr) * | 2009-12-23 | 2012-03-02 | Soitec Silicon Insulator Technologies | Procede de realisation d'une heterostructure avec minimisation de contrainte |
FR2957189B1 (fr) | 2010-03-02 | 2012-04-27 | Soitec Silicon On Insulator | Procede de realisation d'une structure multicouche avec detourage post meulage. |
FR2957716B1 (fr) | 2010-03-18 | 2012-10-05 | Soitec Silicon On Insulator | Procede de finition d'un substrat de type semi-conducteur sur isolant |
FR2961630B1 (fr) | 2010-06-22 | 2013-03-29 | Soitec Silicon On Insulator Technologies | Appareil de fabrication de dispositifs semi-conducteurs |
US8338266B2 (en) | 2010-08-11 | 2012-12-25 | Soitec | Method for molecular adhesion bonding at low pressure |
FR2964193A1 (fr) | 2010-08-24 | 2012-03-02 | Soitec Silicon On Insulator | Procede de mesure d'une energie d'adhesion, et substrats associes |
FR2967295B1 (fr) * | 2010-11-05 | 2013-01-11 | Soitec Silicon On Insulator | Procédé de traitement d'une structure multicouche |
US8765578B2 (en) * | 2012-06-06 | 2014-07-01 | International Business Machines Corporation | Edge protection of bonded wafers during wafer thinning |
US9064770B2 (en) * | 2012-07-17 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for minimizing edge peeling in the manufacturing of BSI chips |
JP2014107448A (ja) * | 2012-11-28 | 2014-06-09 | Nikon Corp | 積層半導体装置の製造方法および積層半導体製造装置 |
US9721832B2 (en) * | 2013-03-15 | 2017-08-01 | Kulite Semiconductor Products, Inc. | Methods of fabricating silicon-on-insulator (SOI) semiconductor devices using blanket fusion bonding |
FR3007576B1 (fr) * | 2013-06-19 | 2015-07-10 | Soitec Silicon On Insulator | Procede de transfert d'une couche de circuits. |
US10510560B2 (en) * | 2015-09-04 | 2019-12-17 | Nanyang Technological University | Method of encapsulating a substrate |
CN105271108B (zh) * | 2015-09-10 | 2017-08-04 | 武汉新芯集成电路制造有限公司 | 一种晶圆的键合方法 |
US10580823B2 (en) * | 2017-05-03 | 2020-03-03 | United Microelectronics Corp. | Wafer level packaging method |
US10818488B2 (en) * | 2017-11-13 | 2020-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer structure and trimming method thereof |
CN110323178A (zh) * | 2019-07-04 | 2019-10-11 | 长春长光圆辰微电子技术有限公司 | 一种soi晶圆边缘零空洞的工艺制程方法 |
US11482506B2 (en) * | 2020-03-31 | 2022-10-25 | Taiwan Semiconductor Manufacturing Company Limited | Edge-trimming methods for wafer bonding and dicing |
CN112289694A (zh) * | 2020-10-30 | 2021-01-29 | 长江存储科技有限责任公司 | 晶圆键合方法 |
FR3120985B1 (fr) * | 2021-03-19 | 2023-03-31 | Soitec Silicon On Insulator | Procédé de fabrication d’une hétérostructure |
CN115579282B (zh) * | 2022-11-04 | 2024-03-22 | 湖北三维半导体集成创新中心有限责任公司 | 晶圆的处理方法 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04263425A (ja) * | 1991-02-18 | 1992-09-18 | Toshiba Corp | 半導体基板の研削装置及び研削方法 |
US5266511A (en) * | 1991-10-02 | 1993-11-30 | Fujitsu Limited | Process for manufacturing three dimensional IC's |
JP3352129B2 (ja) * | 1992-12-04 | 2002-12-03 | 株式会社東芝 | 半導体基板の製造方法 |
JPH0917984A (ja) * | 1995-06-29 | 1997-01-17 | Sumitomo Sitix Corp | 貼り合わせsoi基板の製造方法 |
FR2748851B1 (fr) * | 1996-05-15 | 1998-08-07 | Commissariat Energie Atomique | Procede de realisation d'une couche mince de materiau semiconducteur |
JP3352896B2 (ja) * | 1997-01-17 | 2002-12-03 | 信越半導体株式会社 | 貼り合わせ基板の作製方法 |
JPH10223497A (ja) * | 1997-01-31 | 1998-08-21 | Shin Etsu Handotai Co Ltd | 貼り合わせ基板の作製方法 |
EP0935280B1 (fr) * | 1998-02-04 | 2004-06-09 | Canon Kabushiki Kaisha | Substrat SOI |
JP3635200B2 (ja) * | 1998-06-04 | 2005-04-06 | 信越半導体株式会社 | Soiウェーハの製造方法 |
US6984571B1 (en) * | 1999-10-01 | 2006-01-10 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
US6863774B2 (en) * | 2001-03-08 | 2005-03-08 | Raytech Innovative Solutions, Inc. | Polishing pad for use in chemical-mechanical planarization of semiconductor wafers and method of making same |
US6717212B2 (en) * | 2001-06-12 | 2004-04-06 | Advanced Micro Devices, Inc. | Leaky, thermally conductive insulator material (LTCIM) in semiconductor-on-insulator (SOI) structure |
US6790748B2 (en) * | 2002-12-19 | 2004-09-14 | Intel Corporation | Thinning techniques for wafer-to-wafer vertical stacks |
FR2860842B1 (fr) * | 2003-10-14 | 2007-11-02 | Tracit Technologies | Procede de preparation et d'assemblage de substrats |
CN2673568Y (zh) * | 2004-01-09 | 2005-01-26 | 洛阳轴承集团有限公司 | 杯形泵水砂轮 |
JP4175650B2 (ja) * | 2004-08-26 | 2008-11-05 | シャープ株式会社 | 半導体装置の製造方法 |
JP4918229B2 (ja) * | 2005-05-31 | 2012-04-18 | 信越半導体株式会社 | 貼り合わせウエーハの製造方法 |
JP5122731B2 (ja) * | 2005-06-01 | 2013-01-16 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
JP2008073832A (ja) * | 2006-09-19 | 2008-04-03 | Add:Kk | 薄型ウェハ製作用研削砥石及び研削方法 |
-
2008
- 2008-09-02 FR FR0855872A patent/FR2935535B1/fr not_active Expired - Fee Related
-
2009
- 2009-07-31 US US12/933,966 patent/US20110117691A1/en not_active Abandoned
- 2009-07-31 JP JP2011510009A patent/JP2011523779A/ja not_active Withdrawn
- 2009-07-31 WO PCT/EP2009/059960 patent/WO2010026006A1/fr active Application Filing
- 2009-07-31 KR KR1020107023257A patent/KR101185426B1/ko not_active IP Right Cessation
- 2009-07-31 CN CN2009801154790A patent/CN102017090A/zh active Pending
- 2009-07-31 EP EP09811093A patent/EP2321842A1/fr not_active Withdrawn
- 2009-08-25 TW TW098128543A patent/TW201027608A/zh unknown
Also Published As
Publication number | Publication date |
---|---|
FR2935535A1 (fr) | 2010-03-05 |
JP2011523779A (ja) | 2011-08-18 |
KR20110007138A (ko) | 2011-01-21 |
WO2010026006A1 (fr) | 2010-03-11 |
CN102017090A (zh) | 2011-04-13 |
KR101185426B1 (ko) | 2012-10-02 |
TW201027608A (en) | 2010-07-16 |
US20110117691A1 (en) | 2011-05-19 |
EP2321842A1 (fr) | 2011-05-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
CD | Change of name or company name |
Owner name: SOITEC, FR Effective date: 20120907 |
|
ST | Notification of lapse |
Effective date: 20140530 |