FR2942073B1 - Procede de realisation d'une couche de cavites - Google Patents

Procede de realisation d'une couche de cavites

Info

Publication number
FR2942073B1
FR2942073B1 FR0950805A FR0950805A FR2942073B1 FR 2942073 B1 FR2942073 B1 FR 2942073B1 FR 0950805 A FR0950805 A FR 0950805A FR 0950805 A FR0950805 A FR 0950805A FR 2942073 B1 FR2942073 B1 FR 2942073B1
Authority
FR
France
Prior art keywords
cavities
making
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR0950805A
Other languages
English (en)
Other versions
FR2942073A1 (fr
Inventor
Didier Landru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR0950805A priority Critical patent/FR2942073B1/fr
Application filed by Soitec SA filed Critical Soitec SA
Priority to KR20117018583A priority patent/KR101509008B1/ko
Priority to SG2011045937A priority patent/SG172335A1/en
Priority to US13/143,038 priority patent/US8614501B2/en
Priority to PCT/EP2010/051197 priority patent/WO2010091972A1/fr
Priority to EP10702664A priority patent/EP2396816A1/fr
Priority to CN201080006485.5A priority patent/CN102308382B/zh
Priority to JP2011548660A priority patent/JP5480298B2/ja
Publication of FR2942073A1 publication Critical patent/FR2942073A1/fr
Application granted granted Critical
Publication of FR2942073B1 publication Critical patent/FR2942073B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Formation Of Insulating Films (AREA)
  • Materials For Medical Uses (AREA)
FR0950805A 2009-02-10 2009-02-10 Procede de realisation d'une couche de cavites Active FR2942073B1 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FR0950805A FR2942073B1 (fr) 2009-02-10 2009-02-10 Procede de realisation d'une couche de cavites
SG2011045937A SG172335A1 (en) 2009-02-10 2010-02-01 A method of producing a layer of cavities
US13/143,038 US8614501B2 (en) 2009-02-10 2010-02-01 Method of producing a layer of cavities
PCT/EP2010/051197 WO2010091972A1 (fr) 2009-02-10 2010-02-01 Procédé de production d'une couche de cavités
KR20117018583A KR101509008B1 (ko) 2009-02-10 2010-02-01 캐비티들의 층을 생성하는 방법
EP10702664A EP2396816A1 (fr) 2009-02-10 2010-02-01 Procédé de production d'une couche de cavités
CN201080006485.5A CN102308382B (zh) 2009-02-10 2010-02-01 制造孔层的方法
JP2011548660A JP5480298B2 (ja) 2009-02-10 2010-02-01 キャビティ層の形成方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0950805A FR2942073B1 (fr) 2009-02-10 2009-02-10 Procede de realisation d'une couche de cavites

Publications (2)

Publication Number Publication Date
FR2942073A1 FR2942073A1 (fr) 2010-08-13
FR2942073B1 true FR2942073B1 (fr) 2011-04-29

Family

ID=41077683

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0950805A Active FR2942073B1 (fr) 2009-02-10 2009-02-10 Procede de realisation d'une couche de cavites

Country Status (8)

Country Link
US (1) US8614501B2 (fr)
EP (1) EP2396816A1 (fr)
JP (1) JP5480298B2 (fr)
KR (1) KR101509008B1 (fr)
CN (1) CN102308382B (fr)
FR (1) FR2942073B1 (fr)
SG (1) SG172335A1 (fr)
WO (1) WO2010091972A1 (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2942073B1 (fr) * 2009-02-10 2011-04-29 Soitec Silicon On Insulator Procede de realisation d'une couche de cavites
KR101900525B1 (ko) * 2011-03-18 2018-09-19 가부시키가이샤 한도오따이 에네루기 켄큐쇼 산화물 반도체막, 반도체 장치, 및 반도체 장치의 제작 방법
FR2977069B1 (fr) 2011-06-23 2014-02-07 Soitec Silicon On Insulator Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire
FR2995445B1 (fr) 2012-09-07 2016-01-08 Soitec Silicon On Insulator Procede de fabrication d'une structure en vue d'une separation ulterieure
FR2995444B1 (fr) * 2012-09-10 2016-11-25 Soitec Silicon On Insulator Procede de detachement d'une couche
JP6131701B2 (ja) * 2013-05-08 2017-05-24 株式会社豊田自動織機 半導体基板の製造方法
KR101951902B1 (ko) * 2016-04-12 2019-02-26 주식회사 루미스탈 복수의 공극을 포함한 질화물 반도체 기판 및 그 제조 방법
WO2017179868A1 (fr) * 2016-04-12 2017-10-19 주식회사 루미스탈 Procédé de fabrication de substrat semi-conducteur au nitrure incluant une couche semi-conductrice au nitrure semi-isolante, et substrat semi-conducteur au nitrure ainsi fabriqué
DE102019100312A1 (de) * 2019-01-08 2020-07-09 Parcan NanoTech Co. Ltd. Substrat für eine kontrollierte lonenimplantation und Verfahren zur Herstellung eines Substrats für eine kontrollierte lonenimplantation
CN110079859A (zh) * 2019-04-28 2019-08-02 厦门市三安集成电路有限公司 一种SiC基GaN外延片的剥离方法
FR3105574B1 (fr) * 2019-12-19 2023-01-13 Commissariat Energie Atomique Empilement multicouches de type semi-conducteur-sur-isolant, procédé d’élaboration associé, et module radiofréquence le comprenant

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS592185B2 (ja) * 1980-02-04 1984-01-17 日本電信電話株式会社 半導体基体内への絶縁領域の形成法
US5143858A (en) * 1990-04-02 1992-09-01 Motorola, Inc. Method of fabricating buried insulating layers
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
EP0703608B1 (fr) * 1994-09-23 1998-02-25 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe Procédé pour former des régions d'oxyde enterrées dans des corps en silicium
JP2666757B2 (ja) * 1995-01-09 1997-10-22 日本電気株式会社 Ｓｏｉ基板の製造方法
FR2748851B1 (fr) 1996-05-15 1998-08-07 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
JP3515351B2 (ja) * 1998-01-08 2004-04-05 株式会社東芝 半導体装置の製造方法
FR2784796B1 (fr) * 1998-10-15 2001-11-23 Commissariat Energie Atomique Procede de realisation d'une couche de materiau enterree dans un autre materiau
JP2000124092A (ja) * 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
JP3975634B2 (ja) * 2000-01-25 2007-09-12 信越半導体株式会社 半導体ウェハの製作法
JP3571989B2 (ja) * 2000-03-13 2004-09-29 株式会社東芝 半導体装置及びその製造方法
JP2002359247A (ja) * 2000-07-10 2002-12-13 Canon Inc 半導体部材、半導体装置およびそれらの製造方法
US6495429B1 (en) * 2002-01-23 2002-12-17 International Business Machines Corporation Controlling internal thermal oxidation and eliminating deep divots in SIMOX by chlorine-based annealing
JP4277481B2 (ja) * 2002-05-08 2009-06-10 日本電気株式会社 半導体基板の製造方法、半導体装置の製造方法
JP4000087B2 (ja) * 2003-05-07 2007-10-31 株式会社東芝 半導体装置およびその製造方法
US7256104B2 (en) * 2003-05-21 2007-08-14 Canon Kabushiki Kaisha Substrate manufacturing method and substrate processing apparatus
FR2860249B1 (fr) 2003-09-30 2005-12-09 Michel Bruel Procede de fabrication d'une structure en forme de plaque, en particulier en silicium, application de procede, et structure en forme de plaque, en particulier en silicium
JP2005229062A (ja) * 2004-02-16 2005-08-25 Canon Inc Ｓｏｉ基板及びその製造方法
US7422956B2 (en) * 2004-12-08 2008-09-09 Advanced Micro Devices, Inc. Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers
JP2007220782A (ja) * 2006-02-15 2007-08-30 Shin Etsu Chem Co Ltd Ｓｏｉ基板およびｓｏｉ基板の製造方法
FR2899378B1 (fr) * 2006-03-29 2008-06-27 Commissariat Energie Atomique Procede de detachement d'un film mince par fusion de precipites
JP2008004821A (ja) * 2006-06-23 2008-01-10 Sumco Corp 貼り合わせウェーハの製造方法
FR2942073B1 (fr) * 2009-02-10 2011-04-29 Soitec Silicon On Insulator Procede de realisation d'une couche de cavites

Also Published As

Publication number Publication date
WO2010091972A1 (fr) 2010-08-19
CN102308382B (zh) 2014-12-10
US8614501B2 (en) 2013-12-24
CN102308382A (zh) 2012-01-04
SG172335A1 (en) 2011-07-28
US20110278597A1 (en) 2011-11-17
KR20110102949A (ko) 2011-09-19
KR101509008B1 (ko) 2015-04-07
FR2942073A1 (fr) 2010-08-13
JP2012517694A (ja) 2012-08-02
EP2396816A1 (fr) 2011-12-21
JP5480298B2 (ja) 2014-04-23

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