JP2001503568A - 基盤上に形成された薄層およびその製造方法 - Google Patents
基盤上に形成された薄層およびその製造方法Info
- Publication number
- JP2001503568A JP2001503568A JP52109898A JP52109898A JP2001503568A JP 2001503568 A JP2001503568 A JP 2001503568A JP 52109898 A JP52109898 A JP 52109898A JP 52109898 A JP52109898 A JP 52109898A JP 2001503568 A JP2001503568 A JP 2001503568A
- Authority
- JP
- Japan
- Prior art keywords
- base material
- layer
- support member
- heat treatment
- ion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title abstract description 5
- 239000000758 substrate Substances 0.000 title description 16
- 239000000463 material Substances 0.000 claims abstract description 108
- 238000000034 method Methods 0.000 claims abstract description 77
- 238000010438 heat treatment Methods 0.000 claims abstract description 32
- 150000002500 ions Chemical class 0.000 claims description 26
- 239000010703 silicon Substances 0.000 claims description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 22
- 238000005468 ion implantation Methods 0.000 claims description 17
- 230000008569 process Effects 0.000 claims description 15
- 238000000137 annealing Methods 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 230000003014 reinforcing effect Effects 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 9
- 239000011159 matrix material Substances 0.000 claims description 8
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 7
- 239000007789 gas Substances 0.000 claims description 7
- 238000000227 grinding Methods 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 230000010070 molecular adhesion Effects 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 5
- 238000000926 separation method Methods 0.000 claims description 4
- 239000011800 void material Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 21
- 239000004065 semiconductor Substances 0.000 description 15
- 239000013078 crystal Substances 0.000 description 8
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 230000035882 stress Effects 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 230000008707 rearrangement Effects 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005489 elastic deformation Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 229920006332 epoxy adhesive Polymers 0.000 description 1
- 238000004299 exfoliation Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- -1 hydrogen ions Chemical class 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052756 noble gas Inorganic materials 0.000 description 1
- 150000002835 noble gases Chemical class 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/977—Thinning or removal of substrate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.第2の材料からなる支持部材上に第1の材料からなる薄層を形成する方法で あって、 −前記第1の材料からなる母材(1)の表面(2)にイオン(3)によるイオ ン照射を行い、母材のイオン入射深さと同程度の位置にミクロ空隙層を形成し、 当該層によって母材をイオン照射を受けた表面(2)とミクロ空隙層(4)との 間の薄層領域(5)を含む2つの領域に分割する工程と、 −母材(1)のイオン照射を受けた面(2)を支持部材(6)の対応する表面 に密着させる密着工程と、 −ミクロ空隙層(4)によって母材(1)が2つの領域に分割される為に充分 な温度による熱処理工程を有する方法であって、 −さらに母材(1)および支持部材(6)のうちの少なくとも一方を、薄肉化 された厚さが、密着された両部材が上記の熱処理工程中に両部材の熱膨張係数の 相違で発生する応力に抗して密着を維持することができる厚さであることを特徴 とする方法。 2.前記薄肉化工程が母材(1)をイオン注入の前に薄肉化するものであること を特徴とする請求項1の方法。 3.前記薄肉化工程が母材(1)をイオン注入の後で支持部材への密着の前に薄 肉化することを特徴とする請求項1に記載の方法。 4.前記薄肉化工程がイオン注入の後であって最終熱処理の前に母材(1)を薄 肉化することを特徴とする請求項1に記載の方法。 5.第2の材料からなる支持部材上に第1の材料からなる薄層を形成する方法で あって、 −平行な2つの表面を有する前記第1の材料からなる母材を第一の支持部材の 対応する表面に密着させる工程と、 −前記母材の他方の面から母材を、後の熱処理工程中、母材と他の部材の熱膨 張係数の相違に起因して発生する応力に抗して密着がはがれない厚さにまで薄肉 化する工程と、 −薄肉化された母材の自由表面をイオンで照射し母材のイオンの入射深さに相 当する位置にミクロ空隙の層を形成し、イオン照射を行った表面と当該層の間の 領域を含む2つの領域に母材を区分するイオン注入工程と、 −薄肉化された母材のイオン照射を受けた表面を第2の支持部材の対応する表 面に密着させる工程と、 −ミクロ空隙層を境に母材を分離させる最終熱処理工程とを含む方法。 6.イオン照射を希ガスおよび水素ガスから選択した元素のイオンによって行う ことを特徴とする請求項1ないし請求項5のいずれかに記載した方法。 7.薄肉化工程を、機械研削、機械・化学研磨、化学処理、またはこれらの組み 合わせによって行うことを特徴とする請求項1ないし請求項6のいずれかに記載 の方法。 8.密着工程を、母材の分離が発生する温度以下の温度で行う焼鈍処理によって 補強した分子接着によって行うことを特徴とする請求項1ないし請求項7のいず れかに記載の方法。 9.前記分子接着を補強する焼鈍処理を薄肉化処理の進捗に従って複数回行うこ とを特徴とする請求項8に記載の方法。 10.第2の材料からなる支持部材(6)と第1の材料からなる薄層(1)とを 有し、前記請求項に記載した方法のいずれかによって得られた構造物。 11.第1の材料がシリコンで第2の材料がシリカである請求項10に記載の構 造物。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR96/13449 | 1996-11-05 | ||
FR9613449A FR2755537B1 (fr) | 1996-11-05 | 1996-11-05 | Procede de fabrication d'un film mince sur un support et structure ainsi obtenue |
PCT/FR1997/001969 WO1998020543A2 (fr) | 1996-11-05 | 1997-11-04 | Procede de fabrication d'un film mince sur un support et structure ainsi obtenue |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2001503568A true JP2001503568A (ja) | 2001-03-13 |
Family
ID=9497325
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52109898A Pending JP2001503568A (ja) | 1996-11-05 | 1997-11-04 | 基盤上に形成された薄層およびその製造方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US6335258B1 (ja) |
EP (1) | EP0950257B1 (ja) |
JP (1) | JP2001503568A (ja) |
KR (2) | KR100654164B1 (ja) |
DE (1) | DE69739584D1 (ja) |
FR (1) | FR2755537B1 (ja) |
WO (1) | WO1998020543A2 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006527480A (ja) * | 2003-06-06 | 2006-11-30 | コミツサリア タ レネルジー アトミーク | 自立を誘発することによって薄肉化された極薄層の製造方法 |
JP2009004741A (ja) * | 2007-05-18 | 2009-01-08 | Semiconductor Energy Lab Co Ltd | Soi基板の作製方法、及び半導体装置の作製方法 |
WO2010050556A1 (ja) * | 2008-10-31 | 2010-05-06 | 信越化学工業株式会社 | シリコン薄膜転写絶縁性ウェーハの製造方法 |
WO2014118851A1 (ja) * | 2013-02-01 | 2014-08-07 | 信越半導体株式会社 | Soiウェーハの製造方法及びsoiウェーハ |
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FR2795866B1 (fr) * | 1999-06-30 | 2001-08-17 | Commissariat Energie Atomique | Procede de realisation d'une membrane mince et structure a membrane ainsi obtenue |
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JP2812405B2 (ja) * | 1991-03-15 | 1998-10-22 | 信越半導体株式会社 | 半導体基板の製造方法 |
US5256581A (en) * | 1991-08-28 | 1993-10-26 | Motorola, Inc. | Silicon film with improved thickness control |
FR2681472B1 (fr) * | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
JP2609198B2 (ja) * | 1992-08-07 | 1997-05-14 | 信越半導体株式会社 | 半導体基板の製造方法 |
FR2714524B1 (fr) * | 1993-12-23 | 1996-01-26 | Commissariat Energie Atomique | Procede de realisation d'une structure en relief sur un support en materiau semiconducteur |
FR2725074B1 (fr) * | 1994-09-22 | 1996-12-20 | Commissariat Energie Atomique | Procede de fabrication d'une structure comportant une couche mince semi-conductrice sur un substrat |
CN1132223C (zh) * | 1995-10-06 | 2003-12-24 | 佳能株式会社 | 半导体衬底及其制造方法 |
FR2744285B1 (fr) * | 1996-01-25 | 1998-03-06 | Commissariat Energie Atomique | Procede de transfert d'une couche mince d'un substrat initial sur un substrat final |
FR2748851B1 (fr) * | 1996-05-15 | 1998-08-07 | Commissariat Energie Atomique | Procede de realisation d'une couche mince de materiau semiconducteur |
US6150239A (en) * | 1997-05-31 | 2000-11-21 | Max Planck Society | Method for the transfer of thin layers monocrystalline material onto a desirable substrate |
US5920764A (en) * | 1997-09-30 | 1999-07-06 | International Business Machines Corporation | Process for restoring rejected wafers in line for reuse as new |
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1996
- 1996-11-05 FR FR9613449A patent/FR2755537B1/fr not_active Expired - Fee Related
-
1997
- 1997-11-04 JP JP52109898A patent/JP2001503568A/ja active Pending
- 1997-11-04 US US09/284,801 patent/US6335258B1/en not_active Expired - Lifetime
- 1997-11-04 KR KR1019997003740A patent/KR100654164B1/ko not_active IP Right Cessation
- 1997-11-04 KR KR1020067006274A patent/KR20060040750A/ko not_active Application Discontinuation
- 1997-11-04 EP EP97913241A patent/EP0950257B1/fr not_active Expired - Lifetime
- 1997-11-04 DE DE69739584T patent/DE69739584D1/de not_active Expired - Lifetime
- 1997-11-04 WO PCT/FR1997/001969 patent/WO1998020543A2/fr not_active Application Discontinuation
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2006527480A (ja) * | 2003-06-06 | 2006-11-30 | コミツサリア タ レネルジー アトミーク | 自立を誘発することによって薄肉化された極薄層の製造方法 |
JP2009004741A (ja) * | 2007-05-18 | 2009-01-08 | Semiconductor Energy Lab Co Ltd | Soi基板の作製方法、及び半導体装置の作製方法 |
US9059247B2 (en) | 2007-05-18 | 2015-06-16 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate and method for manufacturing semiconductor device |
WO2010050556A1 (ja) * | 2008-10-31 | 2010-05-06 | 信越化学工業株式会社 | シリコン薄膜転写絶縁性ウェーハの製造方法 |
JP2010135764A (ja) * | 2008-10-31 | 2010-06-17 | Shin-Etsu Chemical Co Ltd | シリコン薄膜転写絶縁性ウェーハの製造方法 |
US8138064B2 (en) | 2008-10-31 | 2012-03-20 | Shin-Etsu Chemical Co., Ltd. | Method for producing silicon film-transferred insulator wafer |
WO2014118851A1 (ja) * | 2013-02-01 | 2014-08-07 | 信越半導体株式会社 | Soiウェーハの製造方法及びsoiウェーハ |
JP2014150193A (ja) * | 2013-02-01 | 2014-08-21 | Shin Etsu Handotai Co Ltd | Soiウェーハの製造方法及びsoiウェーハ |
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---|---|
US6335258B1 (en) | 2002-01-01 |
WO1998020543A3 (fr) | 1998-09-17 |
DE69739584D1 (de) | 2009-10-29 |
EP0950257B1 (fr) | 2009-09-16 |
KR20060040750A (ko) | 2006-05-10 |
FR2755537A1 (fr) | 1998-05-07 |
KR20000052885A (ko) | 2000-08-25 |
FR2755537B1 (fr) | 1999-03-05 |
KR100654164B1 (ko) | 2006-12-05 |
EP0950257A2 (fr) | 1999-10-20 |
WO1998020543A2 (fr) | 1998-05-14 |
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