DE69739584D1 - Verfahren zur herstellung von einer dünnschicht auf einem träger - Google Patents

Verfahren zur herstellung von einer dünnschicht auf einem träger

Info

Publication number
DE69739584D1
DE69739584D1 DE69739584T DE69739584T DE69739584D1 DE 69739584 D1 DE69739584 D1 DE 69739584D1 DE 69739584 T DE69739584 T DE 69739584T DE 69739584 T DE69739584 T DE 69739584T DE 69739584 D1 DE69739584 D1 DE 69739584D1
Authority
DE
Germany
Prior art keywords
producing
support
thin layer
thin
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69739584T
Other languages
English (en)
Inventor
Bernard Aspar
Michel Bruel
Thierry Barge
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Application granted granted Critical
Publication of DE69739584D1 publication Critical patent/DE69739584D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
DE69739584T 1996-11-05 1997-11-04 Verfahren zur herstellung von einer dünnschicht auf einem träger Expired - Lifetime DE69739584D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9613449A FR2755537B1 (fr) 1996-11-05 1996-11-05 Procede de fabrication d'un film mince sur un support et structure ainsi obtenue
PCT/FR1997/001969 WO1998020543A2 (fr) 1996-11-05 1997-11-04 Procede de fabrication d'un film mince sur un support et structure ainsi obtenue

Publications (1)

Publication Number Publication Date
DE69739584D1 true DE69739584D1 (de) 2009-10-29

Family

ID=9497325

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69739584T Expired - Lifetime DE69739584D1 (de) 1996-11-05 1997-11-04 Verfahren zur herstellung von einer dünnschicht auf einem träger

Country Status (7)

Country Link
US (1) US6335258B1 (de)
EP (1) EP0950257B1 (de)
JP (1) JP2001503568A (de)
KR (2) KR20060040750A (de)
DE (1) DE69739584D1 (de)
FR (1) FR2755537B1 (de)
WO (1) WO1998020543A2 (de)

Families Citing this family (86)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020089016A1 (en) * 1998-07-10 2002-07-11 Jean-Pierre Joly Thin layer semi-conductor structure comprising a heat distribution layer
FR2795866B1 (fr) * 1999-06-30 2001-08-17 Commissariat Energie Atomique Procede de realisation d'une membrane mince et structure a membrane ainsi obtenue
FR2809867B1 (fr) * 2000-05-30 2003-10-24 Commissariat Energie Atomique Substrat fragilise et procede de fabrication d'un tel substrat
US7045878B2 (en) 2001-05-18 2006-05-16 Reveo, Inc. Selectively bonded thin film layer and substrate layer for processing of useful devices
US6956268B2 (en) 2001-05-18 2005-10-18 Reveo, Inc. MEMS and method of manufacturing MEMS
US7163826B2 (en) 2001-09-12 2007-01-16 Reveo, Inc Method of fabricating multi layer devices on buried oxide layer substrates
US6875671B2 (en) 2001-09-12 2005-04-05 Reveo, Inc. Method of fabricating vertical integrated circuits
EP2164096B1 (de) * 2002-07-17 2012-09-05 Soitec Verfahren zur Glättung der Kontur einer nützlichen, auf ein Trägersubstrat übertragenen Materialschicht
FR2850390B1 (fr) * 2003-01-24 2006-07-14 Soitec Silicon On Insulator Procede d'elimination d'une zone peripherique de colle lors de la fabrication d'un substrat composite
US7122095B2 (en) * 2003-03-14 2006-10-17 S.O.I.Tec Silicon On Insulator Technologies S.A. Methods for forming an assembly for transfer of a useful layer
EP1482548B1 (de) 2003-05-26 2016-04-13 Soitec Verfahren zur Herstellung von Halbleiterscheiben
FR2855910B1 (fr) * 2003-06-06 2005-07-15 Commissariat Energie Atomique Procede d'obtention d'une couche tres mince par amincissement par auto-portage provoque
FR2855908B1 (fr) * 2003-06-06 2005-08-26 Soitec Silicon On Insulator Procede d'obtention d'une structure comprenant au moins un substrat et une couche ultramince
US7344957B2 (en) * 2005-01-19 2008-03-18 Texas Instruments Incorporated SOI wafer with cooling channels and a method of manufacture thereof
US7674687B2 (en) * 2005-07-27 2010-03-09 Silicon Genesis Corporation Method and structure for fabricating multiple tiled regions onto a plate using a controlled cleaving process
US7642934B2 (en) * 2006-11-10 2010-01-05 Research In Motion Limited Method of mapping a traditional touchtone keypad on a handheld electronic device and associated apparatus
WO2008081987A1 (en) * 2006-12-28 2008-07-10 Fujifilm Corporation Joining method and joining members
EP2155769B1 (de) * 2007-05-04 2012-06-27 Katholieke Universiteit Leuven KU Leuven Research & Development Schutz gegen gewebedegeneration
US9059247B2 (en) * 2007-05-18 2015-06-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate and method for manufacturing semiconductor device
CN102099894B (zh) 2008-08-27 2014-04-16 S.O.I.Tec绝缘体上硅技术公司 制造半导体结构或使用具有选择或受控晶格参数的半导体材料层的器件的方法
FR2936904B1 (fr) 2008-10-03 2011-01-14 Soitec Silicon On Insulator Procedes et structures pour alterer la contrainte dans des materiaux nitrure iii.
US8367520B2 (en) * 2008-09-22 2013-02-05 Soitec Methods and structures for altering strain in III-nitride materials
US8486771B2 (en) * 2008-09-24 2013-07-16 Soitec Methods of forming relaxed layers of semiconductor materials, semiconductor structures, devices and engineered substrates including same
US8637383B2 (en) 2010-12-23 2014-01-28 Soitec Strain relaxation using metal materials and related structures
WO2010056443A1 (en) 2008-10-30 2010-05-20 S.O.I.Tec Silicon On Insulator Technologies Methods of forming layers of semiconductor material having reduced lattice strain, semiconductor structures, devices and engineered substrates including same
JP5496598B2 (ja) * 2008-10-31 2014-05-21 信越化学工業株式会社 シリコン薄膜転写絶縁性ウェーハの製造方法
US8679942B2 (en) 2008-11-26 2014-03-25 Soitec Strain engineered composite semiconductor substrates and methods of forming same
US8278167B2 (en) 2008-12-18 2012-10-02 Micron Technology, Inc. Method and structure for integrating capacitor-less memory cell with logic
US20100187568A1 (en) * 2009-01-28 2010-07-29 S.O.I.Tec Silicon On Insulator Technologies, S.A. Epitaxial methods and structures for forming semiconductor materials
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
US8198172B2 (en) * 2009-02-25 2012-06-12 Micron Technology, Inc. Methods of forming integrated circuits using donor and acceptor substrates
US8178396B2 (en) 2009-03-11 2012-05-15 Micron Technology, Inc. Methods for forming three-dimensional memory devices, and related structures
JP5529963B2 (ja) 2009-07-20 2014-06-25 ソイテック 半導体構造体または半導体デバイスを形成する方法および光起電力構造体
US8461566B2 (en) * 2009-11-02 2013-06-11 Micron Technology, Inc. Methods, structures and devices for increasing memory density
WO2011061580A1 (en) 2009-11-18 2011-05-26 S.O.I.Tec Silicon On Insulator Technologies Methods of fabricating semiconductor structures and devices using glass bonding layers, and semiconductor structures and devices formed by such methods
US8513722B2 (en) 2010-03-02 2013-08-20 Micron Technology, Inc. Floating body cell structures, devices including same, and methods for forming same
US8507966B2 (en) 2010-03-02 2013-08-13 Micron Technology, Inc. Semiconductor cells, arrays, devices and systems having a buried conductive line and methods for forming the same
US9608119B2 (en) 2010-03-02 2017-03-28 Micron Technology, Inc. Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices including such structures
US9646869B2 (en) * 2010-03-02 2017-05-09 Micron Technology, Inc. Semiconductor devices including a diode structure over a conductive strap and methods of forming such semiconductor devices
US8288795B2 (en) 2010-03-02 2012-10-16 Micron Technology, Inc. Thyristor based memory cells, devices and systems including the same and methods for forming the same
WO2011123199A1 (en) 2010-03-31 2011-10-06 S.O.I.Tec Silicon On Insulator Technologies Bonded semiconductor structures and method of forming same
US8461017B2 (en) 2010-07-19 2013-06-11 Soitec Methods of forming bonded semiconductor structures using a temporary carrier having a weakened ion implant region for subsequent separation along the weakened region
TW201214627A (en) 2010-09-10 2012-04-01 Soitec Silicon On Insulator Methods of forming through wafer interconnects in semiconductor structures using sacrificial material and semiconductor structures formes by such methods
WO2012085219A1 (en) 2010-12-23 2012-06-28 Soitec Strain relaxation using metal materials and related structures
US8436363B2 (en) 2011-02-03 2013-05-07 Soitec Metallic carrier for layer transfer and methods for forming the same
FR2972292B1 (fr) * 2011-03-01 2013-03-01 Soitec Silicon On Insulator Support métallique pour le transfert de couche et procédés pour former ce support
US9082948B2 (en) 2011-02-03 2015-07-14 Soitec Methods of fabricating semiconductor structures using thermal spray processes, and semiconductor structures fabricated using such methods
US9142412B2 (en) 2011-02-03 2015-09-22 Soitec Semiconductor devices including substrate layers and overlying semiconductor layers having closely matching coefficients of thermal expansion, and related methods
JP2012178548A (ja) * 2011-02-03 2012-09-13 Soytec 層移転用金属キャリア及びその形成方法
US8598621B2 (en) 2011-02-11 2013-12-03 Micron Technology, Inc. Memory cells, memory arrays, methods of forming memory cells, and methods of forming a shared doped semiconductor region of a vertically oriented thyristor and a vertically oriented access transistor
US8952418B2 (en) 2011-03-01 2015-02-10 Micron Technology, Inc. Gated bipolar junction transistors
US8519431B2 (en) 2011-03-08 2013-08-27 Micron Technology, Inc. Thyristors
US8338294B2 (en) 2011-03-31 2012-12-25 Soitec Methods of forming bonded semiconductor structures including two or more processed semiconductor structures carried by a common substrate, and semiconductor structures formed by such methods
US20120248621A1 (en) * 2011-03-31 2012-10-04 S.O.I.Tec Silicon On Insulator Technologies Methods of forming bonded semiconductor structures, and semiconductor structures formed by such methods
US8970045B2 (en) 2011-03-31 2015-03-03 Soitec Methods for fabrication of semiconductor structures including interposers with conductive vias, and related structures and devices
FR2978600B1 (fr) 2011-07-25 2014-02-07 Soitec Silicon On Insulator Procede et dispositif de fabrication de couche de materiau semi-conducteur
US8772848B2 (en) 2011-07-26 2014-07-08 Micron Technology, Inc. Circuit structures, memory circuitry, and methods
US8842945B2 (en) 2011-08-09 2014-09-23 Soitec Methods of forming three dimensionally integrated semiconductor systems including photoactive devices and semiconductor-on-insulator substrates
TWI500123B (zh) 2011-08-09 2015-09-11 Soitec Silicon On Insulator 包含內有一個或多個電性、光學及流體互連之互連層之黏附半導體構造之形成方法及應用此等方法形成之黏附半導體構造
US8728863B2 (en) 2011-08-09 2014-05-20 Soitec Methods of forming bonded semiconductor structures including interconnect layers having one or more of electrical, optical, and fluidic interconnects therein, and bonded semiconductor structures formed using such methods
US8617925B2 (en) 2011-08-09 2013-12-31 Soitec Methods of forming bonded semiconductor structures in 3D integration processes using recoverable substrates, and bonded semiconductor structures formed by such methods
US8841742B2 (en) * 2011-09-27 2014-09-23 Soitec Low temperature layer transfer process using donor structure with material in recesses in transfer layer, semiconductor structures fabricated using such methods
US8673733B2 (en) * 2011-09-27 2014-03-18 Soitec Methods of transferring layers of material in 3D integration processes and related structures and devices
TWI573198B (zh) 2011-09-27 2017-03-01 索泰克公司 在三度空間集積製程中轉移材料層之方法及其相關結構與元件
WO2013093590A1 (en) 2011-12-23 2013-06-27 Soitec Methods of fabricating semiconductor structures using thermal spray processes, and semiconductor structures fabricated using such methods
US9136134B2 (en) 2012-02-22 2015-09-15 Soitec Methods of providing thin layers of crystalline semiconductor material, and related structures and devices
JP6193271B2 (ja) 2012-02-22 2017-09-06 ソイテック 結晶半導体材料の薄層を設ける方法、ならびに関連する構造体およびデバイス
WO2013132332A1 (en) 2012-03-09 2013-09-12 Soitec Methods for forming semiconductor structures including iii-v semiconductor material using substrates comprising molybdenum, and structures formed by such methods
US8916483B2 (en) 2012-03-09 2014-12-23 Soitec Methods of forming semiconductor structures including III-V semiconductor material using substrates comprising molybdenum
US8980688B2 (en) 2012-06-28 2015-03-17 Soitec Semiconductor structures including fluidic microchannels for cooling and related methods
US9511996B2 (en) 2012-07-31 2016-12-06 Soitec Methods of forming semiconductor structures including MEMS devices and integrated circuits on common sides of substrates, and related structures and devices
WO2014020389A1 (en) 2012-07-31 2014-02-06 Soitec Methods of forming semiconductor structures including a conductive interconnection, and related structures
CN104507853B (zh) 2012-07-31 2016-11-23 索泰克公司 形成半导体设备的方法
WO2014020390A1 (en) 2012-07-31 2014-02-06 Soitec Methods for fabrication of semiconductor structures using laser lift-off process, and related semiconductor structures
WO2014030040A1 (en) * 2012-08-24 2014-02-27 Soitec Methods of forming semiconductor structures and devices including graphene, and related structures and devices
TWI588955B (zh) 2012-09-24 2017-06-21 索泰克公司 使用多重底材形成iii-v族半導體結構之方法及應用此等方法所製作之半導體元件
JP6056516B2 (ja) * 2013-02-01 2017-01-11 信越半導体株式会社 Ｓｏｉウェーハの製造方法及びｓｏｉウェーハ
TWI602315B (zh) 2013-03-08 2017-10-11 索泰克公司 具有經組構成效能更佳之低帶隙主動層之感光元件及相關方法
TWI648872B (zh) 2013-03-15 2019-01-21 法商梭意泰科公司 具有包含ＩｎＧａＮ之作用區域之半導體結構、形成此等半導體結構之方法及由此等半導體結構所形成之發光裝置
FR3003397B1 (fr) 2013-03-15 2016-07-22 Soitec Silicon On Insulator Structures semi-conductrices dotées de régions actives comprenant de l'INGAN
TWI593135B (zh) 2013-03-15 2017-07-21 索泰克公司 具有含氮化銦鎵之主動區域之半導體結構，形成此等半導體結構之方法，以及應用此等半導體結構形成之發光元件
WO2014206737A1 (en) 2013-06-27 2014-12-31 Soitec Methods of fabricating semiconductor structures including cavities filled with a sacrifical material
KR101608273B1 (ko) * 2014-09-05 2016-04-01 코닝정밀소재 주식회사 유기발광소자용 광추출 기판 제조방법, 유기발광소자용 광추출 기판 및 이를 포함하는 유기발광소자
US9209301B1 (en) 2014-09-18 2015-12-08 Soitec Method for fabricating semiconductor layers including transistor channels having different strain states, and related semiconductor layers
US9219150B1 (en) 2014-09-18 2015-12-22 Soitec Method for fabricating semiconductor structures including fin structures with different strain states, and related semiconductor structures
US9165945B1 (en) 2014-09-18 2015-10-20 Soitec Method for fabricating semiconductor structures including transistor channels having different strain states, and related semiconductor structures

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2812405B2 (ja) * 1991-03-15 1998-10-22 信越半導体株式会社 半導体基板の製造方法
US5256581A (en) * 1991-08-28 1993-10-26 Motorola, Inc. Silicon film with improved thickness control
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JP2609198B2 (ja) * 1992-08-07 1997-05-14 信越半導体株式会社 半導体基板の製造方法
FR2714524B1 (fr) * 1993-12-23 1996-01-26 Commissariat Energie Atomique Procede de realisation d'une structure en relief sur un support en materiau semiconducteur
JP3352340B2 (ja) * 1995-10-06 2002-12-03 キヤノン株式会社 半導体基体とその製造方法
FR2725074B1 (fr) * 1994-09-22 1996-12-20 Commissariat Energie Atomique Procede de fabrication d'une structure comportant une couche mince semi-conductrice sur un substrat
FR2744285B1 (fr) * 1996-01-25 1998-03-06 Commissariat Energie Atomique Procede de transfert d'une couche mince d'un substrat initial sur un substrat final
FR2748851B1 (fr) * 1996-05-15 1998-08-07 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
US6150239A (en) * 1997-05-31 2000-11-21 Max Planck Society Method for the transfer of thin layers monocrystalline material onto a desirable substrate
US5920764A (en) * 1997-09-30 1999-07-06 International Business Machines Corporation Process for restoring rejected wafers in line for reuse as new

Also Published As

Publication number Publication date
EP0950257B1 (de) 2009-09-16
JP2001503568A (ja) 2001-03-13
KR100654164B1 (ko) 2006-12-05
FR2755537B1 (fr) 1999-03-05
KR20060040750A (ko) 2006-05-10
EP0950257A2 (de) 1999-10-20
WO1998020543A3 (fr) 1998-09-17
WO1998020543A2 (fr) 1998-05-14
US6335258B1 (en) 2002-01-01
FR2755537A1 (fr) 1998-05-07
KR20000052885A (ko) 2000-08-25

Similar Documents

Publication Publication Date Title
DE69739584D1 (de) Verfahren zur herstellung von einer dünnschicht auf einem träger
DE69700945D1 (de) Verfahren zur herstellung einer gesinterten struktur auf einem substrat
DE69727655D1 (de) Verfahren zur herstellung einer cdte-schicht
DE69735011D1 (de) Verfahren zur Herstellung einer piezoelektrischen Dünnschichtanordnung
DE69828198D1 (de) Verfahren zur herstellung einer thermoplastischen beschichtung
DE69621335D1 (de) Verfahren zur herstellung einer membranhaltenden mikrostruktur
DE69619691T2 (de) Verfahren zur herstellung einer beugungsstruktur
DE69723724D1 (de) Verfahren zur herstellung von polyurethan-peo-heparin-beschichtungen
DE69910614D1 (de) Verfahren zur herstellung einer verbundbeschichtung auf einem substrat
DE69621723D1 (de) Verfahren zur Herstellung einer Schicht
DE69606865D1 (de) Verfahren zur herstellung einer reflektiven folie
DE59609364D1 (de) Verfahren zur herstellung einer lochscheibe
DE69625086D1 (de) Verfahren zur herstellung einer polyestermehrschichtfolie
DE69607546D1 (de) Verfahren zur Herstellung einer Schaltungsanordnung
DE59707781D1 (de) VERFAHREN ZUR HERSTELLUNG EINER FüLLSTOFFHALTIGEN BEDRUCKBAREN POLYMERFOLIE
DE69707005D1 (de) Verfahren zur herstellung einer parylenbeschichtung
DE69701594T2 (de) Verfahren zur herstellung von polysilazan
DE59408258D1 (de) Verfahren zur herstellung einer hartstoffschicht
DE69802250D1 (de) Verfahren zur herstellung einer leitschicht auf einem substrat
DE69804806D1 (de) Verfahren zur herstellung einer kunststofffolie
DE59703321D1 (de) Verfahren zur Herstellung einer Beschichtung
DE69027850T2 (de) Verfahren zur herstellung einer kohlenstoffschicht
DE948435T1 (de) Verfahren zur herstellung einer anzeige
DE59611454D1 (de) Verfahren zur Herstellung einer Verbundanordnung
DE59700065D1 (de) Verfahren zur Herstellung einer photochromen Schicht

Legal Events

Date Code Title Description
8364 No opposition during term of opposition