WO2014118851A1 - Soiウェーハの製造方法及びsoiウェーハ - Google Patents
Soiウェーハの製造方法及びsoiウェーハ Download PDFInfo
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- WO2014118851A1 WO2014118851A1 PCT/JP2013/007248 JP2013007248W WO2014118851A1 WO 2014118851 A1 WO2014118851 A1 WO 2014118851A1 JP 2013007248 W JP2013007248 W JP 2013007248W WO 2014118851 A1 WO2014118851 A1 WO 2014118851A1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 238000010438 heat treatment Methods 0.000 claims abstract description 71
- 230000003746 surface roughness Effects 0.000 claims abstract description 37
- 238000009832 plasma treatment Methods 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims description 51
- 239000013078 crystal Substances 0.000 claims description 23
- -1 Hydrogen ions Chemical class 0.000 claims description 22
- 238000005468 ion implantation Methods 0.000 claims description 21
- 239000001257 hydrogen Substances 0.000 claims description 19
- 229910052739 hydrogen Inorganic materials 0.000 claims description 19
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 150000002500 ions Chemical class 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 238000004299 exfoliation Methods 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 238000012545 processing Methods 0.000 claims description 5
- 238000000926 separation method Methods 0.000 abstract description 15
- 230000007547 defect Effects 0.000 abstract description 12
- 235000012431 wafers Nutrition 0.000 description 190
- 206010040844 Skin exfoliation Diseases 0.000 description 37
- 239000010408 film Substances 0.000 description 35
- 230000000052 comparative effect Effects 0.000 description 12
- 239000001307 helium Substances 0.000 description 9
- 229910052734 helium Inorganic materials 0.000 description 9
- 230000003647 oxidation Effects 0.000 description 9
- 238000007254 oxidation reaction Methods 0.000 description 9
- 230000001133 acceleration Effects 0.000 description 6
- 238000000137 annealing Methods 0.000 description 6
- 238000002513 implantation Methods 0.000 description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- 230000032798 delamination Effects 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 230000003313 weakening effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000005461 lubrication Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000011856 silicon-based particle Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/34—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being on the surface
Definitions
- the present invention relates to a method for manufacturing an SOI wafer using a so-called ion implantation separation method, in which an ion-implanted wafer is bonded and then peeled to manufacture an SOI wafer, and to an SOI wafer manufactured by this method.
- an oxide film is formed on at least one of two silicon wafers, and hydrogen ions or rare gases are formed from the upper surface of one silicon wafer (bond wafer). Gas ions such as ions are implanted to form a microbubble layer (encapsulation layer) inside the wafer. Then, the ion-implanted surface is brought into intimate contact with the other silicon wafer (base wafer) through an oxide film, and then a heat treatment (peeling heat treatment) is applied to form a microbubble layer as a peeled surface to bond one wafer (bond wafer). The thin film is peeled off, and further heat treatment (bonding heat treatment) is applied to firmly bond to form an SOI wafer (see Patent Documents 1 and 2).
- an SOI wafer having an SOI layer having a mirror surface and a highly uniform film thickness can be obtained relatively easily.
- a damage layer due to ion implantation exists on the surface of the bonded wafer after delamination, and the surface is compared with the mirror surface of a normal product level silicon single crystal wafer. Roughness becomes large. Therefore, it is necessary to remove such a damaged layer and surface roughness in the production by the ion implantation separation method.
- polishing polish Removal allowance: about 100 nm
- the amount of polishing is not uniform in the plane, so that the thin film is achieved by implantation and peeling of hydrogen ions and the like. There arises a problem that the thickness uniformity deteriorates.
- the implantation is performed with a dose amount of about 1.5 times that of the smart cut method, and then the bonding surface of the bond wafer and the base wafer is plasma-treated and bonded, and heat treatment is performed.
- the ion-implanted layer is weakened by heat treatment under a heat treatment condition (for example, low-temperature heat treatment of 350 ° C. or lower) that does not cause peeling, and then, for example, a wedge-shaped member is placed on the outer peripheral edge near the bonding surface at room temperature.
- both hydrogen ions and helium ions are ion-implanted
- Patent Documents 4 and 5 both hydrogen ions and helium ions are ion-implanted into the bond wafer, and then bonded to the base wafer, followed by exfoliation heat treatment, for example, at 500 ° C. for about 30 minutes, and delamination at the ion implantation layer
- This method is capable of peeling with a small dose compared to the smart cut method using single ion implantation, and can also improve the surface roughness of the peeled surface.
- the SOI wafer manufacturing method using the ion implantation separation method can be classified into three methods (smart cut method, SiGen method, and co-implantation method).
- the smart cut method is a level that does not pose a major problem with respect to the SOI layer thickness range and the terrace shape, but the surface roughness of the SOI layer surface is larger than other methods.
- the surface roughness of the SOI layer surface can be kept small, but since a wedge is inserted during room temperature separation, the film thickness distribution changes greatly between the region where the separation occurs initially and the boundary where the separation occurs thereafter. When the range becomes large and the separation is forcibly separated, the terrace shape will be uneven or chipped.
- the surface roughness of the SOI layer surface can be kept small as in the SiGen method, and there is no significant problem with the SOI layer thickness range or terrace shape. And blisters tend to occur more frequently.
- An SOI wafer as a finished product shipped to a device manufacturer has a small SOI layer thickness range, a small surface roughness of the SOI layer surface, a smooth terrace shape, and voids, blisters, etc. in the SOI layer. What is free of defects is required.
- the terrace portion is a region where the SOI layer is not transferred at the outer peripheral portion of the peeled SOI wafer and the surface of the base wafer is exposed. This is about several mm of the outer peripheral portion of the mirror-polished wafer.
- the main reason is that the flatness of the wafer deteriorates, so that the bonding force between the bonded wafers is weak, and the SOI layer is difficult to be transferred to the base wafer side.
- the present invention has been made in view of the above circumstances, the SOI layer thickness range is small, the surface roughness of the SOI layer surface is small, the shape of the terrace portion is smooth, and defects such as voids and blisters are present in the SOI layer. It is an object of the present invention to provide a method for manufacturing an SOI wafer without any SOI wafer.
- the present invention has been made to solve the above problems, Hydrogen ions are implanted from the surface of a bond wafer made of a silicon single crystal wafer to form an ion implantation layer, and the ion implanted surface of the bond wafer and a base wafer surface made of a silicon single crystal wafer are interposed via an oxide film.
- a peeling heat treatment is performed and the bond wafer is peeled off by the ion implantation layer.
- the bonding is performed through the oxide film.
- exfoliation heat treatment by performing a first step of performing a heat treatment for 2 hours or more at a temperature of 250 ° C. or less and a second step of performing a heat treatment for 30 minutes or more at a temperature of 400 ° C. or more and 450 ° C. or less, An SOI wafer manufacturing method is provided, wherein the bond wafer is peeled off by an injection layer.
- the voids and blisters are not affected by the generation of voids and blisters caused by the implantation of helium ions. Does not have such defects.
- the wafer is plasma-treated and bonded to strengthen the bonding force, and then heat treatment (first step and second step) is performed in two steps at a relatively low temperature. The surface roughness of the SOI layer surface can be reduced by weakening the ion-implanted layer and performing peeling.
- the SOI film thickness range can be reduced, and the shape of the terrace portion can be reduced. It can be smooth.
- the plasma treatment is performed by performing nitrogen plasma treatment on a wafer having an oxide film and performing oxygen plasma treatment on a wafer having no oxide film.
- a wafer processed under such conditions is advantageous because the wafer peeling is completed at a relatively low temperature, and an SOI wafer having a small surface roughness on the peeling surface can be produced.
- planarization process can be performed without performing CMP.
- planarization treatment examples include sacrificial oxidation treatment + Ar annealing + sacrificial oxidation treatment.
- the SOI wafer manufactured in this way is advantageous because the SOI layer has particularly excellent film thickness uniformity and can further reduce the SOI layer film thickness range.
- the SOI wafer manufactured in this way has a surface roughness (RMS) of the SOI layer surface, which is a release surface, of 3 nm or less, and the film thickness range of the SOI layer is 1.5 nm or less. can do.
- RMS surface roughness
- the SOI layer thickness range and the surface roughness of the SOI layer surface are extremely small, the shape of the terrace portion is smooth, and the SOI layer has no defects such as voids and blisters. This is convenient as a finished product shipped to a device manufacturer.
- the SOI layer thickness range is small, the surface roughness of the SOI layer surface is small, the shape of the terrace portion is smooth, and the SOI layer has no defects such as voids and blisters. Wafers can be manufactured.
- Example 1 is an example of the shape of a terrace portion of an SOI wafer manufactured by the method for manufacturing an SOI wafer of Example 1. It is an example of the shape of the terrace part of the SOI wafer manufactured by the manufacturing method of the SOI wafer of the comparative example 2.
- Hydrogen ions are implanted from the surface of a bond wafer made of a silicon single crystal wafer to form an ion implantation layer, and the ion implanted surface of the bond wafer and a base wafer surface made of a silicon single crystal wafer are interposed via an oxide film.
- a peeling heat treatment is performed and the bond wafer is peeled off by the ion implantation layer.
- the bonding is performed through the oxide film,
- the exfoliation heat treatment by performing a first step of performing a heat treatment for 2 hours or more at a temperature of 250 ° C. or less and a second step of performing a heat treatment for 30 minutes or more at a temperature of 400 ° C. or more and 450 ° C.
- the SOI wafer manufacturing method is characterized by peeling the bond wafer with an injection layer, the SOI layer thickness range is small, the surface roughness of the SOI layer surface is small, and the shape of the terrace portion is smooth, The inventors have found that an SOI wafer having no defects such as voids and blisters in the SOI layer can be produced, and the present invention has been completed.
- the present invention performs ion implantation of only hydrogen ions on a bond wafer, performs plasma treatment on at least one bonding surface of the bond wafer and the base wafer, and then bonds and peels them through an oxide film. Heat treatment is performed.
- the SOI layer is not affected by voids or blisters generated by injecting helium ions. Does not cause defects such as voids and blisters.
- the present invention strengthens the bonding force of the wafer by performing plasma treatment on at least one bonding surface of the bond wafer and the base wafer, and then performs a peeling treatment by a relatively low temperature heat treatment, The surface roughness of the SOI layer surface can be reduced.
- annealing is performed at 250 ° C. or lower for 2 hours or longer as the first step, and then the temperature is raised and annealing is performed at a temperature range of 400 to 450 ° C. for 30 minutes or longer as the second step. To weaken the ion-implanted layer and separate it.
- the wafer that has been plasma-processed and bonded has improved bonding strength compared to a normal bonded wafer.
- the first ion-implanted layer is weakened and the bonding strength of the wafer is strengthened, and then the bonding strength is further improved by heat treatment at 400 to 450 ° C.
- the weakening of the implanted layer is completed and wafer peeling occurs.
- plasma processing is performed on the wafer to strengthen the bonding force of the wafer, and heat treatment is performed to raise the temperature in two stages at a relatively low temperature (the first step and the second step), and ion implantation is performed step by step.
- the surface roughness of the SOI layer surface can be reduced by weakening the layer and performing peeling.
- the SOI layer thickness range can be reduced, and the terrace The shape of the part can be made smooth.
- the heat treatment time of the first step and the second step of the peeling heat treatment is preferably 8 hours or less and more preferably 4 hours or less in consideration of the efficiency of the peeling heat treatment. Therefore, the heat treatment temperature in the first step is preferably 150 ° C. or higher.
- the plasma treatment it is preferable to perform a nitrogen plasma treatment on a wafer having an oxide film, and an oxygen plasma treatment on a wafer having no oxide film (including a wafer on which only a natural oxide film is grown).
- a wafer processed under such conditions can be peeled off in a relatively short time at a relatively low temperature, and an SOI wafer having a smaller roughness of the peeled surface can be produced.
- the SOI wafer immediately after peeling produced in this manner has a small surface roughness on the surface of the SOI layer, a good thickness distribution of the SOI layer and a terrace shape, and no occurrence of blisters and voids.
- the surface roughness of the SOI layer surface is small, the surface roughness of the SOI layer surface of the finished SOI wafer should be sufficiently reduced even if the planarization process is performed only by heat treatment without using CMP. Can do.
- the SOI wafer manufactured in this way has a surface roughness (RMS) of the SOI layer surface, which is a peeled surface before flattening treatment, of 3 nm or less, and the SOI layer has a film thickness range of 1. It can be 5 nm or less.
- RMS surface roughness
- a high-quality SOI wafer can be manufactured by performing a planarization process without performing CMP on the peeled surface of the SOI wafer after the peeling.
- planarization process for example, a sacrificial oxidation process + Ar annealing + sacrificial oxidation process can be cited.
- the SOI wafer manufactured in this way is advantageous because it has excellent SOI layer thickness uniformity and a smaller SOI layer thickness range.
- the SOI layer thickness range and the surface roughness of the SOI layer surface are extremely small, and the shape of the terrace portion is smooth, and there are no defects such as voids or blisters in the SOI layer.
- Example 1 An SOI wafer was manufactured using a Si single crystal wafer having a diameter of 300 mm and a crystal orientation ⁇ 100>. At that time, a thermal oxide film having a thickness of 150 nm was grown on a bond wafer in a heat treatment furnace, and hydrogen ions (H + ions) were ion-implanted into the wafer at a dose of 5 ⁇ 10 16 / cm 2 with an acceleration energy of 40 keV. A base wafer made of a Si single crystal wafer was prepared, oxygen plasma treatment was performed only on the base wafer, and then bonded to an ion-implanted bond wafer. The bonded wafer is annealed at 200 ° C.
- the wafer was peeled off to become an initial SOI wafer.
- the wafer was peeled off to become an initial SOI wafer.
- the bonded wafer is annealed at 350 ° C. for 2 hours as the first step, then heated at a rate of temperature increase of 10 ° C./min, and annealed at 500 ° C. for 30 minutes as the second step. It was. By this heat treatment, the wafer was peeled off to become an initial SOI wafer.
- Table 1 summarizes the evaluation results of the four items of Example 1, Comparative Example 1 to Comparative Example 3, AFM roughness, SOI layer thickness range, terrace shape, and defects (voids, blisters).
- the AFM roughness in Table 1 is a value representing the surface roughness of a 30 ⁇ m square area measured by AFM (atomic force microscope) in RMS (Root Mean Square).
- Comparative Example 1 is about twice as large as the other examples, the surface roughness is large, and it can be expected that the subsequent planarization process will be loaded.
- Comparative Example 2 only Comparative Example 2 was large. This is because when wafer separation is performed, wafer separation occurs around the wedge at the moment when the wedge is inserted, and then the wafer is further separated by advancing the wedge toward the center of the wafer. The film thickness changes abruptly at the boundary between this initial wafer separation region and the subsequent separation region. This causes a large film thickness distribution.
- Comparative Example 3 As for the occurrence of defects, only Comparative Example 3 occurred. This is because ion implantation of He (helium) and H (hydrogen) is performed, and therefore, the process is most likely to cause particle adhesion in the manufacturing process. The occurrence is thought to be more than other examples. Although not shown in the table, in other examples performed under the same conditions as Comparative Example 3 except that plasma treatment was performed before bonding, the occurrence of blisters decreased, but the generation of voids increased. The total number of blister defects did not change.
- Example 1 An experiment combining the first step and the second step of wafer separation (peeling) was performed under the following conditions.
- An SOI wafer was manufactured using a Si single crystal wafer having a diameter of 300 mm and a crystal orientation ⁇ 100> as a bond wafer and a base wafer.
- a 150 nm thermal oxide film was grown on a bond wafer in a heat treatment furnace. Hydrogen was ion-implanted into this wafer at an acceleration energy of 40 keV at a dose of 5 ⁇ 10 16 / cm 2 .
- a base wafer (no oxide film) was prepared, and the base wafer was subjected to nitrogen plasma treatment and then bonded.
- the bonded wafer is annealed for 2 hours in the range of 150 to 350 ° C. as the first step, heated at 10 ° C./min, and annealed at 350 to 500 ° C. as the second step. (Refer to Table 2 for the heat treatment conditions of the first step and the second step).
- an initial SOI wafer was produced by peeling off the ion-implanted layer (some may not be peeled depending on the heat treatment conditions).
- the initial SOI wafer is sequentially subjected to sacrificial oxidation treatment at 900 ° C. for 2 hours (thermal oxidation + oxide film removal), annealing at 1200 ° C.
- Example 2 The same conditions as in Experimental Example 1 except that the heat treatment time of the first step was 4 hours and the second step was 3 conditions of 350 ° C., 4 hours, 400 ° C., 0.5 hour, 450 ° C., 0.5 hour.
- a finished product of an SOI wafer was produced, and the surface roughness (RMS) of the SOI layer surface was measured by AFM in the range of 30 ⁇ m ⁇ 30 ⁇ m and compared. The results are shown in Table 3 below.
- the surface roughness (RMS) of the SOI layer surface is extremely small when heat treatment is performed in the range of 150 ° C. to 250 ° C. for 4 hours as the first step, and heat treatment is performed for 30 minutes at 400 ° C. to 450 ° C. as the second step. .
- the heat treatment temperature in the second step after the heat treatment in the first step was 350 ° C. (less than 400 ° C.), peeling was not performed even after the heat treatment for 4 hours.
- Example 3 A completed SOI wafer was fabricated under the same conditions as in Experimental Example 1, except that the heat treatment time for the first step was 1 hour and the second step was 2 conditions of 350 ° C., 4 hours, 400 ° C., and 0.5 hour.
- the surface roughness (RMS) of the SOI layer surface was measured by AFM in the range of 30 ⁇ m ⁇ 30 ⁇ m and compared. The results are shown in Table 4 below.
- the heat treatment time of the first step was 1 hour (less than 2 hours), even if heat treatment was performed at 400 ° C. for 30 minutes as the second step, the wafer was not partly peeled off. Further, when the heat treatment time in the first step was 1 hour (less than 2 hours) and the heat treatment temperature in the second step was 350 ° C. (less than 400 ° C.), peeling was not performed even after the heat treatment for 4 hours.
- Example 4 A finished SOI wafer was produced under the same conditions as in Experimental Example 1 (some conditions were not implemented) except that plasma treatment was not performed before bonding, and the surface roughness (RMS) of the SOI layer surface was measured with AFM. And measured in the range of 30 ⁇ m ⁇ 30 ⁇ m. The results are shown in Table 5 below.
- the heat treatment is performed in the range of 150 ° C. to 250 ° C. for 2 hours as the first step, and the heat treatment is performed at 400 ° C. for 4 hours or 450 ° C. for 1 hour as the second step. Even when the wafer was not peeled off, the surface roughness (RMS) of the SOI layer surface was large.
- a completed SOI wafer was produced under the following conditions.
- An SOI was manufactured using a Si single crystal wafer having a diameter of 300 mm and a crystal orientation ⁇ 100> as a bond wafer and a base wafer.
- a 150 nm thermal oxide film was grown on a bond wafer in a heat treatment furnace. Hydrogen was ion-implanted into this wafer at an acceleration energy of 40 keV at a dose of 5 ⁇ 10 16 / cm 2 .
- a base wafer (no oxide film) was prepared, plasma treatment was performed on both, and bonding was then performed.
- the plasma conditions were as shown in Table 6 below.
- the bonded wafer is annealed at 200 ° C. for 4 hours as the first step, then heated at a rate of temperature increase of 10 ° C./min, and annealed at 400 ° C. for 4 hours as the second step. Went.
- This heat treatment peeled off the ion implantation layer, and an initial SOI wafer was produced.
- This initial SOI wafer was subjected to sacrificial oxidation treatment at 900 ° C. for 2 hours, annealing in an Ar atmosphere at 1200 ° C. for 1 hour, and sacrificial oxidation treatment for film thickness adjustment at 950 ° C. to complete an SOI wafer with an SOI layer thickness of 88 nm.
- the surface roughness (RMS) of the SOI layer surface was measured by AFM in the range of 30 ⁇ m ⁇ 30 ⁇ m and compared.
- the surface roughness (RMS) was as follows. Condition (1) 0.17 nm Condition (2) 0.14 nm Condition (3) 0.17 nm Condition (4) 0.15 nm
- RMS surface roughness
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Abstract
Description
スマートカット法は、SOI層膜厚レンジ及びテラス形状については大きな問題にはならないレベルであるが、SOI層表面の表面粗さは他の方法と比較して大きい。
SiGen法ではSOI層表面の表面粗さは小さく抑えられるが、室温分離の際に楔を入れるため、初期に分離が起こる領域とその後分離が起こる境界で膜厚分布が大きく変化しSOI層膜厚レンジが大きくなり、また強制的に分離する事によってテラス形状は凹凸の形状や欠けが発生してしまう。
水素とヘリウムの共注入では、SiGen法と同様にSOI層表面の表面粗さは小さく抑えられ、かつ、SOI層膜厚レンジやテラス形状にも大きな問題はないが、Heを注入した影響でボイドやブリスターの発生が多くなる傾向がある。
シリコン単結晶ウェーハからなるボンドウェーハの表面から水素イオンを注入してイオン注入層を形成し、該ボンドウェーハのイオン注入した表面と、シリコン単結晶ウェーハからなるベースウェーハ表面とを酸化膜を介して貼り合わせた後、剥離熱処理を行い前記イオン注入層でボンドウェーハを剥離することによりSOIウェーハを作製するSOIウェーハの製造方法において、
前記ボンドウェーハの貼り合わせ面と前記ベースウェーハの貼り合わせ面の少なくとも一方の表面にプラズマ処理を施した後に前記酸化膜を介して貼り合わせを行い、
前記剥離熱処理では、250℃以下の温度で2時間以上の熱処理を行う第一ステップと、400℃以上450℃以下の温度で30分以上の熱処理を行う第二ステップとを行うことによって、前記イオン注入層で前記ボンドウェーハを剥離することを特徴とするSOIウェーハの製造方法を提供する。
また、本発明は、剥離の際に(楔を入れて機械的に剥離するのではなく)熱処理によりイオン注入層を剥離するので、SOI膜厚レンジを小さくすることができ、テラス部の形状をスムーズにすることができる。
シリコン単結晶ウェーハからなるボンドウェーハの表面から水素イオンを注入してイオン注入層を形成し、該ボンドウェーハのイオン注入した表面と、シリコン単結晶ウェーハからなるベースウェーハ表面とを酸化膜を介して貼り合わせた後、剥離熱処理を行い前記イオン注入層でボンドウェーハを剥離することによりSOIウェーハを作製するSOIウェーハの製造方法において、
前記ボンドウェーハの貼り合わせ面と前記ベースウェーハの貼り合わせ面の少なくとも一方の表面にプラズマ処理を施した後に前記酸化膜を介して貼り合わせを行い、
前記剥離熱処理では、250℃以下の温度で2時間以上の熱処理を行う第一ステップと、400℃以上450℃以下の温度で30分以上の熱処理を行う第二ステップとを行うことによって、前記イオン注入層で前記ボンドウェーハを剥離することを特徴とするSOIウェーハの製造方法であれば、SOI層膜厚レンジが小さく、SOI層表面の表面粗さが小さく、テラス部の形状がスムーズであり、SOI層にボイドやブリスターなどの欠陥の無いSOIウェーハを製造することができることを見出し、本発明を完成させた。
直径300mm、結晶方位<100>のSi単結晶ウェーハを用いてSOIウェーハを作製した。その際、ボンドウェーハに150nmの熱酸化膜を熱処理炉で成長させ、このウェーハに水素イオン(H+イオン)を5×1016/cm2のドーズ量で40keVの加速エネルギーでイオン注入した。Si単結晶ウェーハからなるベースウェーハを用意して、ベースウェーハのみに酸素プラズマ処理を行い、その後、イオン注入されたボンドウェーハと貼り合わせを行った。この貼り合わせたウェーハに対し、第一ステップとして200℃、4時間のアニールを行った後、10℃/分の昇温速度で昇温し、第二ステップとして400℃、6時間のアニールを行った。この熱処理によりウェーハは剥離され初期SOIウェーハとなった。
直径300mm、結晶方位<100>のSi単結晶ウェーハを用いてSOIウェーハを作製した。その際、ボンドウェーハに150nmの熱酸化膜を熱処理炉で成長させ、このウェーハに水素イオン(H+イオン)を5×1016/cm2のドーズ量で40keVの加速エネルギーでイオン注入した。Si単結晶ウェーハからなるベースウェーハを用意して、イオン注入されたボンドウェーハと貼り合わせを行った(プラズマ処理なし)。この貼り合わせたウェーハに対し、第一ステップとして350℃、2時間のアニールを行った後、10℃/分の昇温速度で昇温し、第二ステップとして500℃、30分のアニールを行った。この熱処理によりウェーハは剥離され初期SOIウェーハとなった。
直径300mm、結晶方位<100>のSi単結晶ウェーハを用いてSOIウェーハを作製した。その際、ボンドウェーハに150nmの熱酸化膜を熱処理炉で成長させ、このウェーハに水素イオン(H+イオン)を7.5×1016/cm2のドーズ量で40keVの加速エネルギーでイオン注入した。Si単結晶ウェーハからなるベースウェーハを用意してベースウェーハのみに酸素プラズマ処理を行い、その後、イオン注入されたボンドウェーハと貼り合わせを行った。この貼り合わせたウェーハに対し350℃、2時間のアニールのみを行った。この状態ではまだウェーハ分離は行われず、楔を使用して室温でウェーハ剥離を行った。
直径300mm、結晶方位<100>のSi単結晶ウェーハを用いてSOIウェーハを作製した。その際、ボンドウェーハに150nmの熱酸化膜を熱処理炉で成長させ、このウェーハにヘリウムイオン(He+イオン)を0.9×1016/cm2のドーズ量で、水素イオン(H+イオン)を0.9×1016/cm2のドーズ量で40keVの加速エネルギーでイオン注入した。Si単結晶ウェーハからなるベースウェーハを用意して、イオン注入されたボンドウェーハと貼り合わせを行った(プラズマ処理なし)。この貼り合わせたウェーハに対し、第一ステップとして350℃、2時間のアニールを行った後、10℃/分の昇温速度で昇温し、第二ステップとして500℃、30分のアニールを行った。この熱処理によりウェーハは剥離され初期SOIウェーハとなった。
尚、表1のAFMラフネスとは、AFM(原子間力顕微鏡)により測定された30μm角の領域の表面粗さをRMS(Root Mean Square)表わした値である。
(実験例1)
ウェーハ分離(剥離)の第一ステップと第二ステップを組み合わせる実験を下記条件で行った。
ボンドウェーハ及びベースウェーハとして直径300mm、結晶方位<100>のSi単結晶ウェーハを用いてSOIウェーハを作製した。
まず、ボンドウェーハに150nmの熱酸化膜を熱処理炉で成長させた。このウェーハに水素を5×1016/cm2のドーズ量で40keVの加速エネルギーでイオン注入を行った。ベースウェーハ(酸化膜なし)を用意して、ベースウェーハに窒素プラズマ処理を行い、その後貼り合わせを行った。この貼り合わせたウェーハに対し、剥離熱処理として、第一ステップとして150~350℃の範囲で2時間のアニールを行い、10℃/分で昇温し、第二ステップとして350~500℃のアニールを行った(第一ステップ、第二ステップの熱処理条件は表2参照)。この熱処理によりイオン注入層で剥離され初期SOIウェーハが作製された(熱処理条件によっては剥離できないものもある)。この初期SOIウェーハに対し、900℃、2時間の犠牲酸化処理(熱酸化+酸化膜除去)、1200℃、1時間のAr雰囲気下のアニール、950℃の膜厚調整用犠牲酸化処理を順次行い、SOI層膜厚が88nmのSOIウェーハの完成品を作製し、そのSOI層表面の表面粗さ(RMS)をAFMで30μm×30μmの範囲で測定し比較した。結果を下記表2に示す。
第一ステップの熱処理時間を4時間とし、第二ステップを350℃,4時間、400℃,0.5時間、450℃,0.5時間の3条件とした以外は実験例1と同一条件でSOIウェーハの完成品を作製し、そのSOI層表面の表面粗さ(RMS)をAFMで30μm×30μmの範囲で測定し比較した。結果を下記表3に示す。
第一ステップの熱処理時間を1時間とし、第二ステップを350℃,4時間、400℃,0.5時間の2条件とした以外は実験例1と同一条件でSOIウェーハの完成品を作製し、そのSOI層表面の表面粗さ(RMS)をAFMで30μm×30μmの範囲で測定し比較した。結果を下記表4に示す。
貼り合わせ前にプラズマ処理を行わないこと以外は実験例1と同一条件(一部の条件は未実施)でSOIウェーハの完成品を作製し、そのSOI層表面の表面粗さ(RMS)をAFMで30μm×30μmの範囲で測定し比較した。結果を下記表5に示す。
プラズマ処理条件の効果を確認するため、下記の条件でSOIウェーハの完成品を作製した。
ボンドウェーハ及びベースウェーハとして直径300mm、結晶方位<100>のSi単結晶ウェーハを用いてSOIを作製した。
まず、ボンドウェーハに150nmの熱酸化膜を熱処理炉で成長させた。このウェーハに水素を5×1016/cm2のドーズ量で40keVの加速エネルギーでイオン注入を行った。ベースウェーハ(酸化膜なし)を用意して、両者にプラズマ処理を行い、その後貼り合わせを行った。
条件(1) 0.17nm
条件(2) 0.14nm
条件(3) 0.17nm
条件(4) 0.15nm
Claims (4)
- シリコン単結晶ウェーハからなるボンドウェーハの表面から水素イオンを注入してイオン注入層を形成し、該ボンドウェーハのイオン注入した表面と、シリコン単結晶ウェーハからなるベースウェーハ表面とを酸化膜を介して貼り合わせた後、剥離熱処理を行い前記イオン注入層でボンドウェーハを剥離することによりSOIウェーハを作製するSOIウェーハの製造方法において、
前記ボンドウェーハの貼り合わせ面と前記ベースウェーハの貼り合わせ面の少なくとも一方の表面にプラズマ処理を施した後に前記酸化膜を介して貼り合わせを行い、
前記剥離熱処理では、250℃以下の温度で2時間以上の熱処理を行う第一ステップと、400℃以上450℃以下の温度で30分以上の熱処理を行う第二ステップとを行うことによって、前記イオン注入層で前記ボンドウェーハを剥離することを特徴とするSOIウェーハの製造方法。 - 前記プラズマ処理は、酸化膜を有するウェーハに対しては窒素プラズマ処理を行い、酸化膜のないウェーハに対しては酸素プラズマ処理を行うことを特徴とする請求項1に記載のSOIウェーハの製造方法。
- 前記剥離後のSOIウェーハの剥離面に対し、CMPを行わずに平坦化処理を行うことを特徴とする請求項1又は請求項2に記載のSOIウェーハの製造方法。
- 請求項1又は請求項2のSOIウェーハの製造方法によって製造されたSOIウェーハであって、剥離面であるSOI層表面の表面粗さ(RMS)が3nm以下であり、かつ、該SOI層の膜厚レンジが1.5nm以下であることを特徴とするSOIウェーハ。
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