JP6028280B2 - 半導体構造又は半導体素子を製造する方法 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Description
Claims (13)
- 半導体構造又は半導体素子を製造する方法であって、
半導体材料の単結晶によって少なくとも実質的に構成された少なくとも1つのシード構造を、ガラスボンディング層を使用してキャリア基板にボンディングするステップと、
前記少なくとも1つのシード構造の半導体材料の前記単結晶によって示される熱膨張係数よりも大きな熱膨張係数を示す材料を含むように前記キャリア基板を選択するステップと、
前記少なくとも1つのシード構造が前記ガラスボンディング層上に支持されている間に、前記ガラスボンディング層のガラス材料のガラス転移温度よりも高い温度で前記少なくとも1つのシード構造の上方に半導体材料の少なくとも1つの層をエピタキシャル成長させるステップと、
前記少なくとも1つのシード構造上に半導体材料の前記少なくとも1つの層をエピタキシャル成長させるステップの後で、半導体材料の前記少なくとも1つの層、前記少なくとも1つのシード構造、前記ガラスボンディング層、及び前記キャリア基板を室温まで冷却するステップと、
前記ガラスボンディング層の前記ガラス材料の前記ガラス転移温度よりも低い温度から室温まで半導体材料の前記少なくとも1つの層、前記少なくとも1つのシード構造、前記ガラスボンディング層、及び前記キャリア基板を冷却するステップ中に、前記キャリア基板の熱収縮を使用して前記少なくとも1つのシード構造の半導体材料の前記単結晶を圧縮して歪ませるステップと、を含む方法。 - 前記ガラスボンディング層を使用して前記キャリア基板に前記少なくとも1つのシード構造をボンディングする前記ステップが、前記ガラスボンディング層を使用して前記キャリア基板に少なくとも実質的に連続するシード層をボンディングするステップを含む、請求項1に記載の方法。
- III−V型半導体材料を含むように前記少なくとも1つのシード構造の半導体材料の前記単結晶を選択するステップをさらに含む、請求項1に記載の方法。
- 前記少なくとも1つのシード構造上に半導体材料の前記少なくとも1つの層をエピタキシャル成長させるステップが、2ミクロン(2μm)以上の厚さに前記少なくとも1つのシード構造上にIII−V型半導体材料の層をエピタキシャル成長させるステップを含む、請求項1に記載の方法。
- ホウリンケイ酸塩ガラス(BPSG)を含むように前記ガラスボンディング層を選択するステップをさらに含む、請求項1に記載の方法。
- 半導体材料の前記少なくとも1つの層を含む発光ダイオード、レーザ、光学センサ、パワー電子素子、及び太陽電池のうちの少なくとも1つを製造するステップをさらに含む、請求項1に記載の方法。
- 半導体材料の単結晶によって少なくとも実質的に構成された少なくとも1つのシード構造を、ガラスボンディング層を使用して第1のキャリア基板にボンディングするステップと、
前記少なくとも1つのシード構造の半導体材料の前記単結晶によって示される熱膨張係数よりも大きな熱膨張係数を示す材料を含むように前記第1のキャリア基板を選択するステップと、
前記少なくとも1つのシード構造をパターニングして複数のシード構造を形成するステップと、
前記複数のシード構造、前記ガラスボンディング層、及び前記第1のキャリア基板を、前記ガラスボンディング層のガラス材料のガラス転移温度よりも高い温度まで加熱するステップと、
前記複数のシード構造、前記ガラスボンディング層、及び前記第1のキャリア基板を加熱するステップの後で、前記複数のシード構造、前記ガラスボンディング層、及び前記第1のキャリア基板を室温まで冷却するステップと、
前記ガラスボンディング層の前記ガラス材料の前記ガラス転移温度よりも低い温度から室温まで前記複数のシード構造、前記ガラスボンディング層、及び前記第1のキャリア基板を冷却するステップ中に、前記第1のキャリア基板の熱収縮を使用して前記複数のシード構造の各シード構造を圧縮して歪ませるステップであって、前記複数のシード構造の各シード構造が圧縮されて歪んだ窒化ガリウムを含む、ステップと、
非ガラス質ボンディング層が第2のキャリア基板と前記複数のシード構造との間に位置するように、当該非ガラス質ボンディング層を使用して前記第2のキャリア基板を前記複数のシード構造にボンディングするステップと、
前記第1のキャリア基板及び前記ガラスボンディング層を、前記複数のシード構造から分離又は除去するステップと、
前記複数のシード構造の表面上に半導体材料の少なくとも1つの層をエピタキシャル成長させるステップであって、前記半導体材料の前記少なくとも1つの層が2ミクロンよりも厚い厚さを有する、ステップと、
前記シード構造上で前記半導体材料の前記少なくとも1つの層をエピタキシャル成長させた後で、室温まで冷却するステップと、
を備える、半導体構造又は半導体素子を製造する方法。 - 前記第2のキャリア基板が、前記複数のシード構造の平均熱膨張係数及び半導体材料の前記少なくとも1つの層の平均熱膨張係数よりも大きな平均熱膨張係数を有する、請求項7に記載の方法。
- 前記非ガラス質ボンディング層が、SiO2、Si3N4、及びSiOxNyのうちの少なくとも1つを含む、請求項7に記載の方法。
- 前記複数のシード構造の各シード構造が、5ミクロン(5μm)と1ミリメートル(1mm)との間の横方向寸法X及びYを有する、請求項7に記載の方法。
- 前記複数のシード構造の各々が、1ミクロン(1μm)と100ミクロン(100μm)との間の距離だけ隣接するシード構造から間隔を空けて配置される、請求項7に記載の方法。
- 前記複数のシード構造の表面上にエピタキシャル成長した半導体材料の前記少なくとも1つの層が、6ミクロン(6μm)よりも厚い厚さを有する、請求項7に記載の方法。
- 前記複数のシード構造の表面上にエピタキシャル成長した半導体材料の前記少なくとも1つの層が、圧縮されて歪んだ窒化ガリウムを含む、請求項7に記載の方法。
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US26239109P | 2009-11-18 | 2009-11-18 | |
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US28668009P | 2009-12-15 | 2009-12-15 | |
US61/286,680 | 2009-12-15 | ||
PCT/IB2010/002542 WO2011061580A1 (en) | 2009-11-18 | 2010-09-24 | Methods of fabricating semiconductor structures and devices using glass bonding layers, and semiconductor structures and devices formed by such methods |
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US (3) | US8114754B2 (ja) |
EP (1) | EP2502266B1 (ja) |
JP (1) | JP6028280B2 (ja) |
KR (1) | KR101478977B1 (ja) |
CN (1) | CN102741999B (ja) |
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DE102009000514A1 (de) * | 2009-01-30 | 2010-08-26 | Robert Bosch Gmbh | Verbundbauteil sowie Verfahren zum Herstellen eines Verbundbauteil |
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KR101478977B1 (ko) | 2015-01-06 |
US8114754B2 (en) | 2012-02-14 |
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SG2014014146A (en) | 2014-07-30 |
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CN102741999B (zh) | 2015-07-15 |
WO2011061580A1 (en) | 2011-05-26 |
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US20120112205A1 (en) | 2012-05-10 |
CN102741999A (zh) | 2012-10-17 |
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