JP2011044655A - 半導体装置及び半導体装置の製造方法 - Google Patents

半導体装置及び半導体装置の製造方法 Download PDF

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JP2011044655A
JP2011044655A JP2009193324A JP2009193324A JP2011044655A JP 2011044655 A JP2011044655 A JP 2011044655A JP 2009193324 A JP2009193324 A JP 2009193324A JP 2009193324 A JP2009193324 A JP 2009193324A JP 2011044655 A JP2011044655 A JP 2011044655A
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Prior art keywords
pad
semiconductor substrate
insulating film
wiring conductor
metal
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JP2009193324A
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JP5304536B2 (ja
Inventor
Atsushi Okuyama
奥山　　敦
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Sony Corp
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Sony Corp
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Priority to JP2009193324A priority Critical patent/JP5304536B2/ja
Application filed by Sony Corp filed Critical Sony Corp
Priority to TW099123321A priority patent/TWI483358B/zh
Priority to KR1020100078691A priority patent/KR101644655B1/ko
Priority to US12/858,052 priority patent/US8368222B2/en
Priority to CN201410686327.9A priority patent/CN104465582A/zh
Priority to CN2010102566190A priority patent/CN101996956A/zh
Priority to CN201110221660.9A priority patent/CN102324404B/zh
Publication of JP2011044655A publication Critical patent/JP2011044655A/ja
Priority to US13/758,775 priority patent/US8742585B2/en
Application granted granted Critical
Publication of JP5304536B2 publication Critical patent/JP5304536B2/ja
Priority to US14/270,104 priority patent/US9269680B2/en
Priority to US14/992,865 priority patent/US9679937B2/en
Priority to KR1020160088496A priority patent/KR20160087378A/ko
Priority to US15/619,156 priority patent/US9941323B2/en
Priority to US15/921,441 priority patent/US10541265B2/en
Priority to US16/714,137 priority patent/US11121164B2/en
Priority to US17/398,532 priority patent/US11715752B2/en
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Abstract

【課題】半導体基板の貼り合わせにおける位置ずれによる電気特性の低下を抑制できる半導体装置を提供する。
【解決手段】チップ５は、互いに貼り合わされる２枚の半導体基板７を有する。また、チップ５は、第１配線導体１９Ａに接続され、第１絶縁膜１５Ａから第２半導体基板７Ｂ側へ露出する第１パッド１７Ａを有する。また、チップ５は、第２配線導体１９Ｂに接続され、第２絶縁膜１５Ｂから第１半導体基板７Ａ側へ露出し、第１パッド１７Ａに貼り合わされる第２パッド１７Ｂを有する。第２パッド１７Ｂは、第２配線導体１９Ｂよりも第１絶縁膜１５Ａに対する拡散性が低い金属により形成されている。
【選択図】図２

Description

本発明は、半導体装置及び半導体装置の製造方法に関する。
半導体チップの集積化等のために、２枚の半導体基板を貼り合わせる技術が知られている（例えば特許文献１）。特許文献１では、半導体基板同士の電気的接続は、２枚の半導体基板の間に挟まれるバンプを介して行われている。
特開２００６−６６８０８号公報
半導体基板同士を電気的に接続する技術として、上記の技術以外にも種々の技術が提案され、技術の豊富化が図られることが望ましい。しかし、新たな電気的な接続の構成を実現するに際しては、従来の構成にはない考慮すべき事項も浮上する。
本願は、半導体基板同士を電気的に接続する新たな技術の提案を行う。具体的には、２枚の半導体基板に設けられたパッド同士を直接的に当接させることにより、これらのパッドを接続する技術を提案する。
この技術においては、従来の構成にはない考慮すべき事項として、半導体基板の貼り合わせにおける位置ずれによる電気特性の低下が挙げられる。具体的には、半導体基板の貼り合わせにおいて位置ずれが生じると、一方の半導体基板のパッドが他方の半導体基板の層間絶縁膜へ当接する。この場合、パッドを構成する金属（のイオン）が絶縁膜に拡散し、電気特性が低下する。
本発明の目的は、半導体基板の貼り合わせにおける位置ずれによる電気特性の低下を抑制できる半導体装置及び半導体装置の製造方法を提供することにある。
本発明の半導体装置は、第１半導体基板と、前記第１半導体基板に対して対向する第２半導体基板と、前記第１半導体基板の前記第２半導体基板側に設けられた第１配線導体と、前記第２半導体基板の前記第１半導体基板側に設けられた第２配線導体と、前記第１配線導体を覆う第１絶縁膜と、前記第２配線導体を覆い、前記第１絶縁膜と貼り合わされた第２絶縁膜と、前記第１配線導体に接続され、前記第１絶縁膜から前記第２半導体基板側へ露出する第１パッドと、前記第２配線導体に接続され、前記第２絶縁膜から前記第１半導体基板側へ露出し、前記第１パッドに貼り合わされ、少なくとも表面が前記第２配線導体よりも前記第１絶縁膜に対する拡散性が低い金属により形成された第２パッドと、を有する。
好適には、前記第２パッドは、前記第１パッドよりも広い。
好適には、前記第１パッドは、少なくとも表面が前記第１配線導体よりも前記第２絶縁膜に対する拡散性が低い金属により形成されている。
好適には、前記第１半導体基板及び前記第２半導体基板の一方に設けられたロジックデバイスと、前記第１半導体基板及び前記第２半導体基板の他方に設けられたメモリと、を有する。
好適には、前記拡散性が低い金属は、Ａｕ、Ａｇ、Ｔａ、Ｔｉ、又は、これらの少なくともいずれか１つを含む合金である。
好適には、前記第２絶縁膜は、シリコンと、窒素、酸素及び炭素の少なくともいずれか１つとを含む材料により形成されている。
本発明の半導体装置の製造方法は、第１配線導体及び前記第１配線導体を覆う第１絶縁膜が形成された第１半導体基板において、前記第１配線導体に接続され、前記第１絶縁膜から露出する第１パッドを形成する工程と、第２配線導体及び前記第２配線導体を覆う第２絶縁膜が形成された第２半導体基板において、前記第２配線導体に接続され、前記第２絶縁膜から露出する第２パッドを形成する工程と、前記第１パッド及び前記第２パッドを互いに当接させた状態で、前記第１半導体基板と前記第２半導体基板とを互いに貼り合わせる工程と、を有し、前記第２パッドの少なくとも表面は、前記第２配線導体よりも前記第１絶縁膜に対する拡散性が低い金属により形成される。
好適には、前記貼り合わせる工程では、所定の位置合わせ精度の貼り合わせ装置により前記第１半導体基板と前記第２半導体基板とを貼り合わせ、前記第２パッドは、前記位置合わせ精度以上の差で、前記第１パッドよりも広く形成される。
好適には、前記第１半導体基板及び前記第２半導体基板はウェハである。
本発明によれば、半導体基板の貼り合わせにおける位置ずれによる電気特性の低下を抑制できる。
本発明の実施形態に係る積層ウェハを模式的に示す斜視図及び断面図。 図１の領域ＩＩａにおける断面図及び平面図。 図１の積層ウェハから形成されるチップの製造方法を説明する概念図。 第１の変形例を示す図２（ａ）に相当する断面図。 第２の変形例を示す図２（ａ）に相当する断面図。 第３の変形例を示す図２（ａ）に相当する断面図。 第４の変形例を示す図２（ｂ）及び図２（ｃ）に相当する平面図。 チップレベルでの貼り合わせの例を模式的に示す斜視図。
図１（ａ）は、本発明の実施形態に係る積層ウェハ１を模式的に示す斜視図である。
積層ウェハ１は、第１ウェハ３Ａ及び第２ウェハ３Ｂ（以下、単に「ウェハ３」といい、両者を区別しないことがある。）が貼り合わされて構成されている。積層ウェハ１がダイシングされることにより、複数のチップ（半導体装置）５が形成される。
図１（ｂ）は、図１（ａ）のＩｂ−Ｉｂ線における模式的な断面図である。
第１ウェハ３Ａは、第１半導体基板７Ａと、第１半導体基板７Ａ上に多層に積層された配線層９及び層間絶縁膜１１とを有している。なお、図１（ｂ）において、複数の層間絶縁膜１１の境界線の図示は省略されている。同様に、第２ウェハ３Ｂは、第２半導体基板７Ｂと、第２半導体基板７Ｂ上に多層に積層された配線層９及び層間絶縁膜１１とを有している。各ウェハ３において、多層の配線層９は、層間絶縁膜１１を貫通するビア１３により接続されている。
なお、以下では、第１半導体基板７Ａ及び第２半導体基板７Ｂを単に「半導体基板７」といい、両者を区別しないことがある。
半導体基板７は、加工前のウェハ（狭義のウェハ）であり、例えば、シリコンにより形成されている。配線層９及びビア１３は、例えば、Ｃｕにより形成されている。層間絶縁膜１１は、例えば、シリコンと、窒素、酸素及び炭素の少なくともいずれか１つとを含む材料により形成されている。例えば、層間絶縁膜１１は、シリコン酸化膜である。
各ウェハ３において、配線層９及びビア１３は、バリアメタル２１（図２（ａ）参照）によって層間絶縁膜１１への拡散が抑制されている。バリアメタル２１は、例えば、ＴｉＮ、ＴａＮにより形成されている。
なお、以下において、半導体基板７及び層間絶縁膜１１等について、ダイシング前とダイシング後とで、異なる名称及び符号を付すと、説明が煩雑となることから、ダイシング前とダイシング後とで共通の語及び符号を用いるものとする。
各ウェハ３においては、例えば、半導体基板７上に形成された不図示の半導体素子、配線層９及びビア１３により、単機能のＬＳＩが構成される。例えば、２つのウェハ３の一方（３Ａ）においては、メモリ３１が構成され、２つのウェハ３の他方（３Ｂ）においては、ロジックデバイス３３が構成される。メモリ３１は、例えば、ＤＲＡＭ、ＳＲＡＭ、フラッシュメモリである。ロジックデバイス３３は、例えば、ＭＰＵや周辺回路である。このような単機能のウェハ３同士の貼り合わせにより、高機能且つ集積度の高いＬＳＩのチップ化が可能となる。
図２（ａ）は、図１（ｂ）の領域ＩＩａの拡大図である。図２（ｂ）は、図２（ａ）の範囲における第１ウェハ３Ａの第２ウェハ３Ｂ側から見た平面図である。図２（ｃ）は、図２（ａ）の範囲における第２ウェハ３Ｂの第１ウェハ３Ａ側から見た平面図である。
２つのウェハ３は、最上層の層間絶縁膜１１同士が互いに貼り合わされる。なお、以下では、第１ウェハ３Ａの最上層の層間絶縁膜１１を「第１絶縁膜１５Ａ」といい、第２ウェハ３Ｂの最上層の層間絶縁膜１１を「第２絶縁膜１５Ｂ」という。また、第１絶縁膜１５Ａ及び第２絶縁膜１５Ｂを単に「絶縁膜１５」といい、両者を区別しないことがある。
また、２つのウェハ３は、第１ウェハ３Ａに設けられた第１パッド１７Ａと、第２ウェハ３Ｂに設けられた第２パッド１７Ｂとが当接することにより、電気的に接続されている。なお、以下では、第１パッド１７Ａ及び第２パッド１７Ｂを単に「パッド１７」といい、両者を区別しないことがある。
第１パッド１７Ａは、第１絶縁膜１５Ａに形成された凹部（溝）に充填された金属により形成されている。第１パッド１７Ａは、第１絶縁膜１５Ａから第２絶縁膜１５Ｂ側へ露出している。第１パッド１７Ａの平面形状は、例えば、矩形である。
第１パッド１７Ａは、例えば、第１パッド１７Ａの直下に設けられたビア１３と接続されている。これにより、第１パッド１７Ａは、配線層９及びビア１３により形成され、第１絶縁膜１５Ａ（及び他の層間絶縁膜１１）に被覆された配線（以下、「第１配線導体１９Ａ」という。符号は図１（ｂ）参照）と接続されている。
第２パッド１７Ｂは、第１パッド１７Ａと同様に、第２絶縁膜１５Ｂに形成された凹部（溝）に充填された金属により形成されている。第２パッド１７Ｂは、第２絶縁膜１５Ｂから第１絶縁膜１５Ａ側へ露出している。第２パッド１７Ｂの平面形状は、例えば、矩形である。
第２パッド１７Ｂは、例えば、層間絶縁膜１１に対する拡散性がＣｕよりも低い金属により形成されている。例えば、第２パッド１７Ｂは、Ａｕ、Ａｇ、Ｔａ、Ｔｉ、又は、これらの少なくともいずれか１つを含む合金により形成されている。
第２パッド１７Ｂは、例えば、第２パッド１７Ｂと同材料で形成された接続部１８に接続されている。接続部１８は、ビア１３を介して、配線層９及びビア１３により形成され、第２絶縁膜１５Ｂに被覆された配線（以下、「第２配線導体１９Ｂ」という。符号は図１（ｂ）参照）と接続されている。
なお、第１配線導体１９Ａ及び第２配線導体１９Ｂを単に「配線導体１９」といい、両者を区別しないことがある。
第２パッド１７Ｂは、第１パッド１７Ａよりも広く形成されている。具体的には、２つのウェハ３を貼り合わせたときに、位置ずれが生じても、第１パッド１７Ａが第２パッド１７Ｂ内に収まるように、２つのパッド１７は形成されている。
貼り合わせの位置ずれ量は、例えば、±３μｍ程度である。従って、第２パッド１７Ｂの１辺は、第２パッド１７Ｂの一辺よりも６μｍ以上の差で広くなるように設定されている。
このように２つのパッド１７が形成されることにより、貼り合わせにおいて位置ずれが生じても、絶縁膜１５に対する拡散性が低い第２パッド１７Ｂのみが絶縁膜１５に当接することになる。
なお、第１パッド１７Ａは、第２パッド１７Ｂと同様に、接続部を介して第１配線導体１９Ａと接続されてもよい。この場合、第２パッド１７Ｂの接続部１８は、第１パッド１７Ａの接続部よりも、位置ずれ量以上の差で広くなるように形成されていることが好ましい。
また、第２パッド１７Ｂは、第１パッド１７Ａと同様に、第２パッド１７Ｂの直下にビア１３が設けられることにより、第２配線導体１９Ｂと接続されていてもよい。
図３は、チップ５の製造方法を説明する概念図である。
配線工程では、フォトリソグラフィー等が繰り返されることにより、層間絶縁膜１１及び配線層９が多層に積層され、配線導体１９及びパッド１７が形成される。配線工程では、成膜装置５１、露光装置５３、エッチング装置５５、平坦化装置５７などが使用される。
配線工程において、パッド１７は、例えば、ダマシンプロセスによって行われる。なお、ダマシンプロセスは、シングルダマシンプロセスでもよいし、デュアルダマシンプロセスでもよい。図２（ａ）では、デュアルダマシンプロセスにより形成された第１パッド１７Ａを示している。
その後、各ウェハ３に対して、貼り合わせ前処理工程が行われる。当該処理においては、例えば、ウェハ３の表面活性化、及び、パッド１７における酸化膜の除去が行われる。当該処理は、例えば、還元処理又はアニールである。還元処理は、例えば、水素プラズマ、ＮＨ３プラズマ、又は、蟻酸プラズマを用いて行われる。アニールは、例えば、水素又はフォーミングガス（Ｎ２及びＨ２）を用いて行われる。
なお、図３では、容量式のプラズマ還元処理装置５９を模式的に例示している。プラズマ還元処理の条件の一例を示すと、ガス：Ｈ２／Ａｒ＝１００／１７０ｓｃｃｍ、マイクロ波：２．８ｋＷ（２．４５ＧＨｚ）、圧力：０．４Ｐａ、基板温度：４００℃、時間：１ｍｉｎである。
前処理が行われたウェハ３は、貼り合わせ工程において、貼り合わせ装置６１により、貼り合わされる。貼り合わせ装置６１としては、半導体基板にインターポーザを貼り合わせる装置などの公知の貼り合わせ装置を適宜に用いることができる。
貼り合わせ装置６１は、例えば、２つのウェハ３を位置合わせして重ね合わせる機能と、重ね合わされたウェハ３を加熱及び加圧して接合する機能とを有している。
位置合わせは、例えば、ノッチやオリフラを所定の係合部材へ係合させる方法、Ｖ字型の枠体等の位置決め部材にウェハ３を嵌合させる方法、ノッチ、オリフラ及び／又はエッジ全体の検出に基づいてウェハ３を適宜に相対移動させる方法などにより行われてよい。
図３では、ウェハ３のノッチ等を検出する検出部６３の検出結果に基づいて、第２ウェハ３Ｂを保持する第２テーブル６５Ｂを駆動部６７により平行移動及び回転移動させて位置合わせする装置を例示している。
位置合わせする装置と、加熱及び加圧する装置とは一体的に構成されても、別個に構成されてもよい。図３では、位置合わせに利用される第１テーブル６５Ａ及び第２テーブル６５Ｂにヒータ６９が内蔵されており、当該第１テーブル６５Ａ及び第２テーブル６５Ｂにより、加圧及び加熱が行われる装置を例示している。
貼り合わせ装置（若しくは、貼り合わせ装置に含まれる位置合わせ装置）の位置合わせ精度は、位置合わせの原理、使用される部材の製造誤差、及び、使用される機器の動作の精度等によって規定される。上述した配線工程においては、第２パッド１７Ｂは、貼り合わせ装置６１の位置合わせの精度以上の差で、第１パッド１７Ａよりも広くなるように形成される。
なお、このような位置合わせの精度として、例えば、貼り合わせ装置の製造者において、実験等において測定されて公表された値、又は、貼り合わせ装置のユーザにおいて、実験等において測定された値が用いられてよい。
２つのウェハ３が貼り合わされて構成された積層ウェハ１は、ダイシング工程においてダイシングブレード７１によりダイシングされる。これにより、複数のチップ５が形成される。
以上の実施形態によれば、チップ５は、第１半導体基板７Ａと、第１半導体基板７Ａに対して対向する第２半導体基板７Ｂとを有する。また、チップ５は、第１半導体基板７Ａの第２半導体基板７Ｂ側に設けられた第１配線導体１９Ａと、第２半導体基板７Ｂの第１半導体基板７Ａ側に設けられた第２配線導体１９Ｂとを有する。また、チップ５は、第１配線導体１９Ａを覆う第１絶縁膜１５Ａと、第２配線導体１９Ｂを覆い、第１絶縁膜１５Ａと貼り合わされた第２絶縁膜１５Ｂとを有する。また、チップ５は、第１配線導体１９Ａに接続され、第１絶縁膜１５Ａから第２半導体基板７Ｂ側へ露出する第１パッド１７Ａを有する。また、チップ５は、第２配線導体１９Ｂに接続され、第２絶縁膜１５Ｂから第１半導体基板７Ａ側へ露出し、第１パッド１７Ａに貼り合わされる第２パッド１７Ｂを有する。第２パッド１７Ｂは、第２配線導体１９Ｂよりも第１絶縁膜１５Ａに対する拡散性が低い金属により形成されている。
また、チップ５の製造方法は、第１配線導体１９Ａ及び第１配線導体１９Ａを覆う第１絶縁膜１５Ａが形成された第１半導体基板７Ａにおいて、第１配線導体１９Ａに接続され、第１絶縁膜１５Ａから露出する第１パッド１７Ａを形成する工程を含む。また、当該製造方法は、第２配線導体１９Ｂ及び第２配線導体１９Ｂを覆う第２絶縁膜１５Ｂが形成された第２半導体基板７Ｂにおいて、第２配線導体１９Ｂに接続され、第２絶縁膜１５Ｂから露出する第２パッド１７Ｂを形成する工程を含む。また、当該製造方法は、第１パッド１７Ａ及び第２パッド１７Ｂを互いに当接させた状態で、第１半導体基板７Ａと第２半導体基板７Ｂとを互いに貼り合わせる工程を含む。そして、第２パッド１７Ｂは、第２配線導体１９Ｂよりも第１絶縁膜１５Ａに対する拡散性が低い金属により形成される。
従って、貼り合わせにおける位置ずれにより、第２パッド１７Ｂが第１絶縁膜１５Ａに当接したとしても、第２配線導体１９Ｂを構成する金属により第２パッド１７Ｂを形成する場合に比較して、金属の第１絶縁膜１５Ａへの拡散が抑制される。また、一般に、絶縁膜への拡散が抑制される金属は高価であるが、そのような金属を配線全体には用いずに、第２パッド１７Ｂ等の一部のみに用いることにより、コスト削減が期待される。さらに、第２パッド１７Ｂの酸化抑制も期待される。
第２パッド１７Ｂは、第１パッド１７Ａよりも広い。従って、位置ずれが生じても、第１パッド１７Ａが第２絶縁膜１５Ｂに当接することが抑制される。その結果、第１パッド１７Ａ及び第２パッド１７Ｂのうち、一方のみにおいて、絶縁膜１５に拡散しにくい金属を用いることにより、位置ずれに起因する金属の絶縁膜１５への拡散が抑制される。その結果、例えば、第１パッド１７Ａは、第２絶縁膜１５Ｂに対する拡散性が第１配線導体１９Ａの第２絶縁膜１５Ｂに対する拡散性と同等の金属（例えば、第１配線導体１９Ａと同一の金属）で形成することができる。また、第１パッド１７Ａは、第２絶縁膜１５Ｂに対する拡散性が第２パッド１７Ｂの第１絶縁膜１５Ａに対する拡散性よりも高い金属により形成することができる。
拡散性が低い金属は、Ａｕ、Ａｇ、Ｔａ、Ｔｉ、又は、これらの少なくともいずれか１つを含む合金である。これらの合金は、配線導体１９を構成するＣｕに比較して拡散性が低いだけでなく、他の拡散性が低い金属（例えば、Ａｌ、Ｗ）に比較して、接合性がよい。
ウェハ３（チップ５）を貼り合わせる工程では、所定の位置合わせ精度の貼り合わせ装置６１により第１半導体基板７Ａと第２半導体基板７Ｂとを貼り合わせる。また、第２パッド１７Ｂは、その位置合わせ精度以上の差で、第１パッド１７Ａよりも広く形成される。従って、位置ずれによる金属の拡散が、より確実に抑制される。
（第１の変形例）
図４は、本発明の第１の変形例を示す、図２（ａ）に相当する断面図である。
実施形態では、第２パッド１７Ｂの全体が、拡散性が低い金属により形成された。一方、第１の変形例の第２パッド１１７Ｂは、表面のみが、拡散性が低い金属により形成されている。
すなわち、当該パッドの体積の大部分を占める基部１２３は、第２配線導体１９Ｂと同一材料（例えばＣｕ）で形成され、基部１２３の第１パッド１７Ａ側の表面に積層された被覆層１２５は、拡散性が低い金属（Ａｕ等）により形成されている。
このような構成とすることにより、例えば、一般に高価な拡散性が低い金属の使用量が低減され、コストが削減されることが期待される。
（第２の変形例）
図５は、本発明の第２の変形例を示す、図２（ａ）に相当する断面図である。
実施形態では、第１パッド１７Ａ及び第２パッド１７Ｂのうち、一方（１７Ｂ）のみが拡散性が低い金属により形成された。一方、第２の変形例では、第１パッド２１７Ａ及び第２パッド２１７Ｂの双方が、拡散性が低い金属により形成されている。
この場合、２つのパッド２１７のいずれが絶縁膜１５に当接しても、金属の絶縁膜１５への拡散は抑制される。換言すれば、位置ずれ量に応じて２つのパッド２１７の一方を他方に対して広くすることをしなくても、双方のパッド２１７の金属の拡散は抑制される。従って、寸法に関する設計の自由度が高い。なお、図５では、第１パッド２１７Ａ及び第２パッド２１７Ｂが同一の広さに形成された場合を例示している。
（第３の変形例）
図６は、本発明の第３の変形例を示す、図２（ａ）に相当する断面図である。
この変形例では、第２絶縁膜１５Ｂ上に、第１パッド１７Ａの金属が第２絶縁膜１５Ｂに拡散することを抑制する拡散防止層３２５が設けられている。拡散防止層３２５は、例えば、ＳｉＮやＳｉＯＣにより形成されている。なお、第２パッド３１７Ｂは、拡散防止層３２５から第１絶縁膜１５Ａ側に露出している。
この場合、第１パッド１７Ａの金属の拡散は、拡散防止層３２５によって抑制される。従って、第２の変形例と同様に、第２パッド３１７Ｂを広くしなくても、第１パッド１７Ａの金属の拡散は抑制される。換言すれば、寸法の設計の自由度が高い。なお、図６では、第１パッド１７Ａ及び第２パッド３１７Ｂが同一の広さに形成された場合を例示している。
（第４の変形例）
図７（ａ）及び図７（ｂ）は、本発明の第４の変形例を示す、図２（ｂ）及び図２（ｃ）に対応する平面図である。
この変形例では、第１パッド４１７Ａは、円形に形成されている。この場合、第１パッド４１７Ａに直交する軸回りの位置ずれによる、第１パッド４１７Ａの第２パッド１７Ｂからのはみ出しが抑制される。その結果、金属の拡散をより確実に抑制できる。
本発明は、以上の実施形態に限定されず、種々の態様で実施されてよい。
実施形態では、ウェハ同士の貼り合わせを例示した。しかし、本発明は、図８（ａ）に示すように、ウェハ（３Ｂ）とチップ（５０３Ａ）との貼り合わせ、及び、チップ（５０３Ａ、５０３Ｂ）同士の貼り合わせに適用されてもよい。
なお、ウェハとチップとの貼り合わせ等は、ウェハ同士の貼り合わせに比較して、位置ずれ量が大きくなることが予想される。例えば、ウェハ同士の貼り合わせの位置合わせ精度が±３μｍ程度であるのに対して、ウェハとチップとの貼り合わせの位置精度は、±１０μｍ以上である。パッドの広さを設計する際には、このような差異にも留意することが好ましい。
ウェハ（チップ）は、２層に貼り合わされるものに限定されず、３層以上貼り合わされるものであってもよい。一のウェハ（チップ）に構成される回路は、メモリやロジックデバイスに限定されない。例えば、撮像素子であってもよい。
本願において開示された実施形態及び変形例等は、適宜に組み合わされてよい。例えば、図４において示したパッドの表面のみに拡散性が低い金属を用いる技術と、図５において示した２つのパッドの双方に拡散性が低い金属を用いる技術とを組み合わせてもよい。すなわち、２つのパッドの双方の表面のみに拡散性が低い金属を用いてもよい。
５…チップ（半導体装置）、７Ａ…第１半導体基板、７Ｂ…第２半導体基板、１５Ａ…第１絶縁膜、１５Ｂ…第２絶縁膜、１７Ａ…第１パッド、１７Ｂ…第２パッド、１９Ａ…第１配線導体、１９Ｂ…第２配線導体。

Claims (9)

  1. 第１半導体基板と、
    前記第１半導体基板に対して対向する第２半導体基板と、
    前記第１半導体基板の前記第２半導体基板側に設けられた第１配線導体と、
    前記第２半導体基板の前記第１半導体基板側に設けられた第２配線導体と、
    前記第１配線導体を覆う第１絶縁膜と、
    前記第２配線導体を覆い、前記第１絶縁膜と貼り合わされた第２絶縁膜と、
    前記第１配線導体に接続され、前記第１絶縁膜から前記第２半導体基板側へ露出する第１パッドと、
    前記第２配線導体に接続され、前記第２絶縁膜から前記第１半導体基板側へ露出し、前記第１パッドに貼り合わされ、少なくとも表面が前記第２配線導体よりも前記第１絶縁膜に対する拡散性が低い金属により形成された第２パッドと、
    を有する半導体装置。
  2. 前記第２パッドは、前記第１パッドよりも広い
    請求項１に記載の半導体装置。
  3. 前記第１パッドは、少なくとも表面が前記第１配線導体よりも前記第２絶縁膜に対する拡散性が低い金属により形成されている
    請求項１に記載の半導体装置。
  4. 前記第１半導体基板及び前記第２半導体基板の一方に設けられたロジックデバイスと、
    前記第１半導体基板及び前記第２半導体基板の他方に設けられたメモリと、
    を有する請求項１に記載の半導体装置。
  5. 前記拡散性が低い金属は、Ａｕ、Ａｇ、Ｔａ、Ｔｉ、又は、これらの少なくともいずれか１つを含む合金である
    請求項１に記載の半導体装置。
  6. 前記第２絶縁膜は、シリコンと、窒素、酸素及び炭素の少なくともいずれか１つとを含む材料により形成されている
    請求項１に記載の半導体装置。
  7. 第１配線導体及び前記第１配線導体を覆う第１絶縁膜が形成された第１半導体基板において、前記第１配線導体に接続され、前記第１絶縁膜から露出する第１パッドを形成する工程と、
    第２配線導体及び前記第２配線導体を覆う第２絶縁膜が形成された第２半導体基板において、前記第２配線導体に接続され、前記第２絶縁膜から露出する第２パッドを形成する工程と、
    前記第１パッド及び前記第２パッドを互いに当接させた状態で、前記第１半導体基板と前記第２半導体基板とを互いに貼り合わせる工程と、
    を有し、
    前記第２パッドの少なくとも表面は、前記第２配線導体よりも前記第１絶縁膜に対する拡散性が低い金属により形成される
    半導体装置の製造方法。
  8. 前記貼り合わせる工程では、所定の位置合わせ精度の貼り合わせ装置により前記第１半導体基板と前記第２半導体基板とを貼り合わせ、
    前記第２パッドは、前記位置合わせ精度以上の差で、前記第１パッドよりも広く形成される
    請求項７に記載の半導体装置の製造方法。
  9. 前記第１半導体基板及び前記第２半導体基板はウェハである
    請求項７に記載の半導体装置の製造方法。
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US12/858,052 US8368222B2 (en) 2009-08-24 2010-08-17 Semiconductor device with pad with less diffusible contacting surface and method for production of the semiconductor device
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US13/758,775 US8742585B2 (en) 2009-08-24 2013-02-04 Semiconductor device having a plurality of pads of low diffusible material formed in a substrate
US14/270,104 US9269680B2 (en) 2009-08-24 2014-05-05 Semiconductor device with a connection pad in a substrate and method for production thereof
US14/992,865 US9679937B2 (en) 2009-08-24 2016-01-11 Semiconductor device and method for production of semiconductor device
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US15/619,156 US9941323B2 (en) 2009-08-24 2017-06-09 Semiconductor device and method for production of semiconductor device
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