DE69535936D1 - Verfahren zum Herstellen einer Halbleitervorrichtung mit Graben - Google Patents

Verfahren zum Herstellen einer Halbleitervorrichtung mit Graben

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Publication number
DE69535936D1
DE69535936D1 DE69535936T DE69535936T DE69535936D1 DE 69535936 D1 DE69535936 D1 DE 69535936D1 DE 69535936 T DE69535936 T DE 69535936T DE 69535936 T DE69535936 T DE 69535936T DE 69535936 D1 DE69535936 D1 DE 69535936D1
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DE
Germany
Prior art keywords
manufacturing
semiconductor device
trench semiconductor
trench
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69535936T
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English (en)
Inventor
Katsumi Nakamura
Tadaharu Minato
Shuuichi Tominaga
Katsuomi Shiozawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Application granted granted Critical
Publication of DE69535936D1 publication Critical patent/DE69535936D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • HELECTRICITY
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
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    • H01L21/76232Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thyristors (AREA)
  • Thin Film Transistor (AREA)
  • Formation Of Insulating Films (AREA)
  • Electrodes Of Semiconductors (AREA)
DE69535936T 1994-02-04 1995-02-06 Verfahren zum Herstellen einer Halbleitervorrichtung mit Graben Expired - Lifetime DE69535936D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1255994 1994-02-04
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EP1160852A3 (de) 2007-05-30
US5783491A (en) 1998-07-21
DE69534955D1 (de) 2006-06-01
JPH07263692A (ja) 1995-10-13
JP3396553B2 (ja) 2003-04-14
EP1160872A3 (de) 2007-06-20
US6117734A (en) 2000-09-12
EP0666590A2 (de) 1995-08-09
US6710401B2 (en) 2004-03-23
EP0666590B1 (de) 2006-04-26
EP1160852A2 (de) 2001-12-05
US20030203573A1 (en) 2003-10-30
DE69534955T8 (de) 2007-09-13
DE69534955T2 (de) 2007-04-12
EP1160852B1 (de) 2009-04-15
US20010006836A1 (en) 2001-07-05
EP0666590A3 (de) 1996-05-08
US7067874B2 (en) 2006-06-27
DE69536116D1 (de) 2010-12-02
EP1160872B1 (de) 2010-10-20
KR100188823B1 (ko) 1999-06-01
EP1160872A2 (de) 2001-12-05

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