DE69229887D1 - Verfahren zum Herstellen einer Halbleiteranordnung mit Schaltkreis-Blockeinheiten - Google Patents

Verfahren zum Herstellen einer Halbleiteranordnung mit Schaltkreis-Blockeinheiten

Info

Publication number
DE69229887D1
DE69229887D1 DE69229887T DE69229887T DE69229887D1 DE 69229887 D1 DE69229887 D1 DE 69229887D1 DE 69229887 T DE69229887 T DE 69229887T DE 69229887 T DE69229887 T DE 69229887T DE 69229887 D1 DE69229887 D1 DE 69229887D1
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
circuit block
block units
units
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69229887T
Other languages
English (en)
Other versions
DE69229887T2 (de
Inventor
Taiji Ema
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69229887D1 publication Critical patent/DE69229887D1/de
Publication of DE69229887T2 publication Critical patent/DE69229887T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0073—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces
    • H05K3/0079—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces characterised by the method of application or removal of the mask

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • General Engineering & Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE69229887T 1991-03-18 1992-03-16 Verfahren zum Herstellen einer Halbleiteranordnung mit Schaltkreis-Blockeinheiten Expired - Fee Related DE69229887T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3051817A JP3027990B2 (ja) 1991-03-18 1991-03-18 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE69229887D1 true DE69229887D1 (de) 1999-10-07
DE69229887T2 DE69229887T2 (de) 2000-05-31

Family

ID=12897453

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69229887T Expired - Fee Related DE69229887T2 (de) 1991-03-18 1992-03-16 Verfahren zum Herstellen einer Halbleiteranordnung mit Schaltkreis-Blockeinheiten

Country Status (5)

Country Link
US (2) US5539224A (de)
EP (1) EP0505248B1 (de)
JP (1) JP3027990B2 (de)
KR (1) KR960009101B1 (de)
DE (1) DE69229887T2 (de)

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DE69324637T2 (de) * 1992-07-31 1999-12-30 Hughes Electronics Corp., El Segundo Sicherheitssystem für integrierte Schaltung und Verfahren mit implantierten Leitungen
US6675361B1 (en) 1993-12-27 2004-01-06 Hyundai Electronics America Method of constructing an integrated circuit comprising an embedded macro
US5671397A (en) 1993-12-27 1997-09-23 At&T Global Information Solutions Company Sea-of-cells array of transistors
US5783846A (en) * 1995-09-22 1998-07-21 Hughes Electronics Corporation Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering
US5859690A (en) * 1996-03-28 1999-01-12 Nikon Corporation Method of dividing and exposing patterns
US5973375A (en) * 1997-06-06 1999-10-26 Hughes Electronics Corporation Camouflaged circuit structure with step implants
US6192290B1 (en) * 1998-05-21 2001-02-20 Lucent Technologies Inc. System and method of manufacturing semicustom integrated circuits using reticle primitives from a library and interconnect reticles
JP2000068488A (ja) * 1998-08-20 2000-03-03 Oki Electric Ind Co Ltd 半導体集積回路のレイアウト方法
US6346427B1 (en) 1999-08-18 2002-02-12 Utmc Microelectronic Systems Inc. Parameter adjustment in a MOS integrated circuit
US6396368B1 (en) 1999-11-10 2002-05-28 Hrl Laboratories, Llc CMOS-compatible MEM switches and method of making
US7217977B2 (en) 2004-04-19 2007-05-15 Hrl Laboratories, Llc Covert transformation of transistor properties as a circuit protection method
US6567967B2 (en) 2000-09-06 2003-05-20 Monterey Design Systems, Inc. Method for designing large standard-cell base integrated circuits
US6815816B1 (en) 2000-10-25 2004-11-09 Hrl Laboratories, Llc Implanted hidden interconnections in a semiconductor device for preventing reverse engineering
US6791191B2 (en) 2001-01-24 2004-09-14 Hrl Laboratories, Llc Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations
US7294935B2 (en) * 2001-01-24 2007-11-13 Hrl Laboratories, Llc Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide
US6774413B2 (en) 2001-06-15 2004-08-10 Hrl Laboratories, Llc Integrated circuit structure with programmable connector/isolator
US6740942B2 (en) * 2001-06-15 2004-05-25 Hrl Laboratories, Llc. Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact
US6897535B2 (en) 2002-05-14 2005-05-24 Hrl Laboratories, Llc Integrated circuit with reverse engineering protection
US7049667B2 (en) * 2002-09-27 2006-05-23 Hrl Laboratories, Llc Conductive channel pseudo block process and circuit to inhibit reverse engineering
US6979606B2 (en) * 2002-11-22 2005-12-27 Hrl Laboratories, Llc Use of silicon block process step to camouflage a false transistor
AU2003293540A1 (en) 2002-12-13 2004-07-09 Raytheon Company Integrated circuit modification using well implants
US7242063B1 (en) 2004-06-29 2007-07-10 Hrl Laboratories, Llc Symmetric non-intrusive and covert technique to render a transistor permanently non-operable
US8168487B2 (en) 2006-09-28 2012-05-01 Hrl Laboratories, Llc Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer
US8728713B2 (en) 2010-09-30 2014-05-20 Truesense Imaging, Inc. Stitching methods using multiple microlithographic expose tools
US8415813B2 (en) * 2011-06-15 2013-04-09 Truesense Imaging, Inc. Identification of dies on a semiconductor wafer
US10923456B2 (en) * 2018-12-20 2021-02-16 Cerebras Systems Inc. Systems and methods for hierarchical exposure of an integrated circuit having multiple interconnected die

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Publication number Priority date Publication date Assignee Title
JPS5591853A (en) * 1978-12-29 1980-07-11 Fujitsu Ltd Semiconductor device
DE3066941D1 (en) * 1979-05-24 1984-04-19 Fujitsu Ltd Masterslice semiconductor device and method of producing it
DE3067832D1 (en) * 1980-07-10 1984-06-20 Ibm Process for compensating the proximity effect in electron beam projection devices
US4583111A (en) * 1983-09-09 1986-04-15 Fairchild Semiconductor Corporation Integrated circuit chip wiring arrangement providing reduced circuit inductance and controlled voltage gradients
EP0158222B1 (de) * 1984-03-29 1990-08-29 Sanyo Electric Co., Ltd. Integrierter Halbleiter-Schaltkreis mit mehrschichtigen Verbindungen
JPS6114734A (ja) * 1984-06-29 1986-01-22 Fujitsu Ltd 半導体集積回路装置及びその製造方法
US4858175A (en) * 1984-09-29 1989-08-15 Kabushiki Kaisha Toshiba Monolithic semi-custom IC having standard LSI sections and coupling gate array sections
US4774559A (en) * 1984-12-03 1988-09-27 International Business Machines Corporation Integrated circuit chip structure wiring and circuitry for driving highly capacitive on chip wiring nets
JPS6214428A (ja) * 1985-07-12 1987-01-23 Nec Corp 縮小投影型露光方法
US4696889A (en) * 1985-08-23 1987-09-29 Yevick George J Method of photoforming optical patterns for VLSI devices
JPS6281745A (ja) * 1985-10-05 1987-04-15 Fujitsu Ltd ウエハ−規模のｌｓｉ半導体装置とその製造方法
JPS6292439A (ja) * 1985-10-18 1987-04-27 Hoya Corp パタ−ン形成方法
GB8610655D0 (en) * 1986-05-01 1986-06-04 Smiths Industries Plc Integrated circuit substrates
JPS62291182A (ja) * 1986-06-11 1987-12-17 Nec Corp 半導体装置の製造方法
US4786613A (en) * 1987-02-24 1988-11-22 International Business Machines Corporation Method of combining gate array and standard cell circuits on a common semiconductor chip
JPS63298347A (ja) * 1987-05-29 1988-12-06 Hoya Corp パタ−ン形成方法
JPS6473616A (en) * 1987-09-14 1989-03-17 Nec Corp Manufacture of semiconductor device
GB8803171D0 (en) * 1988-02-11 1988-03-09 English Electric Valve Co Ltd Imaging apparatus
DE68929148T2 (de) * 1988-06-21 2000-09-21 Sanyo Electric Co., Ltd. Integrierte Halbleiterschaltung
KR920005863B1 (ko) * 1988-08-12 1992-07-23 산요덴끼 가부시끼가이샤 반도체 집적회로
US5364718A (en) * 1988-09-06 1994-11-15 Fujitsu Limited Method of exposing patttern of semiconductor devices and stencil mask for carrying out same
JPH0727968B2 (ja) * 1988-12-20 1995-03-29 株式会社東芝 半導体集積回路装置
JPH0329342A (ja) * 1989-06-26 1991-02-07 Toshiba Corp 半導体装置
US4985374A (en) * 1989-06-30 1991-01-15 Kabushiki Kaisha Toshiba Making a semiconductor device with ammonia treatment of photoresist
JPH03139821A (ja) * 1989-10-25 1991-06-14 Toshiba Corp 微細パターンの形成方法
US5302491A (en) * 1989-12-20 1994-04-12 North American Philips Corporation Method of encoding identification information on circuit dice using step and repeat lithography
US5132571A (en) * 1990-08-01 1992-07-21 Actel Corporation Programmable interconnect architecture having interconnects disposed above function modules
JP3344485B2 (ja) * 1990-11-09 2002-11-11 富士通株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
JPH04287346A (ja) 1992-10-12
US5539224A (en) 1996-07-23
DE69229887T2 (de) 2000-05-31
EP0505248B1 (de) 1999-09-01
EP0505248A1 (de) 1992-09-23
KR960009101B1 (en) 1996-07-10
US5696013A (en) 1997-12-09
JP3027990B2 (ja) 2000-04-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee