JPS6473616A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6473616A JPS6473616A JP62231605A JP23160587A JPS6473616A JP S6473616 A JPS6473616 A JP S6473616A JP 62231605 A JP62231605 A JP 62231605A JP 23160587 A JP23160587 A JP 23160587A JP S6473616 A JPS6473616 A JP S6473616A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- exposure
- exposed
- chip
- reducing projection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
PURPOSE:To manufacture a chip of larger size by exposing a peripheral region having a relatively nonfine pattern by means of simultaneous actual size exposure and an internal circuit region having a fine pattern by means of reducing projection exposure having excellent resolution. CONSTITUTION:A photoresist film on a semiconductor wafer is exposed by means of reducing projection exposure with a reticle containing an internal circuit pattern 1, and then exposed by means of simultaneous actual size exposure with a photomask containing a pattern dark part covering the previously exposed part and a predetermined pattern 3 of a peripheral region to be newly exposed. In this case, a latent image formed on the photoresist film may be aligned according to a normal method. Then, when it is developed, a desired resist pattern 5 synthesized on a semiconductor chip 4 is obtained. When with the pattern 5 as a mask it is etched, a semiconductor device having a chip size exceeding the exposure area of a reducing projection aligner can be manufactured.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62231605A JPS6473616A (en) | 1987-09-14 | 1987-09-14 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62231605A JPS6473616A (en) | 1987-09-14 | 1987-09-14 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6473616A true JPS6473616A (en) | 1989-03-17 |
Family
ID=16926131
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62231605A Pending JPS6473616A (en) | 1987-09-14 | 1987-09-14 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6473616A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0357209A (en) * | 1989-07-25 | 1991-03-12 | Nec Corp | Reduction-production type aligner |
| US5539224A (en) * | 1991-03-18 | 1996-07-23 | Fujitsu Limited | Semiconductor device having unit circuit-blocks in a common chip as a first layer with electrical interconnections therebetween provided exclusively in a second, upper, interconnection layer formed on the first layer |
| JP2001142224A (en) * | 1999-08-31 | 2001-05-25 | Semiconductor Energy Lab Co Ltd | Method for manufacturing semiconductor device |
-
1987
- 1987-09-14 JP JP62231605A patent/JPS6473616A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0357209A (en) * | 1989-07-25 | 1991-03-12 | Nec Corp | Reduction-production type aligner |
| US5539224A (en) * | 1991-03-18 | 1996-07-23 | Fujitsu Limited | Semiconductor device having unit circuit-blocks in a common chip as a first layer with electrical interconnections therebetween provided exclusively in a second, upper, interconnection layer formed on the first layer |
| US5696013A (en) * | 1991-03-18 | 1997-12-09 | Fujitsu Limited | Method of manufacturing semiconductor device having unit circuit-blocks |
| JP2001142224A (en) * | 1999-08-31 | 2001-05-25 | Semiconductor Energy Lab Co Ltd | Method for manufacturing semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR900007062A (en) | CHARGED PARTICLE BEAM EXPOSURE METHOD | |
| US4546066A (en) | Method for forming narrow images on semiconductor substrates | |
| TW344129B (en) | Pattern forming method and method of manufacturing liquid crystal display device | |
| KR100253580B1 (en) | Mask for stitching | |
| JPS6473616A (en) | Manufacture of semiconductor device | |
| KR970018110A (en) | Pattern Forming Method of Semiconductor Device | |
| EP0318956A3 (en) | Positive-working photoresist compositions and use thereof for forming positive-tone relief images | |
| TW200502677A (en) | Mask blank, mask blank manufacturing method, transfer mask manufacturing method, and semiconductor device manufacturing method | |
| JPS5623746A (en) | Manufacture of semiconductor device | |
| JPS56116625A (en) | Exposure of fine pattern | |
| JPS5676531A (en) | Manufacture of semiconductor device | |
| KR970049060A (en) | Micro pattern formation method by multiple exposure | |
| KR920003808B1 (en) | Method for forming pattern | |
| JP2714967B2 (en) | Method of forming resist pattern | |
| JPH06338452A (en) | Formation method of resist pattern | |
| KR980010603A (en) | Photomask manufacturing method | |
| JPH11153871A (en) | Forming method of resist pattern and semiconductor substrate | |
| JPS6370425A (en) | Fine pattern forming method | |
| KR960007293Y1 (en) | Stepper | |
| JPS5642234A (en) | Photomask preparation | |
| JPS57132008A (en) | Measuring method for pattern size | |
| KR950015577A (en) | Manufacturing method of semiconductor device | |
| EP1096551A3 (en) | Method for making integrated circuits having features with reduced critical dimensions | |
| JPS6442820A (en) | Manufacture of semiconductor integrated circuit | |
| KR19980015333A (en) | Method for forming fine pattern |