KR960009101B1 - Semiconductor device and the manufacturing method having unit circuit-block - Google Patents

Semiconductor device and the manufacturing method having unit circuit-block Download PDF

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Publication number
KR960009101B1
KR960009101B1 KR92004473A KR920004473A KR960009101B1 KR 960009101 B1 KR960009101 B1 KR 960009101B1 KR 92004473 A KR92004473 A KR 92004473A KR 920004473 A KR920004473 A KR 920004473A KR 960009101 B1 KR960009101 B1 KR 960009101B1
Authority
KR
South Korea
Prior art keywords
manufacturing
block
semiconductor device
unit circuit
circuit
Prior art date
Application number
KR92004473A
Other languages
English (en)
Inventor
Taiji Ema
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of KR960009101B1 publication Critical patent/KR960009101B1/ko

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L27/0207—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0073—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces
    • H05K3/0079—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces characterised by the method of application or removal of the mask

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR92004473A 1991-03-18 1992-03-18 Semiconductor device and the manufacturing method having unit circuit-block KR960009101B1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3051817A JP3027990B2 (ja) 1991-03-18 1991-03-18 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
KR960009101B1 true KR960009101B1 (en) 1996-07-10

Family

ID=12897453

Family Applications (1)

Application Number Title Priority Date Filing Date
KR92004473A KR960009101B1 (en) 1991-03-18 1992-03-18 Semiconductor device and the manufacturing method having unit circuit-block

Country Status (5)

Country Link
US (2) US5539224A (ko)
EP (1) EP0505248B1 (ko)
JP (1) JP3027990B2 (ko)
KR (1) KR960009101B1 (ko)
DE (1) DE69229887T2 (ko)

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US5671397A (en) 1993-12-27 1997-09-23 At&T Global Information Solutions Company Sea-of-cells array of transistors
US6675361B1 (en) 1993-12-27 2004-01-06 Hyundai Electronics America Method of constructing an integrated circuit comprising an embedded macro
US5783846A (en) * 1995-09-22 1998-07-21 Hughes Electronics Corporation Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering
US5859690A (en) * 1996-03-28 1999-01-12 Nikon Corporation Method of dividing and exposing patterns
US5973375A (en) * 1997-06-06 1999-10-26 Hughes Electronics Corporation Camouflaged circuit structure with step implants
US6192290B1 (en) * 1998-05-21 2001-02-20 Lucent Technologies Inc. System and method of manufacturing semicustom integrated circuits using reticle primitives from a library and interconnect reticles
JP2000068488A (ja) * 1998-08-20 2000-03-03 Oki Electric Ind Co Ltd 半導体集積回路のレイアウト方法
US6346427B1 (en) 1999-08-18 2002-02-12 Utmc Microelectronic Systems Inc. Parameter adjustment in a MOS integrated circuit
US6396368B1 (en) 1999-11-10 2002-05-28 Hrl Laboratories, Llc CMOS-compatible MEM switches and method of making
US7217977B2 (en) * 2004-04-19 2007-05-15 Hrl Laboratories, Llc Covert transformation of transistor properties as a circuit protection method
US6567967B2 (en) 2000-09-06 2003-05-20 Monterey Design Systems, Inc. Method for designing large standard-cell base integrated circuits
US6815816B1 (en) * 2000-10-25 2004-11-09 Hrl Laboratories, Llc Implanted hidden interconnections in a semiconductor device for preventing reverse engineering
US7294935B2 (en) * 2001-01-24 2007-11-13 Hrl Laboratories, Llc Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide
US6791191B2 (en) 2001-01-24 2004-09-14 Hrl Laboratories, Llc Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations
US6774413B2 (en) * 2001-06-15 2004-08-10 Hrl Laboratories, Llc Integrated circuit structure with programmable connector/isolator
US6740942B2 (en) * 2001-06-15 2004-05-25 Hrl Laboratories, Llc. Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact
US6897535B2 (en) 2002-05-14 2005-05-24 Hrl Laboratories, Llc Integrated circuit with reverse engineering protection
US7049667B2 (en) * 2002-09-27 2006-05-23 Hrl Laboratories, Llc Conductive channel pseudo block process and circuit to inhibit reverse engineering
US6979606B2 (en) * 2002-11-22 2005-12-27 Hrl Laboratories, Llc Use of silicon block process step to camouflage a false transistor
AU2003293540A1 (en) * 2002-12-13 2004-07-09 Raytheon Company Integrated circuit modification using well implants
US7242063B1 (en) 2004-06-29 2007-07-10 Hrl Laboratories, Llc Symmetric non-intrusive and covert technique to render a transistor permanently non-operable
US8168487B2 (en) 2006-09-28 2012-05-01 Hrl Laboratories, Llc Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer
US8728722B2 (en) * 2010-09-30 2014-05-20 Truesense Imaging, Inc. Stitching methods using multiple microlithographic expose tools
US8415813B2 (en) * 2011-06-15 2013-04-09 Truesense Imaging, Inc. Identification of dies on a semiconductor wafer
US10923456B2 (en) * 2018-12-20 2021-02-16 Cerebras Systems Inc. Systems and methods for hierarchical exposure of an integrated circuit having multiple interconnected die

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JPS62291182A (ja) * 1986-06-11 1987-12-17 Nec Corp 半導体装置の製造方法
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US5364718A (en) * 1988-09-06 1994-11-15 Fujitsu Limited Method of exposing patttern of semiconductor devices and stencil mask for carrying out same
JPH0727968B2 (ja) * 1988-12-20 1995-03-29 株式会社東芝 半導体集積回路装置
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Also Published As

Publication number Publication date
EP0505248A1 (en) 1992-09-23
US5696013A (en) 1997-12-09
JP3027990B2 (ja) 2000-04-04
EP0505248B1 (en) 1999-09-01
US5539224A (en) 1996-07-23
JPH04287346A (ja) 1992-10-12
DE69229887D1 (de) 1999-10-07
DE69229887T2 (de) 2000-05-31

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G160 Decision to publish patent application
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Payment date: 20080623

Year of fee payment: 13

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