DE69334324D1 - Herstellungsverfahren für Halbleitersubstrat - Google Patents

Herstellungsverfahren für Halbleitersubstrat

Info

Publication number
DE69334324D1
DE69334324D1 DE69334324T DE69334324T DE69334324D1 DE 69334324 D1 DE69334324 D1 DE 69334324D1 DE 69334324 T DE69334324 T DE 69334324T DE 69334324 T DE69334324 T DE 69334324T DE 69334324 D1 DE69334324 D1 DE 69334324D1
Authority
DE
Germany
Prior art keywords
semiconductor substrate
production method
production
semiconductor
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69334324T
Other languages
English (en)
Inventor
Nobuhiko Sato
Takao Yonehara
Kiyofumi Sakaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP3846092A external-priority patent/JP2910001B2/ja
Priority claimed from JP4038458A external-priority patent/JP2901031B2/ja
Priority claimed from JP01652492A external-priority patent/JP3287596B2/ja
Priority claimed from JP04016513A external-priority patent/JP3119384B2/ja
Priority claimed from JP1652392A external-priority patent/JP2994837B2/ja
Application filed by Canon Inc filed Critical Canon Inc
Application granted granted Critical
Publication of DE69334324D1 publication Critical patent/DE69334324D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02Elements
    • C30B29/06Silicon
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02422Non-crystalline insulating materials, e.g. glass, polymers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/02428Structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02365Forming inorganic semiconducting materials on a substrate
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    • H01L21/02433Crystal orientation
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    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02441Group 14 semiconducting materials
    • H01L21/0245Silicon, silicon germanium, germanium
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02365Forming inorganic semiconducting materials on a substrate
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    • H01L21/02494Structure
    • H01L21/02513Microstructure
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
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    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02587Structure
    • H01L21/0259Microstructure
    • H01L21/02598Microstructure monocrystalline
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
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    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02623Liquid deposition
    • H01L21/02628Liquid deposition using solutions
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02631Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02658Pretreatments
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/31051Planarisation of the insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3247Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1892Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof methods involving the use of temporary, removable substrates
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
DE69334324T 1992-01-30 1993-01-29 Herstellungsverfahren für Halbleitersubstrat Expired - Lifetime DE69334324D1 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP3846092A JP2910001B2 (ja) 1992-01-30 1992-01-30 半導体基材及びその作製方法
JP4038458A JP2901031B2 (ja) 1992-01-30 1992-01-30 半導体基材及びその作製方法
JP01652492A JP3287596B2 (ja) 1992-01-31 1992-01-31 半導体基材及びその加工方法
JP04016513A JP3119384B2 (ja) 1992-01-31 1992-01-31 半導体基板及びその作製方法
JP1652392A JP2994837B2 (ja) 1992-01-31 1992-01-31 半導体基板の平坦化方法、半導体基板の作製方法、及び半導体基板

Publications (1)

Publication Number Publication Date
DE69334324D1 true DE69334324D1 (de) 2010-05-06

Family

ID=27519822

Family Applications (3)

Application Number Title Priority Date Filing Date
DE69334324T Expired - Lifetime DE69334324D1 (de) 1992-01-30 1993-01-29 Herstellungsverfahren für Halbleitersubstrat
DE69333619T Expired - Fee Related DE69333619T2 (de) 1992-01-30 1993-01-29 Herstellungsverfahren für Halbleitersubstrate
DE69333152T Expired - Fee Related DE69333152T2 (de) 1992-01-30 1993-01-29 Verfahren zur Herstellung eines Halbleitersubstrates

Family Applications After (2)

Application Number Title Priority Date Filing Date
DE69333619T Expired - Fee Related DE69333619T2 (de) 1992-01-30 1993-01-29 Herstellungsverfahren für Halbleitersubstrate
DE69333152T Expired - Fee Related DE69333152T2 (de) 1992-01-30 1993-01-29 Verfahren zur Herstellung eines Halbleitersubstrates

Country Status (3)

Country Link
US (2) US5869387A (de)
EP (3) EP1251556B1 (de)
DE (3) DE69334324D1 (de)

Families Citing this family (117)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6121112A (en) * 1905-08-29 2000-09-19 Canon Kabushiki Kaisha Fabrication method for semiconductor substrate
US5719065A (en) * 1993-10-01 1998-02-17 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device with removable spacers
US7148119B1 (en) 1994-03-10 2006-12-12 Canon Kabushiki Kaisha Process for production of semiconductor substrate
JP3293736B2 (ja) 1996-02-28 2002-06-17 キヤノン株式会社 半導体基板の作製方法および貼り合わせ基体
US20030087503A1 (en) * 1994-03-10 2003-05-08 Canon Kabushiki Kaisha Process for production of semiconductor substrate
US6103598A (en) * 1995-07-13 2000-08-15 Canon Kabushiki Kaisha Process for producing semiconductor substrate
US6902616B1 (en) * 1995-07-19 2005-06-07 Semiconductor Energy Laboratory Co., Ltd. Method and apparatus for producing semiconductor device
DE69628505T2 (de) * 1995-07-21 2004-05-06 Canon K.K. Halbleitendes Substrat und dessen Herstellungsverfahren
CN1132223C (zh) * 1995-10-06 2003-12-24 佳能株式会社 半导体衬底及其制造方法
SG65697A1 (en) * 1996-11-15 1999-06-22 Canon Kk Process for producing semiconductor article
DE69728022T2 (de) * 1996-12-18 2004-08-12 Canon K.K. Vefahren zum Herstellen eines Halbleiterartikels unter Verwendung eines Substrates mit einer porösen Halbleiterschicht
CA2231625C (en) * 1997-03-17 2002-04-02 Canon Kabushiki Kaisha Semiconductor substrate having compound semiconductor layer, process for its production, and electronic device fabricated on semiconductor substrate
CA2233096C (en) * 1997-03-26 2003-01-07 Canon Kabushiki Kaisha Substrate and production method thereof
US6143628A (en) * 1997-03-27 2000-11-07 Canon Kabushiki Kaisha Semiconductor substrate and method of manufacturing the same
JP3647191B2 (ja) 1997-03-27 2005-05-11 キヤノン株式会社 半導体装置の製造方法
SG68035A1 (en) * 1997-03-27 1999-10-19 Canon Kk Method and apparatus for separating composite member using fluid
JPH10275905A (ja) * 1997-03-31 1998-10-13 Mitsubishi Electric Corp シリコンウェーハの製造方法およびシリコンウェーハ
US6162705A (en) 1997-05-12 2000-12-19 Silicon Genesis Corporation Controlled cleavage process and resulting device using beta annealing
US6291313B1 (en) 1997-05-12 2001-09-18 Silicon Genesis Corporation Method and device for controlled cleaving process
US20070122997A1 (en) 1998-02-19 2007-05-31 Silicon Genesis Corporation Controlled process and resulting device
US6033974A (en) * 1997-05-12 2000-03-07 Silicon Genesis Corporation Method for controlled cleaving process
EP1037272A4 (de) * 1997-06-19 2004-07-28 Asahi Chemical Ind Silizium auf isolator (soi) substrat und halbleitenbauelement und verfahren zum deren herstellung
US6548382B1 (en) 1997-07-18 2003-04-15 Silicon Genesis Corporation Gettering technique for wafers made using a controlled cleaving process
JP3292101B2 (ja) * 1997-07-18 2002-06-17 信越半導体株式会社 珪素単結晶基板表面の平滑化方法
US6686623B2 (en) 1997-11-18 2004-02-03 Semiconductor Energy Laboratory Co., Ltd. Nonvolatile memory and electronic apparatus
KR100258096B1 (ko) * 1997-12-01 2000-06-01 정선종 에스오아이(soi) 기판 제조방법
TW408503B (en) * 1997-12-06 2000-10-11 United Microelectronics Corp Manufacture of the charge storage node
US6171982B1 (en) * 1997-12-26 2001-01-09 Canon Kabushiki Kaisha Method and apparatus for heat-treating an SOI substrate and method of preparing an SOI substrate by using the same
US6413874B1 (en) * 1997-12-26 2002-07-02 Canon Kabushiki Kaisha Method and apparatus for etching a semiconductor article and method of preparing a semiconductor article by using the same
SG71903A1 (en) 1998-01-30 2000-04-18 Canon Kk Process of reclamation of soi substrate and reproduced substrate
JP3500063B2 (ja) 1998-04-23 2004-02-23 信越半導体株式会社 剥離ウエーハを再利用する方法および再利用に供されるシリコンウエーハ
JPH11307472A (ja) * 1998-04-23 1999-11-05 Shin Etsu Handotai Co Ltd 水素イオン剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ
DE19821999A1 (de) * 1998-05-15 1999-11-18 Siemens Ag SOI-Halbleiteranordnung und Verfahren zur Herstellung derselben
JP3697106B2 (ja) 1998-05-15 2005-09-21 キヤノン株式会社 半導体基板の作製方法及び半導体薄膜の作製方法
JP3762144B2 (ja) * 1998-06-18 2006-04-05 キヤノン株式会社 Soi基板の作製方法
JP2000012864A (ja) 1998-06-22 2000-01-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
US6291326B1 (en) 1998-06-23 2001-09-18 Silicon Genesis Corporation Pre-semiconductor process implant and post-process film separation
CN1495915A (zh) * 1998-07-03 2004-05-12 ������������ʽ���� 光电转换元件
JP3358550B2 (ja) * 1998-07-07 2002-12-24 信越半導体株式会社 Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ
US7294535B1 (en) * 1998-07-15 2007-11-13 Semiconductor Energy Laboratory Co., Ltd. Crystalline semiconductor thin film, method of fabricating the same, semiconductor device, and method of fabricating the same
US7153729B1 (en) 1998-07-15 2006-12-26 Semiconductor Energy Laboratory Co., Ltd. Crystalline semiconductor thin film, method of fabricating the same, semiconductor device, and method of fabricating the same
US7084016B1 (en) * 1998-07-17 2006-08-01 Semiconductor Energy Laboratory Co., Ltd. Crystalline semiconductor thin film, method of fabricating the same, semiconductor device, and method of fabricating the same
US7282398B2 (en) * 1998-07-17 2007-10-16 Semiconductor Energy Laboratory Co., Ltd. Crystalline semiconductor thin film, method of fabricating the same, semiconductor device and method of fabricating the same
US6180497B1 (en) 1998-07-23 2001-01-30 Canon Kabushiki Kaisha Method for producing semiconductor base members
US6271101B1 (en) 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
US20010001384A1 (en) * 1998-07-29 2001-05-24 Takeshi Arai Silicon epitaxial wafer and production method therefor
US6559036B1 (en) * 1998-08-07 2003-05-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
US6335269B1 (en) 1998-09-04 2002-01-01 Canon Kabushiki Kaisha Semiconductor substrate and method for producing the same
JP4476390B2 (ja) 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
EP0996145A3 (de) * 1998-09-04 2000-11-08 Canon Kabushiki Kaisha Verfahren zur Herstellung von Halbleitersubstraten
TW465101B (en) * 1998-09-04 2001-11-21 Canon Kk Semiconductor substrate and method for producing the same
DE19841430A1 (de) * 1998-09-10 2000-05-25 Inst Physikalische Elektronik Verfahren zur Herstellung kristalliner Halbleiterschichten
JP2000124092A (ja) * 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ
JP2000223682A (ja) * 1999-02-02 2000-08-11 Canon Inc 基体の処理方法及び半導体基板の製造方法
US6410436B2 (en) 1999-03-26 2002-06-25 Canon Kabushiki Kaisha Method of cleaning porous body, and process for producing porous body, non-porous film or bonded substrate
JP3911901B2 (ja) 1999-04-09 2007-05-09 信越半導体株式会社 Soiウエーハおよびsoiウエーハの製造方法
US6881644B2 (en) 1999-04-21 2005-04-19 Silicon Genesis Corporation Smoothing method for cleaved films made using a release layer
US6171965B1 (en) 1999-04-21 2001-01-09 Silicon Genesis Corporation Treatment method of cleaved film for the manufacture of substrates
US6287941B1 (en) * 1999-04-21 2001-09-11 Silicon Genesis Corporation Surface finishing of SOI substrates using an EPI process
US6204151B1 (en) * 1999-04-21 2001-03-20 Silicon Genesis Corporation Smoothing method for cleaved films made using thermal treatment
AT409429B (de) * 1999-07-15 2002-08-26 Sez Semiconduct Equip Zubehoer Verfahren zum ätzbehandeln von halbleitersubstraten zwecks freilegen einer metallschicht
US6500732B1 (en) 1999-08-10 2002-12-31 Silicon Genesis Corporation Cleaving process to fabricate multilayered substrates using low implantation doses
EP1939932A1 (de) * 1999-08-10 2008-07-02 Silicon Genesis Corporation Ein Substrat mit einer verspannten Silizium-Germanium Trennschicht
US6221740B1 (en) 1999-08-10 2001-04-24 Silicon Genesis Corporation Substrate cleaving tool and method
US6263941B1 (en) 1999-08-10 2001-07-24 Silicon Genesis Corporation Nozzle for cleaving substrates
FR2797713B1 (fr) 1999-08-20 2002-08-02 Soitec Silicon On Insulator Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
US6653209B1 (en) 1999-09-30 2003-11-25 Canon Kabushiki Kaisha Method of producing silicon thin film, method of constructing SOI substrate and semiconductor device
EP1235258A4 (de) * 1999-10-29 2007-03-28 Matsushita Electric Ind Co Ltd Methode, ein substrat zu reinigen und herstellungsmethode für eine halbleiteranordnung
GB9929521D0 (en) * 1999-12-15 2000-02-09 Secr Defence Bonded products and methods of fabrication therefor
US6376395B2 (en) * 2000-01-11 2002-04-23 Memc Electronic Materials, Inc. Semiconductor wafer manufacturing process
JP2001351895A (ja) 2000-06-09 2001-12-21 Denso Corp 半導体装置の製造方法
JP2002110949A (ja) 2000-09-28 2002-04-12 Canon Inc Soiの熱処理方法及び製造方法
US6660606B2 (en) 2000-09-29 2003-12-09 Canon Kabushiki Kaisha Semiconductor-on-insulator annealing method
JP2002110688A (ja) 2000-09-29 2002-04-12 Canon Inc Soiの熱処理方法及び製造方法
US8507361B2 (en) 2000-11-27 2013-08-13 Soitec Fabrication of substrates with a useful layer of monocrystalline semiconductor material
FR2840731B3 (fr) * 2002-06-11 2004-07-30 Soitec Silicon On Insulator Procede de fabrication d'un substrat comportant une couche utile en materiau semi-conducteur monocristallin de proprietes ameliorees
FR2894990B1 (fr) * 2005-12-21 2008-02-22 Soitec Silicon On Insulator Procede de fabrication de substrats, notamment pour l'optique,l'electronique ou l'optoelectronique et substrat obtenu selon ledit procede
FR2817394B1 (fr) * 2000-11-27 2003-10-31 Soitec Silicon On Insulator Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede
JP2002231945A (ja) 2001-02-06 2002-08-16 Denso Corp 半導体装置の製造方法
JP3754897B2 (ja) * 2001-02-09 2006-03-15 キヤノン株式会社 半導体装置用基板およびsoi基板の製造方法
JP2002270614A (ja) * 2001-03-12 2002-09-20 Canon Inc Soi基体、その熱処理方法、それを有する半導体装置およびその製造方法
DE10131249A1 (de) 2001-06-28 2002-05-23 Wacker Siltronic Halbleitermat Verfahren zur Herstellung eines Films oder einer Schicht aus halbleitendem Material
US7052117B2 (en) * 2002-07-03 2006-05-30 Dimatix, Inc. Printhead having a thin pre-fired piezoelectric layer
US7535100B2 (en) * 2002-07-12 2009-05-19 The United States Of America As Represented By The Secretary Of The Navy Wafer bonding of thinned electronic materials and circuits to high performance substrates
WO2004010505A1 (ja) * 2002-07-18 2004-01-29 Shin-Etsu Handotai Co.,Ltd. Soiウェーハおよびその製造方法
US8187377B2 (en) * 2002-10-04 2012-05-29 Silicon Genesis Corporation Non-contact etch annealing of strained layers
US7256104B2 (en) * 2003-05-21 2007-08-14 Canon Kabushiki Kaisha Substrate manufacturing method and substrate processing apparatus
ATE504082T1 (de) * 2003-05-27 2011-04-15 Soitec Silicon On Insulator Verfahren zur herstellung einer heteroepitaktischen mikrostruktur
US7964925B2 (en) * 2006-10-13 2011-06-21 Hewlett-Packard Development Company, L.P. Photodiode module and apparatus including multiple photodiode modules
US7542197B2 (en) * 2003-11-01 2009-06-02 Silicon Quest Kabushiki-Kaisha Spatial light modulator featured with an anti-reflective structure
US7354815B2 (en) * 2003-11-18 2008-04-08 Silicon Genesis Corporation Method for fabricating semiconductor devices using strained silicon bearing material
JP2005311199A (ja) * 2004-04-23 2005-11-04 Canon Inc 基板の製造方法
DE102004030612B3 (de) 2004-06-24 2006-04-20 Siltronic Ag Halbleitersubstrat und Verfahren zu dessen Herstellung
US7214548B2 (en) * 2004-08-30 2007-05-08 International Business Machines Corporation Apparatus and method for flattening a warped substrate
US8993410B2 (en) 2006-09-08 2015-03-31 Silicon Genesis Corporation Substrate cleaving under controlled stress conditions
US8293619B2 (en) 2008-08-28 2012-10-23 Silicon Genesis Corporation Layer transfer of films utilizing controlled propagation
US7811900B2 (en) 2006-09-08 2010-10-12 Silicon Genesis Corporation Method and structure for fabricating solar cells using a thick layer transfer process
US9362439B2 (en) 2008-05-07 2016-06-07 Silicon Genesis Corporation Layer transfer of films utilizing controlled shear region
US20080135827A1 (en) * 2006-09-25 2008-06-12 Stmicroelectronics Crolles 2 Sas MIM transistor
DE102007006151B4 (de) * 2007-02-07 2008-11-06 Siltronic Ag Verfahren zur Verringerung und Homogenisierung der Dicke einer Halbleiterschicht, die sich auf der Oberfläche eines elektrisch isolierenden Materials befindet
KR101443580B1 (ko) * 2007-05-11 2014-10-30 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Soi구조를 갖는 기판
US8101501B2 (en) * 2007-10-10 2012-01-24 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
US8207046B2 (en) * 2007-12-27 2012-06-26 Sharp Kabushiki Kaisha Method for producing semiconductor device and semiconductor device produced by same method
WO2009084284A1 (ja) 2007-12-27 2009-07-09 Sharp Kabushiki Kaisha 半導体装置用の絶縁基板、半導体装置、及び、半導体装置の製造方法
KR101046060B1 (ko) * 2008-07-29 2011-07-01 주식회사 동부하이텍 이미지센서 제조방법
US8330126B2 (en) 2008-08-25 2012-12-11 Silicon Genesis Corporation Race track configuration and method for wafering silicon solar substrates
US8048754B2 (en) 2008-09-29 2011-11-01 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate and method for manufacturing single crystal semiconductor layer
JP5611571B2 (ja) 2008-11-27 2014-10-22 株式会社半導体エネルギー研究所 半導体基板の作製方法及び半導体装置の作製方法
JP5470839B2 (ja) * 2008-12-25 2014-04-16 株式会社Sumco 貼り合わせシリコンウェーハの製造方法
US8329557B2 (en) 2009-05-13 2012-12-11 Silicon Genesis Corporation Techniques for forming thin films by implantation with reduced channeling
US8476147B2 (en) * 2010-02-03 2013-07-02 Semiconductor Energy Laboratory Co., Ltd. SOI substrate and manufacturing method thereof
JP5755931B2 (ja) 2010-04-28 2015-07-29 株式会社半導体エネルギー研究所 半導体膜の作製方法、電極の作製方法、2次電池の作製方法、および太陽電池の作製方法
WO2013002212A1 (ja) * 2011-06-30 2013-01-03 京セラ株式会社 複合基板およびその製造方法
US9136134B2 (en) 2012-02-22 2015-09-15 Soitec Methods of providing thin layers of crystalline semiconductor material, and related structures and devices
US9202711B2 (en) * 2013-03-14 2015-12-01 Sunedison Semiconductor Limited (Uen201334164H) Semiconductor-on-insulator wafer manufacturing method for reducing light point defects and surface roughness
US9611133B2 (en) * 2014-09-11 2017-04-04 Invensense, Inc. Film induced interface roughening and method of producing the same
CN106960793A (zh) * 2016-01-11 2017-07-18 中芯国际集成电路制造(上海)有限公司 鳍部的形成方法和鳍式场效应管的形成方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3929529A (en) * 1974-12-09 1975-12-30 Ibm Method for gettering contaminants in monocrystalline silicon
JPS5516464A (en) 1978-07-21 1980-02-05 Nec Corp Method of forming wafer for semiconductor device
US4649627A (en) * 1984-06-28 1987-03-17 International Business Machines Corporation Method of fabricating silicon-on-insulator transistors with a shared element
US4601779A (en) * 1985-06-24 1986-07-22 International Business Machines Corporation Method of producing a thin silicon-on-insulator layer
JPS62123098A (ja) * 1985-11-22 1987-06-04 Toshiba Ceramics Co Ltd シリコン単結晶の製造方法
JP2559700B2 (ja) * 1986-03-18 1996-12-04 富士通株式会社 半導体装置の製造方法
US4771016A (en) * 1987-04-24 1988-09-13 Harris Corporation Using a rapid thermal process for manufacturing a wafer bonded soi semiconductor
DD266888A1 (de) * 1987-11-12 1989-04-12 Akad Wissenschaften Ddr Verfahren zur oberflaechenglaettung dicker soi-schichten
JPH01183825A (ja) * 1988-01-19 1989-07-21 Sanyo Electric Co Ltd 単結晶シリコン膜の形成方法
JPH02248051A (ja) * 1989-03-20 1990-10-03 Fujitsu Ltd 半導体装置の製造方法
JPH0342818A (ja) * 1989-07-10 1991-02-25 Nippon Telegr & Teleph Corp <Ntt> 化合物半導体装置とその製造方法
JP2801704B2 (ja) * 1989-12-11 1998-09-21 株式会社東芝 半導体基板の製造方法
JP3253099B2 (ja) * 1990-03-27 2002-02-04 キヤノン株式会社 半導体基板の作製方法
US5089441A (en) * 1990-04-16 1992-02-18 Texas Instruments Incorporated Low-temperature in-situ dry cleaning process for semiconductor wafers
DE69133359T2 (de) * 1990-08-03 2004-12-16 Canon K.K. Verfahren zur Herstellung eines SOI-Substrats
JPH0719738B2 (ja) * 1990-09-06 1995-03-06 信越半導体株式会社 接合ウェーハ及びその製造方法
CA2069038C (en) * 1991-05-22 1997-08-12 Kiyofumi Sakaguchi Method for preparing semiconductor member
JP3112106B2 (ja) * 1991-10-11 2000-11-27 キヤノン株式会社 半導体基材の作製方法
EP1179842A3 (de) * 1992-01-31 2002-09-04 Canon Kabushiki Kaisha Halbleitersubstrat und Herstellungsverfahren
JP3416163B2 (ja) * 1992-01-31 2003-06-16 キヤノン株式会社 半導体基板及びその作製方法

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