DE69131241T2 - Herstellungsverfahren für Halbleiteranordnungen - Google Patents

Herstellungsverfahren für Halbleiteranordnungen

Info

Publication number
DE69131241T2
DE69131241T2 DE69131241T DE69131241T DE69131241T2 DE 69131241 T2 DE69131241 T2 DE 69131241T2 DE 69131241 T DE69131241 T DE 69131241T DE 69131241 T DE69131241 T DE 69131241T DE 69131241 T2 DE69131241 T2 DE 69131241T2
Authority
DE
Germany
Prior art keywords
manufacturing process
semiconductor devices
semiconductor
devices
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69131241T
Other languages
English (en)
Other versions
DE69131241D1 (de
Inventor
Shuichi Kameyama
Atsushi Hori
Hiroshi Shimomura
Mizuki Segawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE69131241D1 publication Critical patent/DE69131241D1/de
Publication of DE69131241T2 publication Critical patent/DE69131241T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/011—Bipolar transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/124—Polycrystalline emitter
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/969—Simultaneous formation of monocrystalline and polycrystalline regions
DE69131241T 1990-07-13 1991-07-15 Herstellungsverfahren für Halbleiteranordnungen Expired - Fee Related DE69131241T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP18653390 1990-07-13
JP19120090 1990-07-18

Publications (2)

Publication Number Publication Date
DE69131241D1 DE69131241D1 (de) 1999-06-24
DE69131241T2 true DE69131241T2 (de) 1999-12-02

Family

ID=26503827

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69131241T Expired - Fee Related DE69131241T2 (de) 1990-07-13 1991-07-15 Herstellungsverfahren für Halbleiteranordnungen

Country Status (3)

Country Link
US (1) US5296388A (de)
EP (1) EP0466195B1 (de)
DE (1) DE69131241T2 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5453389A (en) * 1993-08-27 1995-09-26 National Semiconductor, Inc. Defect-free bipolar process
JPH07142419A (ja) * 1993-11-15 1995-06-02 Toshiba Corp 半導体装置の製造方法
US5420050A (en) * 1993-12-20 1995-05-30 United Technologies Corporation Method of enhancing the current gain of bipolar junction transistors
KR0161378B1 (ko) * 1994-06-13 1998-12-01 김광호 바이폴라 접합 트랜지스터 제조방법
JP3545503B2 (ja) * 1995-08-11 2004-07-21 株式会社日立製作所 半導体集積回路装置の製造方法
US5637518A (en) * 1995-10-16 1997-06-10 Micron Technology, Inc. Method of making a field effect transistor having an elevated source and an elevated drain
JP2001085442A (ja) * 1999-09-09 2001-03-30 Mitsubishi Electric Corp トランジスタを備えた半導体装置
DE10034942B4 (de) * 2000-07-12 2004-08-05 Infineon Technologies Ag Verfahren zur Erzeugung eines Halbleitersubstrats mit vergrabener Dotierung
US6620710B1 (en) 2000-09-18 2003-09-16 Hewlett-Packard Development Company, L.P. Forming a single crystal semiconductor film on a non-crystalline surface
US6887765B2 (en) * 2000-12-19 2005-05-03 Texas Instruments Incorporated Method for manufacturing a bipolar junction transistor
US6771010B2 (en) * 2001-04-30 2004-08-03 Hewlett-Packard Development Company, L.P. Silicon emitter with low porosity heavily doped contact layer
KR100449948B1 (ko) * 2002-05-18 2004-09-30 주식회사 하이닉스반도체 콘택저항을 감소시킨 콘택플러그 형성방법
DE10324065A1 (de) * 2003-05-27 2004-12-30 Texas Instruments Deutschland Gmbh Verfahren zur Herstellung eines integrierten Silizium-Germanium-Heterobipolartranistors und ein integrierter Silizium-Germanium Heterobipolartransitor
TWI250640B (en) * 2003-06-19 2006-03-01 Samsung Electronics Co Ltd Bipolar junction transistors and methods of manufacturing the same
US20070298576A1 (en) * 2006-06-21 2007-12-27 Kuhn Kelin J Methods of forming bipolar transistors by silicide through contact and structures formed thereby
US8004013B2 (en) * 2007-06-15 2011-08-23 Sandisk 3D Llc Polycrystalline thin film bipolar transistors
US7855119B2 (en) * 2007-06-15 2010-12-21 Sandisk 3D Llc Method for forming polycrystalline thin film bipolar transistors
US8338906B2 (en) * 2008-01-30 2012-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Schottky device
KR20120064364A (ko) * 2010-12-09 2012-06-19 삼성전자주식회사 태양 전지의 제조 방법
CN103887330B (zh) * 2014-04-04 2016-09-14 哈尔滨工业大学 一种基于发射极电极接触方式的抗辐照双极器件及该双极器件的制备方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2449688C3 (de) * 1974-10-18 1980-07-10 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Herstellung einer dotierten Zone eines Leitfähigkeitstyps in einem Halbleiterkörper
JPS5893221A (ja) * 1981-11-30 1983-06-02 Toshiba Corp 半導体薄膜構造とその製造方法
US4431460A (en) * 1982-03-08 1984-02-14 International Business Machines Corporation Method of producing shallow, narrow base bipolar transistor structures via dual implantations of selected polycrystalline layer
JPS6063961A (ja) * 1983-08-30 1985-04-12 Fujitsu Ltd 半導体装置の製造方法
US4663825A (en) * 1984-09-27 1987-05-12 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
JPS61208869A (ja) * 1985-03-14 1986-09-17 Nec Corp 半導体装置及びその製造方法
JPH0695521B2 (ja) * 1987-02-19 1994-11-24 富士通株式会社 バイポ−ラトランジスタの製造方法
JPS6476763A (en) * 1987-09-18 1989-03-22 Nec Corp Manufacture of semiconductor device
JPH01181561A (ja) * 1988-01-12 1989-07-19 Toshiba Corp 半導体装置の製造方法
JPH026032A (ja) * 1988-06-24 1990-01-10 Aida Eng Ltd 環状溝の成形方法
US5059544A (en) * 1988-07-14 1991-10-22 International Business Machines Corp. Method of forming bipolar transistor having self-aligned emitter-base using selective and non-selective epitaxy
JPH0226032A (ja) * 1988-07-14 1990-01-29 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
KR910005401B1 (ko) * 1988-09-07 1991-07-29 경상현 비결정 실리콘을 이용한 자기정렬 트랜지스터 제조방법
JPH0691263B2 (ja) * 1988-10-19 1994-11-14 株式会社東芝 半導体装置の製造方法

Also Published As

Publication number Publication date
EP0466195A2 (de) 1992-01-15
EP0466195A3 (en) 1993-03-24
EP0466195B1 (de) 1999-05-19
US5296388A (en) 1994-03-22
DE69131241D1 (de) 1999-06-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee