DE69329928D1 - Herstellungsverfahren für integrierten Schaltkreis - Google Patents

Herstellungsverfahren für integrierten Schaltkreis

Info

Publication number
DE69329928D1
DE69329928D1 DE69329928T DE69329928T DE69329928D1 DE 69329928 D1 DE69329928 D1 DE 69329928D1 DE 69329928 T DE69329928 T DE 69329928T DE 69329928 T DE69329928 T DE 69329928T DE 69329928 D1 DE69329928 D1 DE 69329928D1
Authority
DE
Germany
Prior art keywords
integrated circuit
manufacturing process
manufacturing
integrated
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69329928T
Other languages
English (en)
Inventor
Kuo-Hua Lee
Chen-Hua Douglas Yu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Application granted granted Critical
Publication of DE69329928D1 publication Critical patent/DE69329928D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
DE69329928T 1992-11-24 1993-11-18 Herstellungsverfahren für integrierten Schaltkreis Expired - Lifetime DE69329928D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US98216592A 1992-11-24 1992-11-24

Publications (1)

Publication Number Publication Date
DE69329928D1 true DE69329928D1 (de) 2001-03-22

Family

ID=25528895

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69329928T Expired - Lifetime DE69329928D1 (de) 1992-11-24 1993-11-18 Herstellungsverfahren für integrierten Schaltkreis

Country Status (5)

Country Link
US (1) US5418173A (de)
EP (1) EP0601723B1 (de)
JP (1) JPH06216154A (de)
KR (1) KR940012540A (de)
DE (1) DE69329928D1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07184339A (ja) * 1993-12-24 1995-07-21 Asmo Co Ltd モータの取付け構造
US5846887A (en) * 1995-11-30 1998-12-08 Hyundai Electronics Industries Co., Ltd. Method for removing defects by ion implantation using medium temperature oxide layer
US6063676A (en) * 1997-06-09 2000-05-16 Integrated Device Technology, Inc. Mosfet with raised source and drain regions
US6043129A (en) * 1997-06-09 2000-03-28 Integrated Device Technology, Inc. High density MOSFET with raised source and drain regions
US7402467B1 (en) 1999-03-26 2008-07-22 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
EP1646080B1 (de) * 2004-10-07 2014-09-24 Imec Ätzung von Strukturen mit hoher Topographie

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3632438A (en) * 1967-09-29 1972-01-04 Texas Instruments Inc Method for increasing the stability of semiconductor devices
US4590664A (en) * 1983-07-29 1986-05-27 Harris Corporation Method of fabricating low noise reference diodes and transistors
US4732865A (en) * 1986-10-03 1988-03-22 Tektronix, Inc. Self-aligned internal mobile ion getter for multi-layer metallization on integrated circuits
DE3880860T2 (de) * 1987-03-04 1993-10-28 Toshiba Kawasaki Kk Halbleiterspeicheranordnung und Verfahren zu ihrer Herstellung.
EP0315350A1 (de) * 1987-11-02 1989-05-10 AT&T Corp. Technik zum intrinsischen Gettern bei niedriger Temperatur
EP0366343B1 (de) * 1988-10-28 1996-03-20 AT&T Corp. Integrierte Schaltungherstellung, unter Anwendung eines Niedrig-Temperatur-Verfahrens zur Herstellung von Silicid-Strukturen
EP0375255A3 (de) * 1988-12-21 1991-09-04 AT&T Corp. Verfahren zur Herabsetzung der Verunreinigung durch bewegliche Ionen in integrierten Halbleiterschaltungen
US4980301A (en) * 1988-12-21 1990-12-25 At&T Bell Laboratories Method for reducing mobile ion contamination in semiconductor integrated circuits
US4988405A (en) * 1989-12-21 1991-01-29 At&T Bell Laboratories Fabrication of devices utilizing a wet etchback procedure
JPH03276627A (ja) * 1990-03-26 1991-12-06 Fujitsu Ltd 半導体装置の製造方法
US5022958A (en) * 1990-06-27 1991-06-11 At&T Bell Laboratories Method of etching for integrated circuits with planarized dielectric

Also Published As

Publication number Publication date
EP0601723B1 (de) 2001-02-14
KR940012540A (ko) 1994-06-23
EP0601723A2 (de) 1994-06-15
EP0601723A3 (de) 1995-05-17
JPH06216154A (ja) 1994-08-05
US5418173A (en) 1995-05-23

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Legal Events

Date Code Title Description
8332 No legal effect for de