WO2013002212A1 - 複合基板およびその製造方法 - Google Patents
複合基板およびその製造方法 Download PDFInfo
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- WO2013002212A1 WO2013002212A1 PCT/JP2012/066263 JP2012066263W WO2013002212A1 WO 2013002212 A1 WO2013002212 A1 WO 2013002212A1 JP 2012066263 W JP2012066263 W JP 2012066263W WO 2013002212 A1 WO2013002212 A1 WO 2013002212A1
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- substrate
- oxide layer
- layer
- epitaxial layer
- composite substrate
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76262—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using selective deposition of single crystal silicon, i.e. SEG techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/86—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
Definitions
- the present invention relates to a composite substrate for forming a semiconductor element in which a plurality of materials are combined and a method for manufacturing the same.
- a method for manufacturing a composite substrate according to an embodiment of the present invention includes an epitaxial layer forming step of forming an epitaxial layer having semiconductor properties on a first substrate made of a semiconductor material, and ALD (Atomic Layer Deposition) on the epitaxial layer.
- the composite substrate according to the embodiment of the present invention is an epitaxial layer having an oxide layer and a semiconductor property in this order from the second substrate side between the first substrate made of a semiconductor material and the second substrate made of an insulating material.
- a layer is arranged, and oxygen atoms are arranged on the epitaxial layer side of the oxide layer.
- FIG. (A)-(e) is sectional drawing which shows the manufacturing process of the manufacturing method of the composite substrate which concerns on one Embodiment of this invention. It is a flowchart which shows an oxide layer formation process. It is principal part sectional drawing of the composite substrate containing the oxide layer formed by FIG. (A), (b) is sectional drawing which shows the process following FIG. 1 which shows the modification of embodiment of this invention.
- (A) is a top view which shows schematic structure of the composite substrate which concerns on one Embodiment of this invention, (b) is the fragmentary sectional view which looked at the composite substrate.
- a first substrate 10 made of a semiconductor material is prepared.
- the semiconductor material is not particularly limited as long as it has semiconductor properties such as Si, GaAs, GaP, and GaN.
- the semiconductor material is formed of silicon (Si) will be described as an example.
- the silicon of the first substrate 10 p-type or n-type silicon can be adopted.
- the dopant concentration of the first substrate 10 can be freely set.
- a material having semiconductor properties is epitaxially grown on the upper surface of the first substrate 10 on the arrow D1 direction (first direction) side to form an epitaxial layer (semiconductor layer) 20.
- a material having semiconductor properties Si, GaAs, SiGe, or the like can be appropriately selected.
- silicon is used as the first substrate 10
- silicon that is the same material as that constituting the first substrate 10 is used.
- thermal chemical vapor deposition method in which a gaseous silicon compound is passed through the surface of the first substrate 10 while being thermally decomposed while growing the first substrate 10 (thermal CVD method).
- thermal CVD method thermal chemical vapor deposition method
- Various methods such as these can be adopted. Since the epitaxial layer 20 is epitaxially grown on the silicon substrate, lattice defects can be reduced as compared with the case of epitaxial growth on the sapphire substrate.
- the epitaxial layer 20 is usually formed in a vacuum atmosphere. For this reason, mixing of impurities into the epitaxial layer 20 can be suppressed. In particular, mixing of oxygen can be suppressed. Specifically, the oxygen concentration in the layer can be 1 ⁇ 10 16 [atoms / cm 3 ] or less.
- p-type or n-type silicon and having a smaller amount of dopant than the first substrate 10 can be employed.
- the upper surface portion of the epitaxial layer 20 is formed to have any one of a relatively low concentration of p ⁇ and n ⁇ dopants and non-doped.
- the p ⁇ dopant concentration include a range of less than 1 ⁇ 10 16 [atoms / cm 3] .
- the n ⁇ dopant concentration include a range of less than 5 ⁇ 10 15 [atoms / cm 3 ].
- non-doped silicon herein is silicon that is simply not doped with the intention of impurities, and is not limited to intrinsic silicon that does not contain impurities.
- the dopant concentration of the epitaxial layer 20 can be controlled by adjusting the supply amount of impurities during epitaxial growth. By making this impurity supply zero, non-doped silicon can be formed. Further, the dopant concentration may be gradually changed by reducing the diffusion of the dopant generated during the epitaxial growth.
- the thickness of the epitaxial layer 20 is not particularly limited, but is about 2 ⁇ m, for example.
- the epitaxial layer 20 as a high resistance layer, it is possible to suppress the occurrence of leakage current when a semiconductor element is formed.
- an oxide layer 30 is formed on the upper surface of the epitaxial layer 20 in the direction of arrow D1 (first direction) by an ALD (Atomic Layer Deposition) method.
- Various materials can be used as the oxide material.
- aluminum oxide (AlO x ) is used. More specifically, trimethylaluminum (TMA) using aluminum as a raw material and radical oxygen generated from H 2 O gas or oxygen gas are alternately flowed on the substrate surface, and between each gas, Ar or the like
- TMA trimethylaluminum
- This film is formed at a cycle of about 0.1 nm / one atomic layer, and the time required for one cycle is about several seconds.
- the thickness of the oxide layer 30 may be about 50 nm, it is preferable to form the oxide layer 30 with a thickness of 100 nm or less because of the takt time.
- the deposition temperature of the oxide layer 30 is determined within a temperature range called a normal ALD window.
- the ALD window indicates a temperature range peculiar to a precursor (TMA and H 2 O in this example) used in the ALD method capable of obtaining a uniform film thickness.
- TMA and H 2 O examples of the temperature range include 200 ° C. to 300 ° C.
- a second substrate 40 made of an insulating material is prepared.
- a material for forming the second substrate 40 aluminum oxide single crystal (sapphire), silicon carbide, or the like can be used.
- sapphire is employed as the second substrate 40.
- the crystal plane of sapphire is not particularly limited, but the R plane is preferably used.
- the R plane the lattice constant with Si constituting the epitaxial layer 20 can be made closer.
- spinel type ⁇ alumina can be obtained. In that case, the proportion of Al atoms occupying the outermost surface can be increased.
- the bonding method include a method of activating and bonding the surfaces of the surfaces to be bonded, and a method of bonding using electrostatic force.
- the method for activating the surface include a method for activating by irradiating an ion beam or a neutron beam in a vacuum to etch the surface, a method for activating by etching the surface with a chemical solution, and the like. You may perform this joining under normal temperature.
- bonding at room temperature bonding can be performed without changing the dopant distribution in the epitaxial layer 20.
- “normal temperature” is preferably about room temperature, but also includes a temperature range lower than a bonding temperature used in a general substrate bonding technique of different materials. For example, it can be exemplified below 300 ° C.
- the oxide layer 30 and the second substrate 40 are directly connected by solid phase bonding (Solid-State Bonding) using atomic force or the like. Are joined together.
- Solid-State Bonding Solid-State Bonding
- a hybrid layer may be formed between the oxide layer 30 and the second substrate 40.
- substrate 40 have a small surface roughness of the surface to join.
- This surface roughness is represented by arithmetic mean roughness Ra, for example. Examples of the range of the arithmetic average roughness Ra include less than 10 nm.
- the composite substrate 50 having the epitaxial layer 20 and the oxide layer 30 between the first substrate 10 and the second substrate 40 can be formed.
- the oxide layer 30 is produced by a thin film forming method other than the ALD method (sputtering method or the like), even if the surface is activated and contacted at room temperature, The second substrate 40 cannot be bonded.
- the first substrate 10 uses a single crystal substrate, and the epitaxial layer 20 formed on the upper surface in the D1 direction is epitaxially grown on the single crystal first substrate 10. Therefore, lattice defects can be reduced in the portion (semiconductor portion: first substrate 10 and epitaxial layer 20) exhibiting the properties of the semiconductor. Particularly in this example, since the first substrate 10 and the epitaxial layer 20 are made of the same material, lattice defects can be particularly reduced.
- the epitaxial layer 20 can have an oxygen concentration and an impurity concentration lower than those of a bulk substrate formed by the CZ method or the like. Thereby, when forming a semiconductor element using the composite substrate 50, the electrical resistance of the epitaxial layer 20 serving as a functional layer can be increased, and the concentration of impurities that can cause defects such as OSF can be decreased.
- the oxide layer 30 is disposed on the surface of the epitaxial layer 20 on the D1 direction side, the oxide layer 30 functions as a passivation film. For this reason, when forming a semiconductor element using the composite substrate 50, the interface state of the epitaxial layer 20 which becomes a functional layer can be stabilized.
- the flatness of the upper surface of the epitaxial layer 20 in the D1 direction can be improved as compared with the upper surface of the first substrate 10 in the D1 direction.
- the flatness in the D1 direction of the oxide layer 30 on the epitaxial layer 20 can also be improved. Therefore, when the oxide layer 30 and the second substrate 40 are bonded to each other at room temperature, a required bonding can be performed with a small pressure. Strength can be obtained.
- the oxide layer 30 and the second substrate 40 are made of the same material system, the bonding strength between the structure disposed on the first substrate 10 and the second substrate 40 can be increased.
- the oxide layer 30 is aluminum oxide, the composite substrate 50 having excellent heat dissipation can be obtained.
- the oxide layer 30 formed by the ALD method is generally an amorphous layer. That is, the composite substrate 50 has a configuration in which an amorphous layer exists between the first substrate 10 and the epitaxial layer 20 made of a single crystal and the second substrate 40 made of a single crystal. With such a configuration, when the surfaces of the oxide layer 30 and the second substrate 40 are activated, even if impurities present in the atmosphere in the bonding apparatus adhere to the activated surface, the amorphous layer 30 is amorphous. Diffusion of impurity atoms toward the epitaxial layer 20 can be suppressed by the oxide layer 30. Furthermore, by the same mechanism, it is possible to suppress diffusion of trace impurities such as metal elements contained in the second substrate 40 toward the epitaxial layer 2 side.
- the oxide layer 30 is formed by the ALD method, a negative interface state can be formed at the interface between the epitaxial layer 20 and the oxide layer 30. Thereby, even when a metal impurity atom exists, the electric charge resulting from this impurity atom can be fixed to the interface.
- oxygen atoms are supplied to the surface of the epitaxial layer 20A disposed on the upper surface in the D1 direction of the first substrate 10A. More specifically, oxygen radicals generated from H 2 O containing oxygen atoms or oxygen gas are supplied. Thereby, OH groups are formed on the surface of the epitaxial layer 20A.
- H 2 O oxygen radicals generated from H 2 O containing oxygen atoms or oxygen gas
- TMA containing a metal atom is supplied.
- TMA is molecularly adsorbed to OH groups formed on the surface of the epitaxial layer 20A in the D1 direction. Thereby, aluminum couple
- an inert gas is supplied to remove excess H 2 O molecules and separated methyl molecules.
- an oxide layer in which metal atoms (Al in this example) and oxygen atoms are alternately arranged one by one in layers. 30A is formed. Note that the desired thickness can be controlled by the number of repetitions of supplying oxygen atoms, inert gas, metal atoms, and inert gas.
- the oxide layer 30A is an example in which the above steps are repeated twice, and oxygen atom arrangement layers (31a, 31b) and metal atom arrangement layers (32a, 32b) are alternately laminated.
- the oxide layer 30A By forming the oxide layer 30A in this way, oxygen atoms are arranged on the surface of the oxide layer 30A on the epitaxial layer 20A side. That is, there is an oxygen atom arrangement layer 31a in which oxygen atoms are arranged. In other words, a region having a higher oxygen concentration than the average oxygen concentration of the entire oxide layer 30A exists on the epitaxial layer 20A side of the oxide layer 30A. Thereby, when the 2nd board
- an Al atom arrangement layer 32b in which metal atoms (Al) are arranged is present on the outermost surface in the D1 direction of the oxide layer 30A.
- a region having a higher Al concentration than the average Al concentration of the entire oxide layer 30A exists on the upper surface side of the oxide layer 30A.
- metal atoms (Al) are arranged on the uppermost surface of the second substrate 40A.
- the ratio can be further increased.
- the structure formed on the first substrate 10A in an inert gas without exposing it to the atmosphere in the steps from the oxide layer forming step to the bonding step.
- a step of thinning a portion (first substrate 10, 10A, epitaxial film 20, 20A) showing the properties of the semiconductor may be added.
- the process of thinning will be described using the first embodiment.
- various methods such as abrasive polishing, chemical etching, and ion beam etching can be employed, and a plurality of methods may be combined.
- abrasive polishing chemical etching
- ion beam etching ion beam etching
- p-type or n-type silicon is adopted as the first substrate 10, and p ++ and n ++ with relatively high concentrations and p + and n + with medium concentrations are adopted as dopant concentrations.
- the p ++ dopant concentration include a range of 1 ⁇ 10 18 to 1 ⁇ 10 21 [atoms / cm 3 ].
- the p + dopant concentration include a range of 1 ⁇ 10 16 or more and less than 1 ⁇ 10 18 [atoms / cm 3 ].
- the n ++ dopant concentration include a range of 5 ⁇ 10 17 or more and 1 ⁇ 10 21 [atoms / cm 3 ] or less.
- n + dopant concentration examples include a range of 5 ⁇ 10 15 or more and less than 5 ⁇ 10 17 [atoms / cm 3 ].
- a p-type substrate having a dopant concentration of p ++ is employed as the first substrate. Note that “++” and “+” written in the upper right of “p” and “n” are based on the resistance value of silicon.
- Si is epitaxially grown on the upper surface of the first substrate 10 on the arrow D1 direction (first direction) side to form an epitaxial layer (semiconductor layer) 20.
- the epitaxial layer 20 p-type or n-type silicon and having a smaller amount of dopant than the first substrate 10 can be employed.
- the epitaxial layer 20 is formed so that the dopant concentration gradually decreases from the first substrate 10 side toward the upper surface side.
- the upper surface portion of the epitaxial layer 20 is formed to have any one of a relatively low concentration of p ⁇ and n ⁇ dopants and non-doped.
- Examples of the p ⁇ dopant concentration include a range of less than 1 ⁇ 10 16 [atoms / cm 3 ].
- Examples of the n ⁇ dopant concentration include a range of less than 5 ⁇ 10 15 [atoms / cm 3 ].
- What is referred to as “non-doped silicon” herein is silicon that is simply not doped with the intention of impurities, and is not limited to intrinsic silicon that does not contain impurities.
- the epitaxial layer 20 of the present embodiment employs p-type silicon and is formed so that the dopant concentration of the upper surface portion is p ⁇ . Note that the description of “ ⁇ ” in the upper right of “p” and “n” is based on the resistance value of silicon.
- the dopant concentration of the epitaxial layer 20 can be controlled by adjusting the supply amount of impurities during epitaxial growth. By making this impurity supply zero, non-doped silicon can be formed. Further, the dopant concentration may be gradually changed by reducing the diffusion of the dopant generated during the epitaxial growth.
- the epitaxial layer 20 may not be epitaxially grown until the diffusion concentration of the dopant is saturated.
- the formed epitaxial layer is composed of only a transition region in which the dopant concentration gradually changes from the lower surface.
- the oxide layer 30 is formed on the epitaxial layer 20, and the second substrate 40 is bonded to the upper surface of the oxide layer 30 to form the composite substrate 50.
- the composite substrate 50 is processed from the arrow D2 direction side to reduce the thickness of the first substrate 10 as shown in FIG.
- various methods such as abrasive polishing, chemical etching, and ion beam etching can be employed, and a plurality of methods may be combined.
- the first substrate having a reduced thickness is referred to as a first thin substrate 11.
- etching is performed with an etching solution to reduce the thickness of the epitaxial layer 20 as shown in FIG.
- This etching can be performed by employing a selective etching solution in which the etching rate varies greatly depending on the difference in dopant concentration.
- the selective etching solution include a mixed solution of hydrofluoric acid, nitric acid, and acetic acid, and a mixed solution of hydrofluoric acid, nitric acid, and water.
- a mixed solution of hydrofluoric acid, nitric acid, and acetic acid is employed as an etching solution.
- this etching solution is adjusted so that the etching rate is remarkably reduced at a dopant concentration of 7 ⁇ 10 17 to 2 ⁇ 10 18 [ atoms / cm 3 ] as a boundary.
- Other methods for selective etching include an electric field etching method in about 5% hydrogen fluoride solution, a pulse electrode anodizing method in KOH solution, and the like.
- the epitaxial layer 20 is etched halfway through the transition region where the dopant concentration is gradually changing.
- the epitaxial layer whose thickness is reduced by etching is referred to as a functional layer 21.
- the thickness of the functional layer 21 include a range of about several hundred nm to 2 ⁇ m. If the first substrate 10 or the first thin substrate 11 remains, the remaining first substrate 10 or the first thin substrate 11 is also etched.
- the composite substrate 50 ′ in which the functional layer 21 is laminated above the second substrate 40 in the direction of the arrow D 2 as shown in FIG. 5 can be manufactured.
- the functional layer 21 is bonded to the upper surface of the second substrate 40 in the direction of the arrow D ⁇ b> 2 via the oxide layer 30.
- the dopant concentration of the functional layer 21 is thinner on the bonding side than on the surface side. Further, when the dopant concentration is considered as the magnitude of electric resistance, the electric resistance of the functional layer 21 decreases as it approaches the bonding side from the surface side.
- a gradient of the dopant concentration of the epitaxial layer 20 to be the functional layer 21 is formed on the surface to be bonded to the second substrate 40.
- a silicon wafer is generally said to have a thickness variation of ⁇ 10 [ ⁇ m]. This variation in thickness is very large compared to a value of several tens of nanometers to several hundreds of nanometers, which is a thickness required for silicon of an SOS substrate.
- the composite substrate 50 ′ may be precisely polished. By this precise polishing, the thickness uniformity of the functional layer 21 can be improved.
- the etching means used for this precise etching include dry etching. This dry etching includes a chemical reaction and a physical collision. Examples of utilizing chemical reactions include reactive gases (gas), ions and ion beams, and those utilizing radicals. Examples of the etching gas used for the reactive ions include sulfur hexafluoride (SF 6 ) and carbon tetrafluoride (CF 4 ). Moreover, what uses an ion beam is mentioned as a thing by physical collision. One using this ion beam includes a method using a gas cluster ion beam (GCIB). By scanning the composite substrate 50 ′ with a movable stage while etching a narrow region using these etching means, fine etching can be performed satisfactorily even for a large-area material substrate.
- GCIB gas cluster ion beam
- the thickness of the first substrate 10 is reduced by polishing, but this polishing process may be omitted.
- the polishing step is omitted, the first substrate 10 is removed by etching or the like.
- the oxide layer 30 is formed on the epitaxial layer 20 has been described.
- the oxide layer 30A may be formed.
- the step of cleaning the substrate or the like is not specified, but the substrate may be cleaned as necessary.
- the substrate cleaning method include various methods such as cleaning using ultrasonic waves, cleaning using an organic solvent, cleaning using chemicals, and cleaning using O 2 ashing. These cleaning methods may be employed in combination.
- the epitaxial layer 20 and the oxide layer 30 are formed on the first substrate 10 in this order, but the ALD method is used between the semiconductor substrate composed of the first substrate 10 and the epitaxial layer 20 and the second substrate. It is important that the oxide layer 30 formed in is present. For this reason, the epitaxial layer 20 may be omitted.
- the formation method of the oxide layer 30 can be estimated by analyzing the impurity concentration, crystal state, and the like of the oxide layer 30 by D-SIMS, TOF-SIMS, Rutherford backscattering (RBS), and the like. it can.
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Abstract
Description
(エピタキシャル層形成工程)
まず、図1(a)に示すように、半導体材料からなる第1基板10を準備する。半導体材料としては、Si,GaAs,GaP,GaN等、半導体の性質を有するものであれば特に限定されないが、この例では、シリコン(Si)で形成された場合を例に説明する。この第1基板10のシリコンとしては、p型またはn型のシリコンが採用できる。この第1基板10のドーパント濃度は、自由に設定できる。
次に、図1(c)に示すように、エピタキシャル層20の矢印D1方向(第1方向)の上面にALD(Atomic Layer Deposition)法によって酸化物層30を形成する。酸化物材料としては、種々の材料を用いることができるが、この例では、酸化アルミニウム(AlOx)とする。より具体的には、アルミニウムを原料としたトリメチルアルミニウム(TMA)と、H2Oガスまたは酸素ガスから発生させたラジカル酸素とを交互に基板表面に流し、各ガスの間には、Ar等の不活性ガスでパージすることで酸化物層30を形成する。この成膜は約0.1nm/一原子層形成サイクルで形成し、1サイクルにかかる時間は数秒程度である。酸化物層30の厚みは約50nmとすればよいが、タクトタイムの関係から、100nm以下で形成するとよい。
次に、図1(d)に示すように、絶縁性材料からなる第2基板40を準備する。この第2基板40の形成材料としては、酸化アルミニウム単結晶(サファイア)、炭化シリコンなどを用いることができる。本実施形態では、第2基板40としてサファイアを採用する。サファイアの結晶面は特に限定されないが、R面を用いることが好ましい。R面を用いることにより、エピタキシャル層20を構成するSiとの格子定数を近付けることができる。また、R面を用いることにより、スピネル型のγアルミナとすることができる。その場合には、最表面を占めるAl原子の割合を高くすることができる。
次に、本発明の第2の実施形態について図2,図3を用いて説明する。第2の実施形態は、第1の実施形態とは酸化物層形成工程が異なる。以下、異なる部分を説明する。
上述の実施形態の複合基板50,50Aにおいて、半導体の性質を示す部位(第1基板10,10A,エピタキシャル膜20,20A)を薄層化する工程を追加してもよい。
11・・・第1薄基板
20・・・エピタキシャル層
21・・・機能層
30・・・酸化物層
40・・・第2基板
50・・・複合基板
Claims (6)
- 半導体材料からなる第1基板上に半導体の性質を有するエピタキシャル層を形成するエピタキシャル層形成工程と、
前記エピタキシャル層上に、ALD(Atomic Layer Deposition)法によって酸化物層を形成する酸化物層形成工程と、
前記酸化物層に絶縁性材料から成る第2基板を貼り合わせて複合基板を得る接合工程とを有する複合基板の製造方法。 - 前記酸化物層形成工程は、ALD法により、酸素原子および金属原子を順に繰り返し供給し、金属原子を供給して終了して前記酸化物層を形成する、請求項1記載の複合基板の製造方法。
- 前記第1基板を構成する半導体材料をシリコンとし、前記第2基板を構成する絶縁性材料をサファイアとし、前記エピタキシャル層を構成する材料をシリコンとし、前記酸化物層を構成する材料を酸化アルミニウムとする、請求項1記載の複合基板の製造方法。
- 半導体材料からなる第1基板と絶縁性材料からなる第2基板との間に、該第2基板側から順に酸化物層と半導体の性質を有するエピタキシャル層とが配置され、前記酸化物層の前記エピタキシャル層側には酸素原子が並んでいる複合基板。
- 前記酸化物層はアモルファス層である、請求項4記載の複合基板。
- 前記第1基板および前記エピタキシャル層は、シリコンを主成分とし、前記酸化物層および前記第2基板は、酸化アルミニウムを主成分とする、請求項4記載の複合基板。
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JP2014154687A (ja) * | 2013-02-07 | 2014-08-25 | Kyocera Corp | 複合基板 |
EP2800155A1 (en) * | 2013-04-30 | 2014-11-05 | Nichia Corporation | Method for manufacturing light emitting device |
WO2014192873A1 (ja) * | 2013-05-31 | 2014-12-04 | 京セラ株式会社 | 複合基板およびその製造方法 |
WO2017054613A1 (zh) * | 2015-09-29 | 2017-04-06 | 厦门市三安光电科技有限公司 | 一种半导体元件及其制备方法 |
WO2022230553A1 (ja) * | 2021-04-28 | 2022-11-03 | 日本電産マシンツール株式会社 | 半導体装置の製造方法、及び常温接合装置 |
WO2023090019A1 (ja) * | 2021-11-17 | 2023-05-25 | 信越半導体株式会社 | 窒化物半導体基板及び窒化物半導体基板の製造方法 |
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US9287353B2 (en) * | 2010-11-30 | 2016-03-15 | Kyocera Corporation | Composite substrate and method of manufacturing the same |
US8735219B2 (en) | 2012-08-30 | 2014-05-27 | Ziptronix, Inc. | Heterogeneous annealing method and device |
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KR20230003471A (ko) | 2020-03-19 | 2023-01-06 | 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 | 직접 결합된 구조체들을 위한 치수 보상 제어 |
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