DE69429951T2 - Herstellungsverfahren für Halbleiteranordnung unter Verwendung der selektiven CVD-Methode - Google Patents

Herstellungsverfahren für Halbleiteranordnung unter Verwendung der selektiven CVD-Methode

Info

Publication number
DE69429951T2
DE69429951T2 DE69429951T DE69429951T DE69429951T2 DE 69429951 T2 DE69429951 T2 DE 69429951T2 DE 69429951 T DE69429951 T DE 69429951T DE 69429951 T DE69429951 T DE 69429951T DE 69429951 T2 DE69429951 T2 DE 69429951T2
Authority
DE
Germany
Prior art keywords
semiconductor device
manufacturing process
cvd method
selective cvd
selective
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69429951T
Other languages
English (en)
Other versions
DE69429951D1 (de
Inventor
Yoichi Ohshima
Hideaki Aochi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69429951D1 publication Critical patent/DE69429951D1/de
Publication of DE69429951T2 publication Critical patent/DE69429951T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
DE69429951T 1993-07-09 1994-07-01 Herstellungsverfahren für Halbleiteranordnung unter Verwendung der selektiven CVD-Methode Expired - Fee Related DE69429951T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17006893A JP3219909B2 (ja) 1993-07-09 1993-07-09 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE69429951D1 DE69429951D1 (de) 2002-04-04
DE69429951T2 true DE69429951T2 (de) 2002-10-10

Family

ID=15898044

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69429951T Expired - Fee Related DE69429951T2 (de) 1993-07-09 1994-07-01 Herstellungsverfahren für Halbleiteranordnung unter Verwendung der selektiven CVD-Methode

Country Status (5)

Country Link
US (2) US5476814A (de)
EP (1) EP0634788B1 (de)
JP (1) JP3219909B2 (de)
KR (1) KR0169282B1 (de)
DE (1) DE69429951T2 (de)

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DE4410947C1 (de) * 1994-03-29 1995-06-01 Siemens Ag Halbleiterbauelement für vertikale Integration und Herstellungsverfahren
EP0690494B1 (de) * 1994-06-27 2004-03-17 Infineon Technologies AG Verbindungs- und Aufbautechnik für Multichip-Module
JP3397505B2 (ja) * 1995-04-19 2003-04-14 株式会社東芝 半導体装置の製造方法
US5639691A (en) * 1995-06-05 1997-06-17 Advanced Micro Devices, Inc. Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device
US5710078A (en) * 1996-06-03 1998-01-20 Vanguard International Semiconductor Corporation Method to improve the contact resistance of bit line metal structures to underlying polycide structures
US5811350A (en) * 1996-08-22 1998-09-22 Micron Technology, Inc. Method of forming contact openings and an electronic component formed from the same and other methods
US6893980B1 (en) * 1996-12-03 2005-05-17 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method therefor
KR100430687B1 (ko) * 1996-12-31 2004-08-02 주식회사 하이닉스반도체 반도체소자의금속배선형성방법
JP2988413B2 (ja) * 1997-02-20 1999-12-13 日本電気株式会社 半導体装置及びその製造方法
US6027973A (en) * 1997-12-09 2000-02-22 Advanced Micro Devices Oxidation and etchback process for forming thick contact area on polysilicon layer in microelectronic structure
US6150691A (en) * 1997-12-19 2000-11-21 Micron Technology, Inc. Spacer patterned, high dielectric constant capacitor
US6025254A (en) * 1997-12-23 2000-02-15 Intel Corporation Low resistance gate electrode layer and method of making same
JPH11214504A (ja) * 1998-01-26 1999-08-06 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP3199015B2 (ja) * 1998-02-04 2001-08-13 日本電気株式会社 半導体装置及びその製造方法
JP3186040B2 (ja) * 1998-06-01 2001-07-11 日本電気株式会社 半導体装置の製造方法
US6261948B1 (en) 1998-07-31 2001-07-17 Micron Technology, Inc. Method of forming contact openings
US6380023B2 (en) * 1998-09-02 2002-04-30 Micron Technology, Inc. Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and integrated circuits
US6762479B2 (en) * 1998-11-06 2004-07-13 International Business Machines Corporation Microwave array transistor for low-noise and high-power applications
US6261950B1 (en) * 1999-10-18 2001-07-17 Infineon Technologies Ag Self-aligned metal caps for interlevel metal connections
US6261935B1 (en) 1999-12-13 2001-07-17 Chartered Semiconductor Manufacturing Ltd. Method of forming contact to polysilicon gate for MOS devices
JP4703364B2 (ja) 2005-10-24 2011-06-15 株式会社東芝 半導体装置及びその製造方法
US20070141798A1 (en) * 2005-12-20 2007-06-21 Intel Corporation Silicide layers in contacts for high-k/metal gate transistors
US8241944B2 (en) 2010-07-02 2012-08-14 Micron Technology, Inc. Resistive RAM devices and methods
US20160276156A1 (en) * 2015-03-16 2016-09-22 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing process thereof
US11094795B2 (en) 2018-11-20 2021-08-17 Nanya Technology Corporation Semiconductor device and method for manufacturing the same
CN113316840A (zh) * 2019-03-28 2021-08-27 东京毅力科创株式会社 半导体装置的制造方法
JP6793867B1 (ja) 2020-06-29 2020-12-02 株式会社ハーモニック・ドライブ・システムズ 波動歯車装置ユニット
US20230101107A1 (en) * 2021-09-24 2023-03-30 Intel Corporation Simultaneous filling of variable aspect ratio single damascene contact to gate and trench vias with low resistance barrierless selective metallization

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4622735A (en) * 1980-12-12 1986-11-18 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing a semiconductor device utilizing self-aligned silicide regions
US5324536A (en) * 1986-04-28 1994-06-28 Canon Kabushiki Kaisha Method of forming a multilayered structure
US4902533A (en) * 1987-06-19 1990-02-20 Motorola, Inc. Method for selectively depositing tungsten on a substrate by using a spin-on metal oxide
US4966868A (en) * 1988-05-16 1990-10-30 Intel Corporation Process for selective contact hole filling including a silicide plug
JPH02151034A (ja) * 1988-12-01 1990-06-11 Toshiba Corp 半導体装置の製造方法
JPH02272747A (ja) * 1989-04-14 1990-11-07 Sony Corp 配線の形成方法
JP2897248B2 (ja) * 1989-04-18 1999-05-31 富士通株式会社 半導体装置の製造方法
JP2660072B2 (ja) * 1989-11-10 1997-10-08 株式会社東芝 コンタクトの形成方法
JP2892421B2 (ja) * 1990-02-27 1999-05-17 沖電気工業株式会社 半導体素子の製造方法
MY109605A (en) * 1990-06-29 1997-03-31 Canon Kk Method for producing semiconductor device having alignment mark.
US5023201A (en) * 1990-08-30 1991-06-11 Cornell Research Foundation, Inc. Selective deposition of tungsten on TiSi2
JP3175188B2 (ja) * 1991-05-10 2001-06-11 ソニー株式会社 位置合わせマークの形成方法
US5204286A (en) * 1991-10-15 1993-04-20 Micron Technology, Inc. Method of making self-aligned contacts and vertical interconnects to integrated circuits
JP2586365B2 (ja) * 1991-12-20 1997-02-26 株式会社日立製作所 洗たく機の排水制御装置
JPH05234940A (ja) * 1992-02-24 1993-09-10 Nec Corp 選択埋め込み成長方法

Also Published As

Publication number Publication date
KR950004416A (ko) 1995-02-18
US5763321A (en) 1998-06-09
EP0634788A3 (de) 1995-11-02
US5476814A (en) 1995-12-19
EP0634788B1 (de) 2002-02-27
KR0169282B1 (ko) 1999-02-01
JP3219909B2 (ja) 2001-10-15
EP0634788A2 (de) 1995-01-18
DE69429951D1 (de) 2002-04-04
JPH0729854A (ja) 1995-01-31

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee