DE69600261D1 - Herstellungsmethode für Halbleiterbauelement mit Salizid-Bereich - Google Patents
Herstellungsmethode für Halbleiterbauelement mit Salizid-BereichInfo
- Publication number
- DE69600261D1 DE69600261D1 DE69600261T DE69600261T DE69600261D1 DE 69600261 D1 DE69600261 D1 DE 69600261D1 DE 69600261 T DE69600261 T DE 69600261T DE 69600261 T DE69600261 T DE 69600261T DE 69600261 D1 DE69600261 D1 DE 69600261D1
- Authority
- DE
- Germany
- Prior art keywords
- salicide
- manufacturing
- range
- semiconductor device
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/97—Specified etch stop material
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7049037A JP2842284B2 (ja) | 1995-02-14 | 1995-02-14 | 半導体装置の製造方法 |
JP7129771A JP2827962B2 (ja) | 1995-04-28 | 1995-04-28 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69600261D1 true DE69600261D1 (de) | 1998-06-04 |
DE69600261T2 DE69600261T2 (de) | 1998-10-15 |
Family
ID=26389393
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69600261T Expired - Fee Related DE69600261T2 (de) | 1995-02-14 | 1996-02-14 | Herstellungsmethode für Halbleiterbauelement mit Salizid-Bereich |
Country Status (4)
Country | Link |
---|---|
US (1) | US5656519A (de) |
EP (1) | EP0727815B1 (de) |
KR (1) | KR100223729B1 (de) |
DE (1) | DE69600261T2 (de) |
Families Citing this family (73)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2792467B2 (ja) * | 1995-06-13 | 1998-09-03 | 日本電気株式会社 | 半導体装置の製造方法 |
TW304278B (en) * | 1996-09-17 | 1997-05-01 | Nat Science Council | The source-drain distributed implantation method |
US5923999A (en) * | 1996-10-29 | 1999-07-13 | International Business Machines Corporation | Method of controlling dopant diffusion and metal contamination in thin polycide gate conductor of mosfet device |
JPH10223889A (ja) * | 1997-02-04 | 1998-08-21 | Mitsubishi Electric Corp | Misトランジスタおよびその製造方法 |
US5930634A (en) * | 1997-04-21 | 1999-07-27 | Advanced Micro Devices, Inc. | Method of making an IGFET with a multilevel gate |
US6074921A (en) * | 1997-06-30 | 2000-06-13 | Vlsi Technology, Inc. | Self-aligned processing of semiconductor device features |
US6261887B1 (en) | 1997-08-28 | 2001-07-17 | Texas Instruments Incorporated | Transistors with independently formed gate structures and method |
KR100268871B1 (ko) * | 1997-09-26 | 2000-10-16 | 김영환 | 반도체소자의제조방법 |
JPH11135745A (ja) | 1997-10-29 | 1999-05-21 | Toshiba Corp | 半導体装置及びその製造方法 |
US6048784A (en) * | 1997-12-17 | 2000-04-11 | Texas Instruments Incorporated | Transistor having an improved salicided gate and method of construction |
US6083836A (en) * | 1997-12-23 | 2000-07-04 | Texas Instruments Incorporated | Transistors with substitutionally formed gate structures and method |
US6274421B1 (en) | 1998-01-09 | 2001-08-14 | Sharp Laboratories Of America, Inc. | Method of making metal gate sub-micron MOS transistor |
KR19990065891A (ko) * | 1998-01-19 | 1999-08-05 | 구본준 | 통합 반도체 소자의 제조방법 |
US6118163A (en) * | 1998-02-04 | 2000-09-12 | Advanced Micro Devices, Inc. | Transistor with integrated poly/metal gate electrode |
US6147405A (en) | 1998-02-19 | 2000-11-14 | Micron Technology, Inc. | Asymmetric, double-sided self-aligned silicide and method of forming the same |
US6133106A (en) * | 1998-02-23 | 2000-10-17 | Sharp Laboratories Of America, Inc. | Fabrication of a planar MOSFET with raised source/drain by chemical mechanical polishing and nitride replacement |
US6136636A (en) * | 1998-03-25 | 2000-10-24 | Texas Instruments - Acer Incorporated | Method of manufacturing deep sub-micron CMOS transistors |
US5930617A (en) * | 1998-03-25 | 1999-07-27 | Texas Instruments-Acer Incorporated | Method of forming deep sub-micron CMOS transistors with self-aligned silicided contact and extended S/D junction |
US6649308B1 (en) * | 1998-03-30 | 2003-11-18 | Texas Instruments-Acer Incorporated | Ultra-short channel NMOSFETS with self-aligned silicide contact |
US5956584A (en) * | 1998-03-30 | 1999-09-21 | Texas Instruments - Acer Incorporated | Method of making self-aligned silicide CMOS transistors |
US6090653A (en) * | 1998-03-30 | 2000-07-18 | Texas Instruments | Method of manufacturing CMOS transistors |
TW372349B (en) * | 1998-06-08 | 1999-10-21 | United Microelectronics Corp | Bridge prevention method for self-aligned metal silicide |
US6265256B1 (en) * | 1998-09-17 | 2001-07-24 | Advanced Micro Devices, Inc. | MOS transistor with minimal overlap between gate and source/drain extensions |
US6265252B1 (en) | 1999-05-03 | 2001-07-24 | Vlsi Technology, Inc. | Reducing the formation of electrical leakage pathways during manufacture of an electronic device |
US6194299B1 (en) * | 1999-06-03 | 2001-02-27 | Advanced Micro Devices, Inc. | Method for fabrication of a low resistivity MOSFET gate with thick metal on polysilicon |
US6251732B1 (en) * | 1999-08-10 | 2001-06-26 | Macronix International Co., Ltd. | Method and apparatus for forming self-aligned code structures for semi conductor devices |
US6297109B1 (en) * | 1999-08-19 | 2001-10-02 | Chartered Semiconductor Manufacturing Ltd. | Method to form shallow junction transistors while eliminating shorts due to junction spiking |
US6200886B1 (en) * | 1999-10-28 | 2001-03-13 | United Silicon Incorporated | Fabricating process for polysilicon gate |
US6271106B1 (en) * | 1999-10-29 | 2001-08-07 | Motorola, Inc. | Method of manufacturing a semiconductor component |
JP2001237422A (ja) * | 1999-12-14 | 2001-08-31 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
US6294448B1 (en) | 2000-01-18 | 2001-09-25 | Taiwan Semiconductor Manufacturing Company | Method to improve TiSix salicide formation |
JP2001210726A (ja) * | 2000-01-24 | 2001-08-03 | Hitachi Ltd | 半導体装置及びその製造方法 |
US6294433B1 (en) * | 2000-02-09 | 2001-09-25 | Advanced Micro Devices, Inc. | Gate re-masking for deeper source/drain co-implantation processes |
JP3490046B2 (ja) * | 2000-05-02 | 2004-01-26 | シャープ株式会社 | 半導体装置及びその製造方法 |
US6458678B1 (en) * | 2000-07-25 | 2002-10-01 | Advanced Micro Devices, Inc. | Transistor formed using a dual metal process for gate and source/drain region |
US6664740B2 (en) | 2001-02-01 | 2003-12-16 | The Regents Of The University Of California | Formation of a field reversed configuration for magnetic and electrostatic confinement of plasma |
US6524939B2 (en) | 2001-02-23 | 2003-02-25 | Vanguard International Semiconductor Corporation | Dual salicidation process |
US6528402B2 (en) * | 2001-02-23 | 2003-03-04 | Vanguard International Semiconductor Corporation | Dual salicidation process |
US6611106B2 (en) * | 2001-03-19 | 2003-08-26 | The Regents Of The University Of California | Controlled fusion in a field reversed configuration and direct energy conversion |
US6518154B1 (en) * | 2001-03-21 | 2003-02-11 | Advanced Micro Devices, Inc. | Method of forming semiconductor devices with differently composed metal-based gate electrodes |
US6624043B2 (en) * | 2001-09-24 | 2003-09-23 | Sharp Laboratories Of America, Inc. | Metal gate CMOS and method of manufacturing the same |
DE10208728B4 (de) | 2002-02-28 | 2009-05-07 | Advanced Micro Devices, Inc., Sunnyvale | Ein Verfahren zur Herstellung eines Halbleiterelements mit unterschiedlichen Metallsilizidbereichen |
DE10208904B4 (de) | 2002-02-28 | 2007-03-01 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung unterschiedlicher Silicidbereiche auf verschiedenen Silicium enthaltenden Gebieten in einem Halbleiterelement |
AU2002359813A1 (en) * | 2002-03-01 | 2003-09-16 | Advanced Micro Devices, Inc. | A semiconductor device having different metal-semiconductor portions formed in a semiconductor region and a method for fabricating the semiconductor device |
JP2003297956A (ja) * | 2002-04-04 | 2003-10-17 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
DE10234931A1 (de) | 2002-07-31 | 2004-02-26 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung eines Metallsilizidgates in einer standardmässigen MOS-Prozesssequenz |
US6815235B1 (en) | 2002-11-25 | 2004-11-09 | Advanced Micro Devices, Inc. | Methods of controlling formation of metal silicide regions, and system for performing same |
US7153772B2 (en) | 2003-06-12 | 2006-12-26 | Asm International N.V. | Methods of forming silicide films in semiconductor devices |
US9123512B2 (en) | 2005-03-07 | 2015-09-01 | The Regents Of The Unviersity Of California | RF current drive for plasma electric generation system |
US9607719B2 (en) * | 2005-03-07 | 2017-03-28 | The Regents Of The University Of California | Vacuum chamber for plasma electric generation system |
US8031824B2 (en) | 2005-03-07 | 2011-10-04 | Regents Of The University Of California | Inductive plasma source for plasma electric generation system |
JP5010589B2 (ja) * | 2005-06-16 | 2012-08-29 | アイメック | 半導体デバイス製造方法及びその方法により製造した半導体デバイスを備えた半導体集積回路チップ |
JP2007073760A (ja) * | 2005-09-07 | 2007-03-22 | Matsushita Electric Ind Co Ltd | Mosトランジスタセル及び半導体装置 |
US8278176B2 (en) | 2006-06-07 | 2012-10-02 | Asm America, Inc. | Selective epitaxial formation of semiconductor films |
US8367548B2 (en) | 2007-03-16 | 2013-02-05 | Asm America, Inc. | Stable silicide films and methods for making the same |
JP2009076731A (ja) * | 2007-09-21 | 2009-04-09 | Renesas Technology Corp | 半導体装置およびその製造方法 |
CN101752314B (zh) * | 2008-12-04 | 2012-10-03 | 上海华虹Nec电子有限公司 | 具有自对准接触孔的表面沟道pmos器件及制作方法 |
CN101752313B (zh) * | 2008-12-04 | 2012-10-03 | 上海华虹Nec电子有限公司 | 一种具有自对准接触孔的表面沟道pmos器件及制作方法 |
US7927942B2 (en) | 2008-12-19 | 2011-04-19 | Asm International N.V. | Selective silicide process |
US9379011B2 (en) | 2008-12-19 | 2016-06-28 | Asm International N.V. | Methods for depositing nickel films and for making nickel silicide and nickel germanide |
US8367528B2 (en) | 2009-11-17 | 2013-02-05 | Asm America, Inc. | Cyclical epitaxial deposition and etch |
US8871617B2 (en) | 2011-04-22 | 2014-10-28 | Asm Ip Holding B.V. | Deposition and reduction of mixed metal oxide thin films |
US8809170B2 (en) | 2011-05-19 | 2014-08-19 | Asm America Inc. | High throughput cyclical epitaxial deposition and etch process |
RS56260B1 (sr) | 2011-11-14 | 2017-11-30 | Univ California | Sistem za formiranje i održavanje frc visokih performansi |
JP6876435B2 (ja) | 2013-09-24 | 2021-05-26 | ティーエーイー テクノロジーズ, インコーポレイテッド | 高性能frcを形成し維持するシステムおよび方法 |
PT3633683T (pt) | 2014-10-13 | 2021-06-03 | Tae Tech Inc | Processo de fusão e compressão de toros compactos |
JP6855374B2 (ja) | 2014-10-30 | 2021-04-07 | ティーエーイー テクノロジーズ, インコーポレイテッド | 高性能frcを形成し維持するシステムおよび方法 |
KR102598740B1 (ko) | 2015-05-12 | 2023-11-03 | 티에이이 테크놀로지스, 인크. | 원하지 않는 맴돌이 전류를 감소시키는 시스템 및 방법 |
US9607842B1 (en) | 2015-10-02 | 2017-03-28 | Asm Ip Holding B.V. | Methods of forming metal silicides |
IL259313B2 (en) | 2015-11-13 | 2023-11-01 | Tae Tech Inc | Systems and methods for positioning stability of FRC plasma |
UA128079C2 (uk) | 2016-10-28 | 2024-04-03 | Тае Текнолоджіз, Інк. | Системи і способи поліпшеної підтримки підвищених енергій високоефективної конфігурації з оберненим полем, що передбачають використання інжекторів нейтральних пучків з настроюваними енергіями пучків |
AU2017355652B2 (en) | 2016-11-04 | 2022-12-15 | Tae Technologies, Inc. | Systems and methods for improved sustainment of a high performance FRC with multi-scaled capture type vacuum pumping |
UA126673C2 (uk) | 2016-11-15 | 2023-01-11 | Тае Текнолоджіз, Інк. | Системи і способи поліпшеної підтримки високоефективної конфігурації з оберненим полем і нагрівання електронів за допомогою вищих гармонік швидких хвиль у високоефективній конфігурації з оберненим полем |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2537936B2 (ja) * | 1986-04-23 | 1996-09-25 | エイ・ティ・アンド・ティ・コーポレーション | 半導体デバイスの製作プロセス |
CA1306072C (en) * | 1987-03-30 | 1992-08-04 | John E. Cronin | Refractory metal - titanium nitride conductive structures and processes for forming the same |
JPH0227737A (ja) * | 1988-07-15 | 1990-01-30 | Nec Corp | 半導体装置の製造方法 |
US4998150A (en) * | 1988-12-22 | 1991-03-05 | Texas Instruments Incorporated | Raised source/drain transistor |
JP2793248B2 (ja) * | 1989-04-28 | 1998-09-03 | 日本電気株式会社 | 半導体・素子構造の製造方法 |
US4948745A (en) * | 1989-05-22 | 1990-08-14 | Motorola, Inc. | Process for elevated source/drain field effect structure |
JPH03288443A (ja) * | 1990-04-04 | 1991-12-18 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
US5164333A (en) * | 1990-06-19 | 1992-11-17 | Siemens Aktiengesellschaft | Method for manufacturing a multi-layer gate electrode for a mos transistor |
US5168072A (en) * | 1990-10-12 | 1992-12-01 | Texas Instruments Incorporated | Method of fabricating an high-performance insulated-gate field-effect transistor |
US5322809A (en) * | 1993-05-11 | 1994-06-21 | Texas Instruments Incorporated | Self-aligned silicide process |
-
1996
- 1996-02-13 US US08/600,532 patent/US5656519A/en not_active Expired - Fee Related
- 1996-02-14 EP EP96102174A patent/EP0727815B1/de not_active Expired - Lifetime
- 1996-02-14 DE DE69600261T patent/DE69600261T2/de not_active Expired - Fee Related
- 1996-02-14 KR KR1019960003510A patent/KR100223729B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
DE69600261T2 (de) | 1998-10-15 |
EP0727815A2 (de) | 1996-08-21 |
US5656519A (en) | 1997-08-12 |
EP0727815A3 (de) | 1996-09-25 |
KR100223729B1 (ko) | 1999-10-15 |
EP0727815B1 (de) | 1998-04-29 |
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