DE10123514B4 - Halbleiter-Speicherbaustein - Google Patents

Halbleiter-Speicherbaustein Download PDF

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Publication number
DE10123514B4
DE10123514B4 DE10123514A DE10123514A DE10123514B4 DE 10123514 B4 DE10123514 B4 DE 10123514B4 DE 10123514 A DE10123514 A DE 10123514A DE 10123514 A DE10123514 A DE 10123514A DE 10123514 B4 DE10123514 B4 DE 10123514B4
Authority
DE
Germany
Prior art keywords
channel mos
mos transistor
bit line
line
wiring layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE10123514A
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German (de)
English (en)
Other versions
DE10123514A1 (de
Inventor
Koji Nii
Atsushi Miyanishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE10123514A1 publication Critical patent/DE10123514A1/de
Application granted granted Critical
Publication of DE10123514B4 publication Critical patent/DE10123514B4/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE10123514A 2000-05-16 2001-05-15 Halbleiter-Speicherbaustein Expired - Lifetime DE10123514B4 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP143861/00 2000-05-16
JP2000143861 2000-05-16
JP003500/01 2001-01-11
JP2001003500A JP4885365B2 (ja) 2000-05-16 2001-01-11 半導体装置

Publications (2)

Publication Number Publication Date
DE10123514A1 DE10123514A1 (de) 2001-11-22
DE10123514B4 true DE10123514B4 (de) 2005-07-28

Family

ID=26591985

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10123514A Expired - Lifetime DE10123514B4 (de) 2000-05-16 2001-05-15 Halbleiter-Speicherbaustein

Country Status (4)

Country Link
US (2) US6347062B2 (enExample)
JP (1) JP4885365B2 (enExample)
KR (1) KR100419687B1 (enExample)
DE (1) DE10123514B4 (enExample)

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CA2299991A1 (en) * 2000-03-03 2001-09-03 Mosaid Technologies Incorporated A memory cell for embedded memories
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JP2003133529A (ja) * 2001-10-24 2003-05-09 Sony Corp 情報記憶装置およびその製造方法
JP2003152111A (ja) * 2001-11-13 2003-05-23 Mitsubishi Electric Corp 半導体記憶装置
JP2003218238A (ja) * 2001-11-14 2003-07-31 Mitsubishi Electric Corp 半導体記憶装置
US6737685B2 (en) * 2002-01-11 2004-05-18 International Business Machines Corporation Compact SRAM cell layout for implementing one-port or two-port operation
JP4073691B2 (ja) * 2002-03-19 2008-04-09 株式会社ルネサステクノロジ 半導体記憶装置
JP4278338B2 (ja) 2002-04-01 2009-06-10 株式会社ルネサステクノロジ 半導体記憶装置
KR100468780B1 (ko) * 2002-12-18 2005-01-29 삼성전자주식회사 더블 포트 반도체 메모리 장치
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KR100539229B1 (ko) 2003-01-30 2005-12-27 삼성전자주식회사 듀얼 포트 반도체 메모리 장치
JP4416428B2 (ja) 2003-04-30 2010-02-17 株式会社ルネサステクノロジ 半導体記憶装置
JP2005175415A (ja) * 2003-12-05 2005-06-30 Taiwan Semiconductor Manufacturing Co Ltd 集積回路デバイスとその製造方法
JP2005333084A (ja) * 2004-05-21 2005-12-02 Nec Electronics Corp 半導体記憶装置
JPWO2006016403A1 (ja) * 2004-08-10 2008-05-01 富士通株式会社 半導体記憶装置
US7365432B2 (en) * 2004-08-23 2008-04-29 Taiwan Semiconductor Manufacturing Company, Ltd. Memory cell structure
JP2006127737A (ja) * 2004-09-30 2006-05-18 Nscore:Kk 不揮発性メモリ回路
JP4846721B2 (ja) 2005-05-11 2011-12-28 富士通セミコンダクター株式会社 半導体装置とその製造方法
JP4578329B2 (ja) * 2005-06-03 2010-11-10 ルネサスエレクトロニクス株式会社 半導体記憶装置
CN1893084A (zh) * 2005-07-07 2007-01-10 松下电器产业株式会社 半导体装置
US7405994B2 (en) 2005-07-29 2008-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Dual port cell structure
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US7956421B2 (en) * 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US7908578B2 (en) * 2007-08-02 2011-03-15 Tela Innovations, Inc. Methods for designing semiconductor device with dynamic array section
JP5061490B2 (ja) * 2006-04-06 2012-10-31 ソニー株式会社 半導体装置およびその製造方法
US7898894B2 (en) * 2006-04-12 2011-03-01 International Business Machines Corporation Static random access memory (SRAM) cells
US7269056B1 (en) * 2006-04-27 2007-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Power grid design for split-word line style memory cell
US7606057B2 (en) * 2006-05-31 2009-10-20 Arm Limited Metal line layout in a memory cell
JP2008027493A (ja) * 2006-07-19 2008-02-07 Toshiba Corp 半導体記憶装置
JP2008130670A (ja) * 2006-11-17 2008-06-05 Seiko Epson Corp 半導体装置、論理回路および電子機器
US9099172B2 (en) * 2013-01-02 2015-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Dual-port SRAM connection structure
US9424889B1 (en) * 2015-02-04 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-port SRAM device
US7525868B2 (en) * 2006-11-29 2009-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Multiple-port SRAM device
JP2008159669A (ja) * 2006-12-21 2008-07-10 Matsushita Electric Ind Co Ltd 半導体記憶装置
US7839697B2 (en) 2006-12-21 2010-11-23 Panasonic Corporation Semiconductor memory device
US7738282B2 (en) * 2007-02-15 2010-06-15 Taiwan Semiconductor Manufacturing Company, Ltd. Cell structure of dual port SRAM
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
JP2009016809A (ja) * 2007-06-07 2009-01-22 Toshiba Corp 半導体記憶装置
KR100849794B1 (ko) * 2007-07-04 2008-07-31 주식회사 하이닉스반도체 강유전체 소자를 적용한 반도체 메모리 장치
KR100865633B1 (ko) * 2007-07-19 2008-10-27 주식회사 동부하이텍 듀얼 포트 에스램
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
JP2009238332A (ja) 2008-03-27 2009-10-15 Renesas Technology Corp 半導体記憶装置
JP5231924B2 (ja) * 2008-10-03 2013-07-10 株式会社東芝 半導体記憶装置
GB2460049A (en) * 2008-05-13 2009-11-18 Silicon Basis Ltd Reading from an SRAM cell using a read bit line
US7864600B2 (en) * 2008-06-19 2011-01-04 Texas Instruments Incorporated Memory cell employing reduced voltage
KR101739709B1 (ko) 2008-07-16 2017-05-24 텔라 이노베이션스, 인코포레이티드 동적 어레이 아키텍쳐에서의 셀 페이징과 배치를 위한 방법 및 그 구현
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US8009463B2 (en) * 2009-07-31 2011-08-30 Taiwan Semiconductor Manufacturing Co., Ltd. Cell structure for dual port SRAM
US8189368B2 (en) * 2009-07-31 2012-05-29 Taiwan Semiconductor Manufacturing Co., Ltd. Cell structure for dual port SRAM
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
JP5596335B2 (ja) * 2009-12-24 2014-09-24 ルネサスエレクトロニクス株式会社 半導体装置
JP5594294B2 (ja) 2009-12-25 2014-09-24 パナソニック株式会社 半導体装置
US8218354B2 (en) * 2009-12-30 2012-07-10 Taiwan Semicondcutor Manufacturing Co., Ltd. SRAM word-line coupling noise restriction
US9362290B2 (en) * 2010-02-08 2016-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Memory cell layout
US8675397B2 (en) * 2010-06-25 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Cell structure for dual-port SRAM
US8315084B2 (en) * 2010-03-10 2012-11-20 Taiwan Semiconductor Manufacturing Company, Ltd. Fully balanced dual-port memory cell
US8942030B2 (en) 2010-06-25 2015-01-27 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for SRAM cell circuit
CN102243888A (zh) * 2010-05-13 2011-11-16 黄效华 负载平衡的多端口寄存器存储单元
WO2012017535A1 (ja) * 2010-08-05 2012-02-09 ルネサスエレクトロニクス株式会社 半導体装置
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
JP5711033B2 (ja) * 2011-04-12 2015-04-30 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US8576655B2 (en) 2011-06-21 2013-11-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor memories
JP5705053B2 (ja) 2011-07-26 2015-04-22 ルネサスエレクトロニクス株式会社 半導体装置
US10032781B2 (en) 2011-07-29 2018-07-24 Renesas Electronics Corporation Static random access memory device with halo regions having different impurity concentrations
US8406028B1 (en) * 2011-10-31 2013-03-26 Taiwan Semiconductor Manufacturing Co., Ltd. Word line layout for semiconductor memory
US9099199B2 (en) 2012-03-15 2015-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Memory cell and memory array
US9036404B2 (en) 2012-03-30 2015-05-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for SRAM cell structure
JP6151504B2 (ja) * 2012-10-17 2017-06-21 ルネサスエレクトロニクス株式会社 半導体記憶装置
CN105408960B (zh) 2013-08-06 2019-02-15 瑞萨电子株式会社 半导体集成电路器件
US9536596B2 (en) * 2014-08-26 2017-01-03 Qualcomm Incorporated Three-port bit cell having increased width
US9806083B2 (en) 2014-12-03 2017-10-31 Qualcomm Incorporated Static random access memory (SRAM) bit cells with wordlines on separate metal layers for increased performance, and related methods
US9876017B2 (en) * 2014-12-03 2018-01-23 Qualcomm Incorporated Static random access memory (SRAM) bit cells with wordline landing pads split across boundary edges of the SRAM bit cells
US9524972B2 (en) * 2015-02-12 2016-12-20 Qualcomm Incorporated Metal layers for a three-port bit cell
JP6501688B2 (ja) * 2015-09-29 2019-04-17 ルネサスエレクトロニクス株式会社 半導体記憶装置およびそのテスト方法
TWI726869B (zh) 2016-02-24 2021-05-11 聯華電子股份有限公司 靜態隨機存取記憶體的佈局結構及其製作方法
JP2016146504A (ja) * 2016-04-06 2016-08-12 ルネサスエレクトロニクス株式会社 半導体装置および半導体チップ
TWI681542B (zh) * 2016-05-04 2020-01-01 聯華電子股份有限公司 靜態隨機存取記憶體的佈局圖案
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JP6586204B2 (ja) * 2018-08-02 2019-10-02 ルネサスエレクトロニクス株式会社 半導体装置
TWI823896B (zh) * 2019-02-12 2023-12-01 聯華電子股份有限公司 靜態隨機處理記憶體
JP7370730B2 (ja) * 2019-05-14 2023-10-30 ルネサスエレクトロニクス株式会社 半導体記憶装置
CN111129005B (zh) * 2019-12-25 2023-09-19 上海华力集成电路制造有限公司 一种双口静态随机存储单元版图结构
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US5338963A (en) * 1993-04-05 1994-08-16 International Business Machines Corporation Soft error immune CMOS static RAM cell
JPH10178110A (ja) * 1996-12-19 1998-06-30 Toshiba Corp 半導体記憶装置

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JP3771283B2 (ja) 1993-09-29 2006-04-26 株式会社ルネサステクノロジ 半導体集積回路装置
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KR100289386B1 (ko) * 1997-12-27 2001-06-01 김영환 멀티 포트 에스램
KR100502672B1 (ko) * 1998-04-21 2005-10-05 주식회사 하이닉스반도체 풀 씨모스 에스램 셀
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US5325338A (en) * 1991-09-04 1994-06-28 Advanced Micro Devices, Inc. Dual port memory, such as used in color lookup tables for video systems
US5338963A (en) * 1993-04-05 1994-08-16 International Business Machines Corporation Soft error immune CMOS static RAM cell
JPH10178110A (ja) * 1996-12-19 1998-06-30 Toshiba Corp 半導体記憶装置
US5930163A (en) * 1996-12-19 1999-07-27 Kabushiki Kaisha Toshiba Semiconductor memory device having two P-well layout structure

Also Published As

Publication number Publication date
KR100419687B1 (ko) 2004-02-21
JP4885365B2 (ja) 2012-02-29
KR20010106233A (ko) 2001-11-29
JP2002043441A (ja) 2002-02-08
US20010043487A1 (en) 2001-11-22
US20020064080A1 (en) 2002-05-30
US6535453B2 (en) 2003-03-18
US6347062B2 (en) 2002-02-12
DE10123514A1 (de) 2001-11-22

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