KR100419687B1 - 반도체 기억 장치 - Google Patents

반도체 기억 장치 Download PDF

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Publication number
KR100419687B1
KR100419687B1 KR10-2001-0025724A KR20010025724A KR100419687B1 KR 100419687 B1 KR100419687 B1 KR 100419687B1 KR 20010025724 A KR20010025724 A KR 20010025724A KR 100419687 B1 KR100419687 B1 KR 100419687B1
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KR
South Korea
Prior art keywords
channel mos
mos transistor
wiring layer
well
line
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
KR10-2001-0025724A
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English (en)
Korean (ko)
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KR20010106233A (ko
Inventor
니이고지
미야니시아츠시
Original Assignee
미쓰비시덴키 가부시키가이샤
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Application filed by 미쓰비시덴키 가부시키가이샤 filed Critical 미쓰비시덴키 가부시키가이샤
Publication of KR20010106233A publication Critical patent/KR20010106233A/ko
Application granted granted Critical
Publication of KR100419687B1 publication Critical patent/KR100419687B1/ko
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
KR10-2001-0025724A 2000-05-16 2001-05-11 반도체 기억 장치 Expired - Lifetime KR100419687B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2000143861 2000-05-16
JP2000-143861 2000-05-16
JP2001-003500 2001-01-11
JP2001003500A JP4885365B2 (ja) 2000-05-16 2001-01-11 半導体装置

Publications (2)

Publication Number Publication Date
KR20010106233A KR20010106233A (ko) 2001-11-29
KR100419687B1 true KR100419687B1 (ko) 2004-02-21

Family

ID=26591985

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2001-0025724A Expired - Lifetime KR100419687B1 (ko) 2000-05-16 2001-05-11 반도체 기억 장치

Country Status (4)

Country Link
US (2) US6347062B2 (enExample)
JP (1) JP4885365B2 (enExample)
KR (1) KR100419687B1 (enExample)
DE (1) DE10123514B4 (enExample)

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JP2003152111A (ja) * 2001-11-13 2003-05-23 Mitsubishi Electric Corp 半導体記憶装置
JP2003218238A (ja) * 2001-11-14 2003-07-31 Mitsubishi Electric Corp 半導体記憶装置
US6737685B2 (en) * 2002-01-11 2004-05-18 International Business Machines Corporation Compact SRAM cell layout for implementing one-port or two-port operation
JP4073691B2 (ja) * 2002-03-19 2008-04-09 株式会社ルネサステクノロジ 半導体記憶装置
JP4278338B2 (ja) 2002-04-01 2009-06-10 株式会社ルネサステクノロジ 半導体記憶装置
KR100468780B1 (ko) * 2002-12-18 2005-01-29 삼성전자주식회사 더블 포트 반도체 메모리 장치
JP4418153B2 (ja) * 2002-12-27 2010-02-17 株式会社ルネサステクノロジ 半導体装置
KR100539229B1 (ko) 2003-01-30 2005-12-27 삼성전자주식회사 듀얼 포트 반도체 메모리 장치
JP4416428B2 (ja) 2003-04-30 2010-02-17 株式会社ルネサステクノロジ 半導体記憶装置
JP2005175415A (ja) * 2003-12-05 2005-06-30 Taiwan Semiconductor Manufacturing Co Ltd 集積回路デバイスとその製造方法
JP2005333084A (ja) * 2004-05-21 2005-12-02 Nec Electronics Corp 半導体記憶装置
JPWO2006016403A1 (ja) * 2004-08-10 2008-05-01 富士通株式会社 半導体記憶装置
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JP2006127737A (ja) * 2004-09-30 2006-05-18 Nscore:Kk 不揮発性メモリ回路
JP4846721B2 (ja) 2005-05-11 2011-12-28 富士通セミコンダクター株式会社 半導体装置とその製造方法
JP4578329B2 (ja) 2005-06-03 2010-11-10 ルネサスエレクトロニクス株式会社 半導体記憶装置
CN1893084A (zh) * 2005-07-07 2007-01-10 松下电器产业株式会社 半导体装置
US7405994B2 (en) 2005-07-29 2008-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Dual port cell structure
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US9230910B2 (en) * 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
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US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
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US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US7956421B2 (en) * 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
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US7898894B2 (en) * 2006-04-12 2011-03-01 International Business Machines Corporation Static random access memory (SRAM) cells
US7269056B1 (en) * 2006-04-27 2007-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Power grid design for split-word line style memory cell
US7606057B2 (en) * 2006-05-31 2009-10-20 Arm Limited Metal line layout in a memory cell
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JP2008130670A (ja) * 2006-11-17 2008-06-05 Seiko Epson Corp 半導体装置、論理回路および電子機器
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US9424889B1 (en) * 2015-02-04 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-port SRAM device
US9099172B2 (en) * 2013-01-02 2015-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Dual-port SRAM connection structure
JP2008159669A (ja) * 2006-12-21 2008-07-10 Matsushita Electric Ind Co Ltd 半導体記憶装置
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US7738282B2 (en) * 2007-02-15 2010-06-15 Taiwan Semiconductor Manufacturing Company, Ltd. Cell structure of dual port SRAM
US8667443B2 (en) * 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US7888705B2 (en) 2007-08-02 2011-02-15 Tela Innovations, Inc. Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same
JP2009016809A (ja) * 2007-06-07 2009-01-22 Toshiba Corp 半導体記憶装置
KR100849794B1 (ko) * 2007-07-04 2008-07-31 주식회사 하이닉스반도체 강유전체 소자를 적용한 반도체 메모리 장치
KR100865633B1 (ko) * 2007-07-19 2008-10-27 주식회사 동부하이텍 듀얼 포트 에스램
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
JP2009238332A (ja) 2008-03-27 2009-10-15 Renesas Technology Corp 半導体記憶装置
JP5231924B2 (ja) * 2008-10-03 2013-07-10 株式会社東芝 半導体記憶装置
GB2460049A (en) * 2008-05-13 2009-11-18 Silicon Basis Ltd Reading from an SRAM cell using a read bit line
US7864600B2 (en) * 2008-06-19 2011-01-04 Texas Instruments Incorporated Memory cell employing reduced voltage
MY152456A (en) 2008-07-16 2014-09-30 Tela Innovations Inc Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US8009463B2 (en) * 2009-07-31 2011-08-30 Taiwan Semiconductor Manufacturing Co., Ltd. Cell structure for dual port SRAM
US8189368B2 (en) * 2009-07-31 2012-05-29 Taiwan Semiconductor Manufacturing Co., Ltd. Cell structure for dual port SRAM
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
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WO2011077664A1 (ja) 2009-12-25 2011-06-30 パナソニック株式会社 半導体装置
US8218354B2 (en) * 2009-12-30 2012-07-10 Taiwan Semicondcutor Manufacturing Co., Ltd. SRAM word-line coupling noise restriction
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US8315084B2 (en) * 2010-03-10 2012-11-20 Taiwan Semiconductor Manufacturing Company, Ltd. Fully balanced dual-port memory cell
US8675397B2 (en) * 2010-06-25 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Cell structure for dual-port SRAM
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WO2012017535A1 (ja) * 2010-08-05 2012-02-09 ルネサスエレクトロニクス株式会社 半導体装置
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JP5711033B2 (ja) * 2011-04-12 2015-04-30 ルネサスエレクトロニクス株式会社 半導体集積回路装置
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JP5705053B2 (ja) 2011-07-26 2015-04-22 ルネサスエレクトロニクス株式会社 半導体装置
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US8406028B1 (en) * 2011-10-31 2013-03-26 Taiwan Semiconductor Manufacturing Co., Ltd. Word line layout for semiconductor memory
US9099199B2 (en) * 2012-03-15 2015-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Memory cell and memory array
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JP6151504B2 (ja) * 2012-10-17 2017-06-21 ルネサスエレクトロニクス株式会社 半導体記憶装置
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US9536596B2 (en) * 2014-08-26 2017-01-03 Qualcomm Incorporated Three-port bit cell having increased width
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JP6501688B2 (ja) * 2015-09-29 2019-04-17 ルネサスエレクトロニクス株式会社 半導体記憶装置およびそのテスト方法
TWI726869B (zh) 2016-02-24 2021-05-11 聯華電子股份有限公司 靜態隨機存取記憶體的佈局結構及其製作方法
JP2016146504A (ja) * 2016-04-06 2016-08-12 ルネサスエレクトロニクス株式会社 半導体装置および半導体チップ
TWI681542B (zh) * 2016-05-04 2020-01-01 聯華電子股份有限公司 靜態隨機存取記憶體的佈局圖案
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JP6586204B2 (ja) * 2018-08-02 2019-10-02 ルネサスエレクトロニクス株式会社 半導体装置
TWI823896B (zh) * 2019-02-12 2023-12-01 聯華電子股份有限公司 靜態隨機處理記憶體
JP7370730B2 (ja) * 2019-05-14 2023-10-30 ルネサスエレクトロニクス株式会社 半導体記憶装置
CN111129005B (zh) * 2019-12-25 2023-09-19 上海华力集成电路制造有限公司 一种双口静态随机存储单元版图结构
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Also Published As

Publication number Publication date
US20010043487A1 (en) 2001-11-22
KR20010106233A (ko) 2001-11-29
DE10123514B4 (de) 2005-07-28
US6535453B2 (en) 2003-03-18
JP4885365B2 (ja) 2012-02-29
DE10123514A1 (de) 2001-11-22
JP2002043441A (ja) 2002-02-08
US20020064080A1 (en) 2002-05-30
US6347062B2 (en) 2002-02-12

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