US20010043487A1 - Semiconductor memory device - Google Patents
Semiconductor memory device Download PDFInfo
- Publication number
- US20010043487A1 US20010043487A1 US09/824,008 US82400801A US2001043487A1 US 20010043487 A1 US20010043487 A1 US 20010043487A1 US 82400801 A US82400801 A US 82400801A US 2001043487 A1 US2001043487 A1 US 2001043487A1
- Authority
- US
- United States
- Prior art keywords
- type mos
- channel type
- mos transistor
- area
- phase bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 117
- 238000009792 diffusion process Methods 0.000 claims description 290
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 140
- 229920005591 polysilicon Polymers 0.000 claims description 138
- 230000015654 memory Effects 0.000 claims description 108
- 238000010276 construction Methods 0.000 abstract description 12
- 239000002184 metal Substances 0.000 description 58
- 230000006870 function Effects 0.000 description 34
- 238000010586 diagram Methods 0.000 description 28
- 230000000694 effects Effects 0.000 description 24
- 101500027749 Mus musculus Serpinin Proteins 0.000 description 11
- 239000012535 impurity Substances 0.000 description 11
- 102000000582 Retinoblastoma-Like Protein p107 Human genes 0.000 description 9
- 108010002342 Retinoblastoma-Like Protein p107 Proteins 0.000 description 9
- 102000004642 Retinoblastoma-Like Protein p130 Human genes 0.000 description 9
- 108010003494 Retinoblastoma-Like Protein p130 Proteins 0.000 description 9
- 230000009467 reduction Effects 0.000 description 9
- 101100378758 Anemone leveillei AL21 gene Proteins 0.000 description 8
- 239000000758 substrate Substances 0.000 description 8
- 230000010354 integration Effects 0.000 description 7
- 101710190981 50S ribosomal protein L6 Proteins 0.000 description 6
- 101000575029 Bacillus subtilis (strain 168) 50S ribosomal protein L11 Proteins 0.000 description 6
- 102100035793 CD83 antigen Human genes 0.000 description 6
- 101000946856 Homo sapiens CD83 antigen Proteins 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 6
- 101100055224 Anemone leveillei AL10 gene Proteins 0.000 description 5
- 230000003247 decreasing effect Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 238000000682 scanning probe acoustic microscopy Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
Definitions
- the present invention relates to a semiconductor memory device. More particularly this invention relates, to a layout of a multi-port SRAM (Static Random Access Memory) cell having CMOS construction.
- SRAM Static Random Access Memory
- DRAM Dynamic RAM
- SRAM Stynamic RAM
- SRAM is generally used for cache memories and the like that require a high-speed processing.
- the SPAM is known to have a high-resistance load type memory cell and a CMOS type memory cell.
- the high-resistance load type is constructed of four transistors and two high-resistance elements.
- the CMOS type is constructed of six transistors. Because of very small leakage current during data holding, the CMOS type SRAM has high reliability and has been used as a main SRAM at present.
- a reduction in the area of the memory cell means not only a reduction in the size of the memory cell array but also a realization of high-speed processing.
- various layout proposals have been made so far.
- JP-A Japanese Patent Application Laid-Open
- P-well areas and N-well area formed with inverters that constitute a memory cell are disposed so that their boundary lines are parallel with bit lines.
- diffusion areas within the P-well areas and the N-well area and a cross-connected portion of two inverters are formed in simple shapes respectively having no bending. As a result, the cell area is reduced.
- FIG. 21 and FIG. 22 are layout diagrams of the semiconductor memory device disclosed in Japanese Patent Application Laid-Open (JP-A) No. 10-178110.
- FIG. 21 shows diffusion areas formed on the surface of a semiconductor substrate, a polycrystalline silicon film formed on the diffusion areas, and a ground including a first metal-wiring layer.
- FIG. 22 shows an upper ground including second and third metal-wiring layers formed on the upper layer.
- N-well area in which P-channel type MOS transistors P 101 and P 102 are formed.
- P-well areas On both sides of this N-well area, there are formed P-well areas in which N-channel type MOS transistors N 101 and N 103 , and N 102 and N 104 are formed respectively.
- the P-channel type MOS transistors P 101 and P 102 and the N-channel type MOS transistors N 101 and N 102 are mutually connected in cross to form a CMOS inverter, that is, a flip-flop circuit.
- the N-channel type MOS transistors N 103 and N 104 correspond to an access gate (a transfer gate).
- bit lines BL and /BL are separately formed as second metal-wiring layers.
- the bit lines BL and /BL are connected to one end of semiconductor terminals of the lower-layer access gate MOS transistors N 103 and N 104 respectively.
- a power source line Vdd is formed as a second metal-wiring layer in the center between the bit lines BL and /BL in parallel with these bit lines.
- the power source line Vdd is connected to one of semiconductor terminals of the lower-layer P-channel type MOS transistors P 101 and P 102 .
- a word line WL is formed as a third metal-wiring layer in a direction orthogonal with the bit lines BL and /BL.
- the word line WL is connected to gates of the lower-layer N-channel type MOS transistor N 103 and N 104 .
- Two ground lines GND are formed as third metal-wiring layers on both sides of the word line WL in parallel with this word line.
- an N-type diffusion area within the P-well area in which the MOS transistors N 101 and N 103 are formed and an N-type diffusion area in which the MOS transistors N 102 and N 104 are formed can be formed linearly in parallel with the bit lines BL and /BL. This construction can prevent a generation of an unnecessary area.
- the length of the cell in a lateral direction that is, the length of the word line WL
- the length of the cell in a longitudinal direction that is, the length of the bit lines BL and /BL. Therefore, it becomes easy to provide a layout of a sense amplifier connected to the bit lines BL and /BL.
- the number of cells to be connected to one word line can be reduced. As a result, it is possible to reduce a cell current that flows during the reading. In other words, it is possible to reduce power consumption.
- the above-described SRAM memory cell is an example of what is called one-port SRAM.
- a multi-processor technique as one of means for achieving high-speed processing of computers. Based on this technique, a plurality of CPUs are required to share one memory area.
- various layouts have been proposed for a multi-port SRAM that makes it possible to have access to CPUs from two ports to the one memory cell.
- FIG. 23 shows the layout of the memory cell disclosed in Japanese Patent Application Laid-Open (JP-A) No. 07-7089.
- P-channel type MOS transistors P 201 and P 202 and N-channel type MOS transistors N 201 ′, N 202 ′, N 201 ′′ and N 202 ′′ are mutually connected in cross to form a CMOS inverter, that is, a flip-flop.
- N-channel type MOS transistors NA, NB, NA 2 and NB 2 correspond to access gates (transfer gates).
- N-channel type MOS transistors NA and NB make it possible to have an access from one gate via a word line WL 1
- N-channel type MOS transistors NA 2 and NB 2 make it possible to have an access from the other gate via a word line WL 2 .
- this semiconductor memory device does not solve the above problem for a multi-port SRAM generally having two sets of access gates and a drive-type MOS transistor.
- the memory cell disclosed in Japanese Patent Application Laid-Open (JP-A) No. 07-7089 shows a layout of a multi-port SRAM cell.
- JP-A Japanese Patent Application Laid-Open
- this provides the layout for making it easy to add a second port without generating a large change in the layout of the one-port SRAM cell. This has not an object of reducing the multi-port SRAM cell in the direction of the bit lines.
- the P-well area is divided into two P-well areas.
- the two P-well areas are disposed on the two sides of the N-well area.
- the boundaries between P and N-well areas are parallel to the bit lines, and a pair of access gates are formed in each of the two P-well areas.
- two P-well areas are provided on the two sides of the N-well area, three (first, third and fifth) N-channel type MOS transistors are electrically connected to the positive-phase bit line and are formed in one P-well area, and three (second, fourth and sixth) N-channel type MOS transistors are connected to the negative-phase bit line and are formed in the other P-well area.
- the P-well areas and the N-well area are disposed in a direction perpendicular to the positive-phase and negative-phase bit lines. Therefore, it is possible to provide a layout that requires shorter bit lines.
- the first and second P-well areas are formed on both sides of the N-well area. According, it is possible to make uniform the distances of wiring connection between the N-channel type MOS transistors formed in the first and second P-well areas respectively and the P-channel type MOS transistors formed in the N-well area.
- first positive-phase bit line, first negative-phase bit line, the second positive-phase bit line, and the second negative-phase bit line extend parallel to boundary lines between the first and second P-well areas and the N-well area respectively. According, it is possible to provide a layout having each bit line formed in a shortest length by taking into consideration a reduction in the length of each word line.
- the boundary lines between the first and second P-well areas and the N-well area are perpendicular to the direction in which the first and second word lines extend. Accordingly, it is possible to provide a layout having each word line formed in a shortest length by taking into consideration a reduction in the length of each bit line with priority.
- the first P-channel type MOS transistor and the first, third and fourth N-channel type MOS transistors are formed so that respective gate areas are parallel with the extension direction of the first word line and are positioned on the same straight line
- the second P-channel type MOS transistor and the second, fifth and sixth N-channel type MOS transistors are formed so that respective gate areas are parallel with the extension direction of the second word line and are positioned on the same straight line. Accordingly, it is possible to form wires for connecting between the gates in a straight-line shape.
- the second P-channel type MOS transistor and the gate areas of the second, fifth and sixth N-channel type MOS transistors are positioned on the same straight line, it is possible to form wires for connecting between the gates in a straight-line shape.
- the third and fifth N-channel type MOS transistors are formed in such a manner that respective source diffusion areas and drain diffusion areas are positioned on the same straight line, and are also disposed in parallel with the directions of the extension of the first and second positive-phase bit lines.
- the fourth and sixth N-channel type MOS transistors are formed in such a manner that respective source diffusion areas and drain diffusion areas are positioned on the same straight line, and are also disposed in parallel with the directions of the extension of the first and second negative-phase bit lines.
- drain diffusion areas of the third and fifth N-channel type MOS transistors are formed in a common first n + diffusion area, and drain diffusion areas of the fourth and sixth N-channel type MOS transistors are formed in a common second n + diffusion area. Accordingly, it is possible to reduce the size of the n + diffusion areas.
- drain diffusion area of the first N-channel type MOS transistor and drain diffusion areas of the third and fifth N-channel type MOS transistors are connected to each other by an upper-layer first metal-wiring layer via contact holes
- a drain diffusion area of the second N-channel type MOS transistor and drain diffusion areas of the fourth and sixth N-channel type MOS transistors are connected to each other by an upper-layer second metal-wiring layer via contact holes. Accordingly, it is possible to form the first and second metal-wiring layers in a straight-line shape according to the positions of the drain diffusion areas.
- the extension direction of the first and second metal-wiring layers is parallel with the extension direction of the first and second word lines. Accordingly, it is possible to optimize the length of the metal-wiring layers like the word lines.
- extension directions of the first and second positive-phase bit line, the first and second negative-phase bit lines, the power source line and the GND line respectively are perpendicular to the first and second word lines. Accordingly, it is possible to minimize the respective length of these lines.
- drain diffusion areas of the first, third and fifth N-channel type MOS transistors are formed in a common first n + diffusion area
- drain diffusion areas of the second, fourth and sixth N-channel type MOS transistors are formed in a common second n + diffusion area. Accordingly, it is possible to omit the metal-wiring layers between these drain diffusion areas.
- the first n + diffusion area and a drain diffusion area of the first P-channel type MOS transistor are connected to each other by an upper-layer first metal-wiring layer via contact holes
- the second n + diffusion area and a drain diffusion area of the second P-channel type MOS transistor are connected to each other by an upper-layer second metal-wiring layer via contact holes. Accordingly, it is possible to form the metal-wiring layers in a straight-line shape according to the positions of the drain diffusion areas and the n + diffusion areas.
- the semiconductor memory device comprises a first word line, a second word line, a first positive-phase bit line, a first negative-phase bit line, and a second positive-phase bit line; a first CMOS inverter that structures a CMOS inverter by including a first N-channel type MOS transistor and a first P-channel type MOS transistor; a second CMOS inverter that structures a CMOS inverter by including a second N-channel type MOS transistor and a second P-channel type MOS transistor, and that has an input terminal of the CMOS inverter connected to an output terminal of the first CMOS inverter as a first memory node, and has an output terminal of the CMOS inverter connected to an input terminal of the first CMOS inverter as a second memory node; a third N-channel type MOS transistor that has a gate connected to the first word line, has a drain connected to the first positive-phase bit line, and has a source
- first and second P-channel type MOS transistors are formed in an N-well area
- the first and third N-channel type MOS transistors are formed in a first P-well area
- the second, fourth, fifth and sixth N-channel type MOS transistors are formed in a second P-well area.
- the semiconductor memory device further comprises a third word line, a first positive-phase line, and a second negative-phase bit line; a seventh N-channel type MOS transistor that has a gate connected to the second memory node; and an eighth N-channel type MOS transistor that has a gate connected to the third word line, has a drain connected to the second negative-phase bit line, and has a source connected to a drain of the seventh N-channel type MOS transistor.
- the seventh and eighth N-channel type MOS transistors are formed in the first P-well area.
- the second and third word lines are formed as one common word line.
- first and second P-well areas are formed at both sides of the N-well area.
- the respective directions of the extensions of the first positive-phase bit line, the first negative-phase bit line, and the second positive-phase bit line are parallel with a boundary line between the first and second P-well areas and the N-well area.
- a boundary line between the first and second P-well areas and the N-well area is orthogonal with directions of respective extensions of the first and second word lines.
- the first P-channel type MOS transistor, and the first, fourth and sixth N-channel type MOS transistors are formed such that their respective gate areas are positioned on the same straight line, and are also disposed in parallel with the direction of the extension of the first word line.
- the second P-channel type MOS transistor, and the second, third and fifth N-channel type MOS transistors are formed such that their respective gate areas are positioned on the same straight line, and are also disposed in parallel with the direction of the extension of the second word line.
- the first and third N-channel type MOS transistors are formed such that a drain diffusion area of the first N-channel type MOS transistor and a source diffusion area of the third N-channel type MOS transistor are positioned on the same straight line, and also disposed in parallel with the direction of the extension of the first positive-phase bit line.
- the second and fourth N-channel type MOS transistors are formed such that a drain diffusion area of the second N-channel type MOS transistor and a source diffusion area of the fourth N-channel type MOS transistor are positioned on the same straight line, and also disposed in parallel with the direction of the extension of the first negative-phase bit line.
- the fifth and sixth N-channel type MOS transistors are formed such that a drain diffusion area of the fifth N-channel type MOS transistor and a source diffusion area of the sixth N-channel type MOS transistor are positioned on the same straight line, and also disposed in parallel with the direction of the extension of the second positive-phase bit line.
- a drain diffusion area of the first N-channel type MOS transistor and a source diffusion area of the third N-channel type MOS transistor are formed in a common first n + diffusion area.
- a drain diffusion area of the second N-channel type MOS transistor and a source diffusion area of the fourth N-channel type MOS transistor are formed in a common second n + diffusion area.
- a drain diffusion area of the fifth N-channel type MOS transistor and a source diffusion area of the sixth N-channel type MOS transistor are formed in a common third n + diffusion area.
- the second P-channel type MOS transistor, and the second and fifth N-channel type MOS transistors have their respective gate areas connected by a straight line-shaped common polysilicon wiring.
- the directions of the extensions of the first and second positive-phase bit lines, the first negative-phase bit line, a power source line, and a GND line respectively are perpendicular to the first and second word lines.
- the first P-channel type MOS transistor, and the first, fourth, sixth and seventh N-channel type MOS transistors are formed such that their respective gate areas are in parallel with the direction of the extension of the first word line, and are also positioned on the same straight line.
- the second P-channel type MOS transistor, and the second, third, fifth and eighth N-channel type MOS transistors are formed such that their respective gate areas are in parallel with the direction of the extension of the second word line, and are also positioned on the same straight line.
- the first and third N-channel type MOS transistors are formed such that a drain diffusion area of the first N-channel type MOS transistor and a source diffusion area of the third N-channel type MOS transistor are in parallel with the direction of the extension of the first positive-phase bit line, and are also positioned on the same straight line.
- the second and fourth N-channel type MOS transistors are formed such that a drain diffusion area of the second N-channel type MOS transistor and a source diffusion area of the fourth N-channel type MOS transistor are in parallel with the direction of the extension of the first negative-phase bit line, and are also positioned on the same straight line.
- the fifth and sixth N-channel type MOS transistors are formed such that a drain diffusion area of the fifth N-channel type MOS transistor and a source diffusion area of the sixth N-channel type MOS transistor are in parallel with the direction of the extension of the second positive-phase bit line, and are also positioned on the same straight line.
- the seventh and eighth N-channel type MOS transistors are formed such that a drain diffusion area of the seventh N-channel type MOS transistor and a source diffusion area of the eighth N-channel type MOS transistor are in parallel with the direction of the extension of the second negative-phase bit line, and are also positioned on the same straight line.
- a drain diffusion area of the first N-channel type MOS transistor and a source diffusion area of the third N-channel type MOS transistor are formed in a common first n + diffusion area.
- a drain diffusion area of the second N-channel type MOS transistor and a source diffusion area of the fourth N-channel type MOS transistor are formed in a common second n + diffusion area.
- a drain diffusion area of the fifth N-channel type MOS transistor and a source diffusion area of the sixth N-channel type MOS transistor are formed in a common third n + diffusion area.
- a drain diffusion area of the seventh N-channel type MOS transistor and a source diffusion area of the eighth N-channel type MOS transistor are formed in a common fourth n + diffusion area.
- the second P-channel type MOS transistor, and the second and fifth N-channel type MOS transistors have their respective gate areas connected by a straight line-shaped common first polysilicon wiring.
- the first P-channel type MOS transistor, and the first and seventh N-channel type MOS transistors have their respective gate areas connected by a straight line-shaped common second polysilicon wiring.
- FIG. 1 is a diagram showing an equivalent circuit of a semiconductor memory device according to a first embodiment of the present invention.
- FIG. 2 is a diagram showing an example of the layout of a memory cell of the semiconductor memory device according to the first embodiment.
- FIG. 3 is a diagram showing an another example of the layout of the memory cell of the semiconductor memory device according to the first embodiment.
- FIG. 4 is a diagram showing still another example of the layout of the memory cell of the semiconductor memory device according to the first embodiment.
- FIG. 5 is a diagram showing still another example of the layout of the memory cell of the semiconductor memory device according to the first embodiment.
- FIG. 6 is an explanation of various symbols like a contact hole, a via hole, etc.
- FIG. 7 is a diagram showing an example of the layout of a memory cell of a semiconductor memory device according to a second embodiment of the invention.
- FIG. 8 is a diagram showing an equivalent circuit of a semiconductor memory device according to a third embodiment of the present invention.
- FIG. 9 is a diagram showing an example of the layout of a memory cell of the semiconductor memory device according to the third embodiment.
- FIG. 10 is a diagram showing another example of the layout of the memory cell of the semiconductor memory device according to the third embodiment.
- FIG. 11 is a diagram showing still another example of the layout of the memory cell of the semiconductor memory device according to the third embodiment.
- FIG. 12 is a diagram showing still another example of the layout of the memory cell of the semiconductor memory device according to the third embodiment.
- FIG. 13 is a diagram showing an equivalent circuit of a semiconductor memory device according to a fourth embodiment of the present invention.
- FIG. 14 is a diagram showing an example of the layout of the memory cell of the semiconductor memory device according to the fourth embodiment.
- FIG. 15 is a diagram showing another example of the layout of the memory cell of the semiconductor memory device according to the fourth embodiment.
- FIG. 16 is a diagram showing still another example of the layout of the memory cell of the semiconductor memory device according to the fourth embodiment.
- FIG. 17 is a diagram showing still another example of the layout of the memory cell of the semiconductor memory device according to the fourth embodiment.
- FIG. 18 is a diagram showing an equivalent circuit of a semiconductor memory device according to a fifth embodiment of the present invention.
- FIG. 19 is a diagram showing an example of the layout of the memory cell of the semiconductor memory device according to the fifth embodiment.
- FIG. 20 is a diagram showing another example of the layout of the memory cell of the semiconductor memory device according to the fifth embodiment.
- FIG. 21 is a layout diagram showing a diffusion area formed on the surface of a semiconductor substrate, a polycrystalline silicon film formed on the diffusion areas, and a ground including a first metal-wiring layer, according to a conventional semiconductor memory device.
- FIG. 22 is a layout diagram showing an upper ground including second and third metal-wiring layers formed on the upper layer, according to the conventional semiconductor memory device.
- FIG. 23 is a layout diagram showing a conventional memory cell.
- FIG. 1 shows an equivalent circuit of the semiconductor memory device of the first embodiment.
- a P-channel type MOS transistor P 1 and an N-channel type MOS transistor N 1 (N 1 ′) constitute a first CMOS inverter.
- a P-channel type MOS transistor P 2 and an N-channel type MOS transistor N 2 (N 2 ′) constitute a second CMOS inverter. Inputs and outputs of these CMOS inverters are connected in cross.
- these MOS transistors P 1 , P 2 , N 1 , N 1 ′, N 2 and N 2 ′ constitute a flip-flop circuit.
- FIG. 1 it is possible to carry out a writing and a reading in a logic state in a memory node MA which is an output point of the first CMOS inverter and input point of the second CMOS inverter, and in a memory node MB which is an output point of the second CMOS inverter and input point of the first CMOS inverter.
- N-channel type MOS transistors M 3 , N 4 , N 5 and N 6 function as access gates respectively.
- the gate of the N-channel type MOS transistor N 3 is connected to a first word line WL 0
- the source is connected to the memory node MA
- the drain is connected to a first positive-phase bit line B 100 .
- the gate of the N-channel type MOS transistor N 5 is connected to a second word line WL 1
- the source is connected to the memory node MA
- the drain is connected to a second positive-phase bit line BL 10 .
- the gate of the N-channel type MOS transistor N 4 is connected to a first word line WL 0 , the source is connected to the memory node MB, and the drain is connected to a first negative-phase bit line BL 01 .
- the gate of the N-channel type MOS transistor N 6 is connected to the second word line WL 1 , the source is connected to the memory node MB, and the drain is connected to a second negative-phase bit line BL 11 .
- FIG. 2 to FIG. 5 are layout diagrams of the memory cell of the semiconductor memory device of the first embodiment.
- FIG. 6 explains various symbols like a contact hole, a via hole, etc. shown in FIG. 2 to FIG. 5.
- FIG. 2 shows layers including well areas formed on a semiconductor substrate, diffusion areas formed in the well areas, and a polysilicon wiring layer formed on the upper surface.
- a first P-well area PW 1 In the memory cell of the semiconductor memory device of the first embodiment, there are formed a first P-well area PW 1 , an N-well area NW, and a second P-well area PW 2 in this sequence in a plain direction on the semiconductor substrate, as shown in FIG. 2.
- the two P-well areas PW 1 and PW 2 are disposed separately on the two sides of the N-well area NW.
- these well areas are formed so that a boundary line between the first P-well area PW 1 and the N-well area NW (hereinafter to be referred to as a first well boundary line) and a boundary line between the second P-well area PW 2 and the N-well area NW (hereinafter to be referred to as a second well boundary line) are parallel with each other.
- a boundary line between the first P-well area PW 1 and the N-well area NW hereinafter to be referred to as a first well boundary line
- a boundary line between the second P-well area PW 2 and the N-well area NW hereinafter to be referred to as a second well boundary line
- the N-channel type MOS transistors N 1 , N 1 ′, N 3 and N 5 shown in FIG. 1 are formed in the first P-well area PW 1 .
- the P-channel type MOS transistors P 1 and P 2 shown in FIG. 1 are formed in the N-well area NW.
- the N-channel type MOS transistors N 2 , N 2 ′, N 4 and N 6 shown in FIG. 1 are formed in the second P-well area PW 2 .
- each layer shown in FIG. 2 to FIG. 5 will be explained in sequence.
- two polysilicon wiring layers PL 21 and PL 22 are disposed in the first P-well area PW 1 extending in a direction perpendicular to the first well boundary line.
- two polysilicon wiring layers PL 31 and PL 32 are disposed in the second P-well area PW 2 extending in a direction perpendicular to the second well boundary line.
- a piece type polysilicon wiring layer PL 11 is formed in the area from the N-well area NW to the first P-well area PW 1 in a direction perpendicular to the first well boundary line so that the piece end is positioned in the first P-well area PW 1 .
- the piece end has a shape that two parallel axes (a main axis and a return axis) that constitute the piece end of the polysilicon wiring layer PL 11 coincide with axes of the two polysilicon wiring layers PL 21 and PL 22 respectively. Further, the main axis of the polysilicon wiring layer PL 11 coincides with the polysilicon wiring layer PL 21 . On the other hand, the other end of the polysilicon wiring layer PL 11 is positioned on the second well boundary line.
- a piece type polysilicon wiring layer PL 12 is formed in the area from the N-well area NW to the second P-well area PW 2 in a direction perpendicular to the second well boundary line so that the piece end is positioned in the second P-well area PW 2 .
- the piece end has a shape that two parallel axes that constitute the piece end of the polysilicon wiring layer PL 12 coincide with axes of the two polysilicon wiring layers PL 31 and PL 32 respectively.
- the main axis of the polysilicon wiring layer PL 12 coincides with the polysilicon wiring layer PL 31 .
- the other end of the polysilicon wiring layer PL 12 is positioned on the first well boundary line.
- n + diffusion areas FL 21 and FL 22 are formed in the first P-well area PW 1 by injecting an N-type impurity at positions sandwiching the polysilicon wiring layer PL 21 .
- an N-channel type MOS transistor N 3 that uses the polysilicon wiring layer PL 21 as a gate electrode.
- n + diffusion areas FL 22 and FL 23 are formed at positions sandwiching the polysilicon wiring layer PL 22 .
- an N-channel type MOS transistor N 5 that uses the polysilicon wiring layer PL 22 as a gate electrode.
- the polysilicon wiring layers PL 21 and PL 22 are disposed in parallel in the N-channel type MOS transistors N 3 and N 5 respectively, it is possible to dispose the n + diffusion areas FL 21 to FL 23 in a direction parallel with the first well boundary line and also in a straight line.
- the N-channel type MOS transistors N 3 and N 5 can share the n + diffusion area FL 22 .
- the sharing of this n + diffusion area FL 22 makes it possible to connect the sources of the N-channel type MOS transistors N 3 and N 5 together, and also contributes to reduce the area occupied by the N-channel type MOS transistors N 3 and N 5 , according to the equivalent circuit shown in FIG. 1.
- n + diffusion areas FL 24 and FL 25 are formed in the first P-well area PW 1 by injecting an N-type impurity at positions sandwiching the main axis of the piece end of the polysilicon wiring layer PL 11 .
- an N-channel type MOS transistor N 1 that uses the main axis of the polysilicon wiring layer PL 11 as a gate electrode.
- n + diffusion areas FL 25 and FL 26 are formed at positions sandwiching the return axis of the piece end of the polysilicon wiring layer PL 11 .
- an N-channel type MOS transistor N 1 ′ that uses the return axis of the polysilicon wiring layer PL 11 as a gate electrode.
- the piece end of the polysilicon wiring layer PL 11 makes it possible to connect the gates of the N-channel type MOS transistors N 1 and N 1 ′ together, according to the equivalent circuit shown in FIG. 1.
- the main axis and the return axis of the polysilicon wiring layer PL 11 are disposed in parallel in the N-channel type MOS transistors N 1 and N 1 ′ respectively. Therefore, it is possible to dispose the n + diffusion areas FL 24 to FL 26 in a direction parallel with the first well boundary line and also in a straight line. With this arrangement, the N-channel type MOS transistors N 1 and N 1 ′ can share the n + diffusion area FL 25 .
- n + diffusion area FL 25 makes it possible to connect the drains of the N-channel type MOS transistors N 1 and N 1 ′ together, and also contributes to reduce the area occupied by the N-channel type MOS transistors N 1 and N 1 ′, according to the equivalent circuit shown in FIG. 1.
- the main axes of the polysilicon wiring layer PL 21 and the polysilicon wiring layer PL 11 are positioned on the same straight line, and the return axes of the polysilicon wiring layer PL 22 and the polysilicon wiring layer PL 11 are also positioned on the same straight line. Therefore, it is possible to reduce the disposition distance between the N-channel type MOS transistors N 1 and N 1 ′ and between the N-channel type MOS transistors N 3 and MS respectively. As a result, it is possible to achieve a reduction in the area occupied by these four N-channel type MOS transistors in the first P-well area PW 1 .
- n + diffusion areas FL 31 and FL 32 are similarly formed in the second P-well area PW 2 by injecting an N-type impurity at positions sandwiching the polysilicon wiring layer PL 31 .
- an N-channel type MOS transistor N 6 that uses the polysilicon wiring layer PL 21 as a gate electrode.
- n + diffusion areas FL 32 and FL 33 are formed at positions sandwiching the polysilicon wiring layer PL 32 .
- an N-channel type MOS transistor N 4 that uses the polysilicon wiring layer PL 32 as a gate electrode.
- the polysilicon wiring layers PL 31 and PL 32 are also disposed in parallel in the N-channel type MOS transistors N 4 and N 6 respectively, it is possible to dispose the n + diffusion areas FL 31 to FL 33 in a direction parallel with the second well boundary line and also in a straight line. With this arrangement, the N-channel type MOS transistors N 4 and N 6 can share the n + diffusion area FL 32 .
- the sharing of this n + diffusion area FL 32 makes it possible to connect the sources of the N-channel type MOS transistors N 4 and N 6 together, and also contributes to reduce the area occupied by the N-channel type MOS transistors N 4 and N 6 , according to the equivalent circuit shown in FIG. 1.
- n + diffusion areas FL 34 and FL 35 are formed in the second P-well area PW 2 by injecting an N-type impurity at positions sandwiching the main axis of the piece end of the polysilicon wiring layer PL 12 .
- an N-channel type MOS transistor N 2 that uses the main axis of the polysilicon wiring layer PL 12 as a gate electrode.
- n + diffusion areas FL 35 and FL 36 are formed at positions sandwiching the return axis of the piece end of the polysilicon wiring layer PL 12 .
- an N-channel type MOS transistor N 2 ′ that uses the return axis of the polysilicon wiring layer PL 12 as a gate electrode.
- the piece end of the polysilicon wiring layer PL 12 makes it possible to connect the gates of the N-channel type MOS transistors N 2 and N 2 ′ together, according to the equivalent circuit shown in FIG. 1.
- the main axis and the return axis of the polysilicon wiring layer PL 12 are disposed in parallel in the N-channel type MOS transistors N 2 and N 2 ′ respectively. Therefore, it is possible to dispose the n + diffusion areas FL 34 to FL 36 in a direction parallel with the second well boundary line and also in a straight line. With this arrangement, the N-channel type MOS transistors N 2 and N 2 ′ can share the n + diffusion area FL 35 .
- n + diffusion area FL 35 makes it possible to connect the drains of the N-channel type MOS transistors N 2 and N 2 ′ together, and also contributes to reduce the area occupied by the N-channel type MOS transistors N 2 and N 2 ′, according to the equivalent circuit shown in FIG. 1.
- the main axes of the polysilicon wiring layer PL 31 and the polysilicon wiring layer PL 12 are positioned on the same straight line, and the return axes of the polysilicon wiring layer PL 32 and the polysilicon wiring layer PL 12 are also positioned on the same straight line. Therefore, it is possible to reduce the disposition distance between the N-channel type MOS transistors N 2 and N 2 ′ and between the N-channel type MOS transistors N 4 and N 6 respectively. As a result, it is possible to achieve a reduction in the area occupied by these four N-channel type MOS transistors in the second P-well area PW 2 .
- p + diffusion areas FL 11 and FL 12 are formed in the N-well area NW by injecting a P-type impurity at positions sandwiching the main axis of the polysilicon wiring layer PL 11 .
- a P-channel type MOS transistor P 1 that uses the polysilicon wiring layer PL 11 as a gate electrode.
- p + diffusion areas FL 13 and FL 14 are formed at positions sandwiching the main axis of the polysilicon wiring layer PL 12 .
- P-channel type MOS transistor P 2 that uses the polysilicon wiring layer PL 12 as a gate electrode.
- Positions of the P-channel type MOS transistors P 1 and P 2 are determined based on the positions of the polysilicon wiring layers PL 11 and PL 12 .
- Distance between the polysilicon wiring layers PL 11 and PL 12 can be reduced to about the size of the p + diffusion area FL 12 or the FL 13 (minimum pitch of the transistor) as shown in FIG. 2.
- the sizes of the p + diffusion areas FL 12 and FL 13 are set approximately equal to the sizes of the n + diffusion areas FL 22 and FL 25 in the first P-well area PW 1 and the n + diffusion areas FL 32 and FL 35 in the second P-well area PW 2 , it is possible to minimize the total area required for the layout of the memory cell.
- the above arrangement also means that it is possible to dispose the main axes of the polysilicon wiring layers PL 21 and PL 11 , the return axis of the PL 12 and the PL 32 on the same straight line, and it is also possible to dispose the main axes of the polysilicon wiring layers PL 22 and PL 12 , the return axis of the PL 11 and the PL 31 on the same straight line.
- FIG. 3 shows layers including first metal-wiring layers formed on the layers shown in FIG. 2.
- a first metal-wiring layer AL 11 for electrically connecting the lower-layer items of the n + diffusion areas FL 22 and FL 25 , the p + diffusion area FL 12 , and the polysilicon wiring layer PL 12 .
- This first metal-wiring layer AL 11 makes it possible to connect the sources of the N-channel type MOS transistors N 3 and N 5 , the drains of the N-channel type MOS transistors N 1 and N 1 ′, the output terminal of the first CMOS inverter, and the input terminal of the second CMOS inverter, according to the equivalent circuit shown in FIG. 1.
- first metal-wiring layer AL 12 for electrically connecting between the lower-layer items of the n + diffusion areas FL 32 and FL 35 , the p + diffusion area FL 13 , and the polysilicon wiring layer PL 11 .
- This first metal-wiring layer AL 12 makes it possible to connect between the sources of the N-channel type MOS transistors N 4 and N 6 , the drains of the N-channel type MOS transistors N 2 and N 2 ′, the output terminal of the second CMOS inverter, and the input terminal of the first CMOS inverter, according to the equivalent circuit shown in FIG. 1.
- the contact points of the n + diffusion areas FL 32 and FL 35 and the p + diffusion area FL 13 are disposed on the same straight line as described above. Therefore, it is possible to form a wire for connecting between these three points in a straight-line shape.
- the above similarly applies to the first metal-wiring layer AL 12 .
- first metal-wiring layer AL 15 for moving the connection point of the lower-layer p + diffusion area FL 11
- first metal-wiring layer AL 16 for moving the connection point of the lower-layer p + diffusion area FL 14
- first metal-wiring layer AL 17 for moving the connection point of the lower-layer n + diffusion area FL 23
- first metal-wiring layer AL 18 for moving the connection point of the lower-layer n + diffusion area FL 33 .
- FIG. 4 shows layers including second metal-wiring layers formed on the layers shown in FIG. 3.
- a second metal-wiring layer AL 21 for applying a power source potential VDD to the p + diffusion area FL 11 via the first metal-wiring layer AL 15 shown in FIG. 3 and for applying a power source potential VDD to the p + diffusion area FL 14 via the first metal-wiring layer AL 16 .
- the second metal-wiring layer AL 21 functions as a power source potential VDD line, and achieves a connection between the source of the P-channel type MOS transistor P 1 and the power source and a connection between the source of the P-channel type MOS transistor P 2 and the power source, in the equivalent circuit shown in FIG. 1.
- second metal-wiring layers AL 22 and AL 23 for applying a ground potential GND to the p + diffusion areas FL 24 and FL 26 and to the p + diffusion areas FL 34 and FL 36 respectively via contact holes and first via holes shown in FIG. 3.
- the second metal-wiring layers AL 22 and AL 23 function as a ground potential GND line respectively, and achieve a grounding of each source of the N-channel type MOS transistors N 1 , N 1 ′, N 2 and N 2 ′ respectively, in the equivalent circuit shown in FIG. 1.
- the n + diffusion areas FL 24 and FL 26 are disposed on a straight line parallel with the first well boundary line. Therefore, the contact holes on the n + diffusion areas may be formed at positions where a straight line connecting between the contact holes is parallel with the first well boundary line.
- the second metal-wiring layer AL 22 shown in FIG. 4 in a straight-line shape parallel with the first well boundary line. This similarly applies to the second metal-wiring layer AL 23 .
- a second metal-wiring layer AL 24 that is connected with the lower-layer p + diffusion area FL 21 and functions as a first positive-phase bit line BL 00
- a second metal-wiring layer AL 25 that is connected with the lower-layer p + diffusion area FL 26 and functions as a second positive-phase bit line BL 10
- a second metal-wiring layer AL 26 that is connected with the lower-layer p + diffusion area FL 36 and functions as a first negative-phase bit line BL 01
- a second metal-wiring layer AL 27 that is connected with the lower-layer p + diffusion area FL 31 and functions as a second negative-phase bit line BL 11 , via the contact holes and the first via holes shown in FIG. 3 respectively.
- these second metal-wiring layers AL 24 to AL 27 achieve a connection between the other semiconductor end (drain) of the N-channel type MOS transistor N 3 and the first positive-phase bit line BL 00 , a connection between the other semiconductor end (drain) of the N-channel type MOS transistor N 5 and the second positive-phase bit line BL 10 , a connection between the other semiconductor end (drain) of the N-channel type MOS transistor N 4 and the first negative-phase bit line BL 01 , and a connection between the other semiconductor end (drain) of the N-channel type MOS transistor N 6 and the second negative-phase bit line BL 11 , respectively, in the equivalent circuit shown in FIG. 1.
- the second metal-wiring layers AL 24 to AL 27 in a straight-line shape respectively extending in a direction parallel with the first well boundary line. This means that it is possible to further reduce the length of each of the first positive-phase bit line BL 00 , the second positive-phase bit line BL 10 , the first negative-phase bit line BL 01 and the second negative-phase bit line BL 11 , within one memory cell.
- FIG. 5 shows layers including third metal-wiring layers formed on the layers shown in FIG. 4.
- a third metal-wiring layer AL 31 for electrically connecting the polysilicon wiring layers PL 21 and PL 32 via the first via hole and a second via hole and for functioning as a first word line WL 0 .
- the third metal-wiring layer AL 31 achieves a connection between the gates of the N-channel type MOS transistors N 3 and N 4 and the first word line WL 0 , in the equivalent circuit shown in FIG. 1.
- a third metal-wiring layer AL 32 for electrically connecting the polysilicon wiring layers PL 22 and PL 31 via the first via hole and the second via hole and for functioning as a second word line WL 1 .
- the third metal-wiring layer AL 32 achieves a connection between the gates of the N-channel type MOS transistors N 5 and N 6 and the second word line WL 1 , in the equivalent circuit shown in FIG. 1.
- the polysilicon wiring layers PL 21 and PL 32 are disposed on the same straight line extending in a direction perpendicular to the first well boundary line. Therefore, it is possible to form the contact holes on the polysilicon wiring layers at positions where a straight line connecting between these contact holes is perpendicular to the first well boundary line.
- the third metal-wiring layer AL 31 shown in FIG. 5 can be formed in a straight-line shape extending in a direction perpendicular to the first well boundary line. This similarly applies to the third metal-wiring layer AL 32 . This means that it is possible to further reduce the length of each of the first word line WLQ and the second word line WL 1 within one memory cell.
- the N-channel type MOS transistors N 3 and N 5 functioning as access gates share the common n + diffusion area FL 22 (or FL 32 ) at a connection point between these semiconductors.
- the n + diffusion areas FL 21 to FL 23 (or FL 31 to FL 33 ) that become the respective semiconductor terminals are formed on the same straight line parallel with the first well boundary line. Therefore, it is possible to reduce the area occupied by the N-channel type MOS transistors N 3 and N 5 (or N 4 and N 6 ). This makes it possible to increase the integration degree of the memory cell array.
- the second metal-wiring layers AL 24 to AL 27 that function as the first positive-phase bit line BL 00 , the second positive-phase bit line BL 10 , the first negative-phase bit line BL 01 and the second negative-phase bit line BL 11 in this order respectively are formed in parallel with the boundary lines between the first P-well area PW 1 , the second P-well area PW 2 and the N-well area NW respectively. Therefore, each bit line length can be reduced. As a result, it is possible to reduce the amount of wiring of the bit lines, which makes it possible to achieve a high-speed accessing.
- the third metal-wiring layers AL 31 and AL 32 that function as the first word line WL 0 and the second word line WL 1 respectively are formed so that these layers are orthogonal with the boundary lines between the first P-well area PW 1 and the second P-well area PW 2 and the N-well area NW respectively. Therefore, each word line length can be reduced. As a result, it is possible to reduce the amount of wiring of the word lines, which makes it possible to achieve a high-speed accessing.
- N-channel type MOS transistors N 1 and N 2 (or N 1 ′ and N 2 ′) are provided in the two different P-well areas, it is possible to take a large width for each transistor. As a result, extraction of bit lines becomes faster, which makes it possible to achieve an access at a higher speed.
- N-channel type MOS transistors N 1 and N 1 ′ (or N 2 and N 2 ′) that function as driver transistors are formed in parallel, it is possible to take a large width W for each transistor. As a result, extraction of bit lines becomes faster, which makes it possible to achieve a reading access at a higher speed.
- drain areas for forming the memory nodes MA and MB are made in a common n + diffusion area, it is possible to reduce the size of these areas. As a result, a parasitic capacitance can be reduced, which makes it possible to achieve a writing access at a higher speed.
- the drain areas for forming the memory nodes MA and MB are made in a common n + diffusion area. Therefore, it is possible to reduce the size of these areas. As a result, a parasitic capacitance can be reduced, which makes it possible to achieve a writing access at a higher speed.
- FIG. 7 is a layout diagram showing a memory cell of the semiconductor memory device of the second embodiment.
- FIG. 7 equivalent to FIG. 2.
- the semiconductor memory device of the second embodiment is characterized by the following. Drain diffusion areas of N-channel type MOS transistors N 3 and N 5 and drain diffusion areas of N-channel type MOS transistors N 1 and N 1 ′ are formed in a P-well area PW 1 by a common n + diffusion area FL 41 . Further, drain diffusion areas of N-channel type MOS transistors N 4 and N 6 and drain diffusion areas of N-channel type MOS transistors N 2 and N 2 ′ are formed in a P-well area PW 2 by a common n + diffusion area FL 42 .
- polysilicon wiring layers PL 51 and PL 52 are formed in place of the polysilicon wiring layers PL 11 and PL 12 shown in FIG. 2.
- the layouts of other upper-layer metal-wiring layers are similar to those shown in FIG. 3 to FIG. 5, and therefore, their explanation will be omitted.
- N-channel type MOS transistors N 1 ′ and N 2 ′ can be omitted from both the first and second embodiments.
- FIG. 8 shows an equivalent circuit of the semiconductor memory device of the third embodiment.
- a P-channel type MOS transistor P 1 and an N-channel type MOS transistor N 1 constitute a first CMOS inverter.
- a P-channel type MOS transistor P 2 and an N-channel type MOS transistor N 2 constitute a second CMOS inverter. Input/output terminals of these CMOS inverters are connected in cross.
- these MOS transistors P 1 , P 2 , N 1 , and N 2 constitute a flip-flop circuit.
- FIG. 8 it is possible to carry out a writing and a reading in a logic state in a memory node MA which is an output point of the first CMOS inverter and input point of the second CMOS inverter, and in a memory node MB which is an output point of the second CMOS inverter and input point of the first CMOS inverter.
- N-channel type MOS transistors N 3 and N 4 function as access gates respectively.
- the gate of the N-channel type MOS transistor N 3 is connected to a first word line WWL
- the source is connected to the memory node MA
- the drain is connected to a first positive-phase bit line WBL 1 .
- the gate of the N-channel type MOS transistor N 4 is connected to the first word line WWL
- the source is connected to the memory node MA
- the gate is connected to a negative-phase bit line WBL 2 .
- the gate of the N-channel type MOS transistor N 8 is connected to the memory node MA, and the source of the N-channel type MOS transistor N 8 is grounded. Further, the drain of the N-channel type MOS transistor N 8 is connected to the source of an N-channel type MOS transistor N 9 .
- the gate of the N-channel type MOS transistor N 9 is connected to the second word line RWL, and the drain is connected to a second positive-phase bit line RBL.
- FIG. 8 The equivalent circuit itself shown in FIG. 8 has a known structure as the conventional two-port SRAM cell.
- FIG. 9 to FIG. 12 are layout diagrams of the memory cell of the semiconductor memory device of the third embodiment.
- FIG. 6 explains various symbols like a contact hole, a via hole, etc. shown in FIG. 9 to FIG. 12.
- FIG. 9 shows layers including well areas formed on a semiconductor substrate, diffusion areas formed in the well areas, and a polysilicon wiring layer formed on the upper surface.
- a first P-well area PW 1 and a second P-well area PW 2 by sandwiching the N-well area NW in a plain direction on the semiconductor substrate, as shown in FIG. 9, in a similar manner to that of the first embodiment. Further, these well areas are formed so that the first well boundary line and the second well boundary line are parallel with each other. Although not shown in FIG. 9, there exist a separation area between the N-well area NW and the first P-well area PW 1 and between the N-well area NW and the second P-well area PW 2 respectively.
- the N-channel type MOS transistors N 1 and N 3 shown in FIG. 8 are formed in the first P-well area PW 1 .
- the P-channel type MOS transistors P 1 and P 2 shown in FIG. 8 are formed in the N-well area NW.
- the N-channel type MOS transistors N 2 , N 4 , N 8 and N 9 shown in FIG. 8 are formed in the second P-well area PW 2 .
- a polysilicon wiring layer PL 21 is formed in the first P-well area PW 1 , extending in a direction perpendicular to the first well boundary line.
- a polysilicon wiring layer PL 11 is disposed in the area from the first P-well area PW 1 to the N-well area NW, extending in a straight line in a direction perpendicular to the first well boundary line.
- One end of the polysilicon wiring layer PL 11 is positioned on the second well boundary line as shown in FIG. 9.
- n + diffusion areas FL 22 and FL 23 in the first P-well area PW 1 by injecting an N-type impurity at positions sandwiching the polysilicon wiring layer PL 21 .
- an N-channel type MOS transistor N 3 that uses the polysilicon wiring layer PL 21 as a gate electrode.
- n + diffusion areas FL 21 and FL 22 are formed at positions sandwiching the polysilicon wiring layer PL 11 .
- an N-channel type MOS transistor N 1 that uses the polysilicon wiring layer PL 11 as a gate electrode.
- the polysilicon wiring layers PL 11 and PL 21 are disposed in parallel in the N-channel type MOS transistors N 1 and N 3 respectively, it is possible to dispose the n + diffusion areas FL 21 to FL 23 in a direction parallel with the first well boundary line and also in a straight line.
- the N-channel type MOS transistors N 1 and N 3 can share the n + diffusion area FL 22 .
- the sharing of this n + diffusion area FL 22 makes it possible to connect the drain of the N-channel type MOS transistors N 1 and the source of the N-channel type MOS transistors N 3 together, and also contributes to reduce the area occupied by the N-channel type MOS transistors N 1 and N 3 , according to the equivalent circuit shown in FIG. 8.
- two polysilicon wiring layers PL 31 and PL 33 are disposed in the second P-well area PW 2 , extending in a direction perpendicular to the second well boundary line. Further, a polysilicon wiring layer PL 12 is formed in the area from the second P-well area PW 2 to the N-well area NW, extending in a direction perpendicular to the second well boundary line. One end of the polysilicon wiring layer PL 12 is positioned on the first well boundary line as shown in FIG. 9.
- n + diffusion areas FL 36 and FL 35 by injecting an N-type impurity at positions sandwiching the polysilicon wiring layer PL 33 .
- an N-channel type MOS transistor N 4 that uses the polysilicon wiring layer PL 33 as a gate electrode.
- n + diffusion areas FL 34 and FL 35 are formed at positions sandwiching the polysilicon wiring layer PL 12 .
- an N-channel type MOS transistor N 2 that uses the polysilicon wiring layer PL 12 as a gate electrode.
- the polysilicon wiring layers PL 33 and PL 12 are disposed in parallel in the N-channel type MOS transistors N 2 and N 4 respectively, it is possible to dispose the n + diffusion areas FL 34 to FL 36 in a direction parallel with the second well boundary line and also in a straight line.
- the N-channel type MOS transistors N 2 and N 4 can share the n + diffusion area FL 35 .
- the sharing of this n + diffusion area FL 35 makes it possible to connect the drain of the N-channel type MOS transistors N 2 and the source of the N-channel type MOS transistors N 4 together, and also contributes to reduce the area occupied by the N-channel type MOS transistors N 2 and N 4 , according to the equivalent circuit shown in FIG. 8.
- n + diffusion areas FL 33 and FL 32 are formed by injecting an N-type impurity at positions sandwiching the polysilicon wiring layer PL 31 .
- an N-channel type MOS transistor N 9 that uses the polysilicon wiring layer PL 31 as a gate electrode.
- n + diffusion areas FL 32 and FL 31 are formed at positions sandwiching the polysilicon wiring layer PL 12 .
- an N-channel type MOS transistor N 8 that uses the polysilicon wiring layer PL 12 as a gate electrode.
- N-channel type MOS transistors N 8 and N 9 have the polysilicon wiring layer PL 31 and PL 12 disposed in parallel with each other. Therefore, it is possible to dispose the n + diffusion areas FL 31 to FL 33 in a direction parallel with the second well boundary line and also in a straight line. With this arrangement, the N-channel type MOS transistors N 8 and N 9 can share the n + diffusion area FL 32 . The sharing of this n + diffusion area FL 32 makes it possible to connect the drain of the N-channel type MOS transistors N 8 and the source of the N-channel type MOS transistor N 9 together, and also contributes to reduce the area occupied by the N-channel type MOS transistors N 8 and N 9 , according to the equivalent circuit shown in FIG. 8.
- p + diffusion areas FL 11 and FL 12 are formed by injecting a P-type impurity at positions sandwiching the polysilicon wiring layer PL 11 .
- p + diffusion areas FL 13 and FL 14 are formed at positions sandwiching the polysilicon wiring layer PL 12 .
- P-channel type MOS transistor P 2 that uses the polysilicon wiring layer PL 12 as a gate electrode.
- Positions of the P-channel type MOS transistors P 1 and P 2 are determined based on the positions of the polysilicon wiring layers PL 11 and PL 12 .
- Distance between the polysilicon wiring layers PL 11 and PL 12 can be reduced to about the size of the p + diffusion area FL 12 or the FL 13 (minimum pitch of the transistor) as shown in FIG. 9, like in the first embodiment.
- the sizes of the p + diffusion areas FL 12 and FL 13 are set approximately equal to the sizes of the n + diffusion area FL 22 in the first P-well area PW 1 and the n + diffusion areas FL 32 and FL 35 in the second P-well area PW 2 , it is possible to minimize the total area required for the layout of the memory cell.
- the above arrangement also means that it is possible to dispose the polysilicon wiring layers PL 11 , PL 33 and PL 31 on the same straight line, and it is also possible to dispose the polysilicon wiring layers PL 21 and PL 12 on the same straight line.
- FIG. 10 shows layers including first metal-wiring layers formed on the layers shown in FIG. 9.
- a first metal-wiring layer AL 11 for electrically connecting the lower-layer n + diffusion area FL 22 , the p + diffusion area FL 12 , and the polysilicon wiring layer PL 12 .
- This first metal-wiring layer AL 11 makes it possible to connect the drain of the N-channel type MOS transistors N 1 , the source of the N-channel type MOS transistor N 3 , the drain of the P-channel type MOS transistor P 1 , and the input terminal of the second CMOS inverter, according to the equivalent circuit shown in FIG. 8.
- first metal-wiring layer AL 12 for electrically connecting between the lower-layer n + diffusion area FL 35 , the p + diffusion area FL 13 , and the polysilicon wiring layer PL 11 .
- This second metal-wiring layer AL 12 makes it possible to connect between the drain of the N-channel type MOS transistor N 2 , the sources of the N-channel type MOS transistor N 4 , the drain of the P-channel type MOS transistor P 2 , and the input terminal of the first CMOS inverter, according to the equivalent circuit shown in FIG. 8.
- the contact points of the n + diffusion area FL 22 and the p + diffusion area FL 12 are disposed on the same straight line as described above. Therefore, it is possible to form a wire for connecting between these two points in a straight-line shape.
- the above similarly applies to the first metal-wiring layer AL 12 .
- first metal-wiring layer AL 15 for moving the connection point of the lower-layer p + diffusion area FL 11
- first metal-wiring layer AL 16 for moving the connection point of the p + diffusion area FL 14
- first metal-wiring layer AL 13 for moving the connection point of the lower-layer polysilicon wiring layer PL 21
- first metal-wiring layer AL 14 for moving the connection point of the polysilicon wiring layer PL 31
- first metal-wiring layer AL 19 for moving the connection point of the polysilicon wiring layer PL 33 .
- first metal-wiring layer AL 18 for electrically connecting the lower-layer p + diffusion areas FL 34 and FL 31 , and for moving the connection point with the upper layer.
- This first metal-wiring layer AL 18 makes it possible to connect the sources of the N-channel type MOS transistors N 2 and N 8 together, according to the equivalent circuit shown in FIG. 8.
- the n + diffusion areas FL 34 and FL 31 are disposed on the same straight line perpendicular to the second well boundary line. Therefore, the contact holes on these n + diffusion area scan also be formed on the same straight line on which a straight line connecting between these contact holes is perpendicular to the second well boundary line. In other words, it is possible to form the second metal-wiring layer AL 18 shown in FIG. 10 in a straight-line shape perpendicular to the second well boundary line.
- FIG. 11 shows layers including second metal-wiring layers formed on the layers shown in FIG. 10.
- a second metal-wiring layer AL 21 for applying a power source potential VDD to the p + diffusion area FL 11 via the first metal-wiring layer AL 15 shown in FIG. 10 and for applying a power source potential VDD to the p + diffusion area FL 14 via the first metal-wiring layer AL 16 .
- the second metal-wiring layer AL 21 functions as a power source potential VDD line, and achieves a connection between the source of the P-channel type MOS transistor P 1 and the power source and a connection between the source of the P-channel type MOS transistor P 2 and the power source, in the equivalent circuit shown in FIG. 8.
- a second metal-wiring layer AL 22 for applying a ground potential GND to the p + diffusion area FL 21 via a first metal wiring layer AL 17 shown in FIG. 10
- a second metal-wiring layer AL 23 for applying a ground potential GND to the p + diffusion areas FL 31 and FL 34 respectively via a first metal wiring layer AL 18 shown in FIG. 10.
- the second metal-wiring layers AL 22 and AL 23 function as a ground potential GND line respectively, and achieve a grounding of each source of the N-channel type MOS transistors N 1 , N 2 and N 8 respectively, in the equivalent circuit shown in FIG. 8.
- a second metal-wiring layer AL 24 that is connected with the lower-layer p + diffusion area FL 23 and functions as a first positive-phase bit line WBL 1
- a second metal-wiring layer AL 25 that is connected with the p + diffusion area FL 36 and functions as a negative-phase bit line WBL 2
- a second metal-wiring layer AL 26 that is connected with the p + diffusion area FL 33 and functions as a second positive-phase bit line RBL, via the contact holes and the first via holes shown in FIG. 10 respectively.
- these second metal-wiring layers AL 24 to AL 26 achieve a connection between the other semiconductor terminal end (drain) of the N-channel type MOS transistor N 3 and the first positive-phase bit line WBL 1 , a connection between the other semiconductor terminal end (drain) of the N-channel type MOS transistor N 4 and the negative-phase bit line WBL 2 , and a connection between the other semiconductor terminal end (drain) of the N-channel type MOS transistor N 9 and the second positive-phase bit line RBL, respectively, in the equivalent circuit shown in FIG. 8.
- the second metal-wiring layers AL 24 to AL 26 in a straight-line shape respectively extending in a direction parallel with the first well boundary line. This means that it is possible to further reduce the length of each of the first positive-phase bit line WBL 1 , the negative-phase bit line WBL 2 , and the second positive-phase bit line RBL, within one memory cell.
- a second metal-wiring layer AL 27 for moving the connection point between the lower-layer first metal wiring layer AL 13 and the upper layer
- a second metal-wiring layer AL 28 for moving the connection point between the lower-layer first metal wiring layer AL 19 and the upper layer
- a second metal-wiring layer AL 29 for moving the connection point between the lower-layer first metal wiring layer AL 14 and the upper layer.
- FIG. 12 shows layers including third metal-wiring layers formed on the layers shown in FIG. 11.
- a third metal-wiring layer AL 31 for electrically connecting the polysilicon wiring layers PL 21 and PL 33 via the first metal wiring layer AL 13 and the second metal wiring layer AL 27 and also for functioning as a word line WWL.
- the third metal-wiring layer AL 31 achieves a connection between the gates of the N-channel type MOS transistors N 3 and N 4 and the word line WWL, in the equivalent circuit shown in FIG. 8.
- a third metal-wiring layer AL 32 for electrically connecting with the polysilicon wiring layer PL 31 via the first metal wiring layer AL 14 and the second metal wiring layer AL 29 and for functioning as a word line RWL.
- the third metal-wiring layer AL 32 achieves a connection between the gate of the N-channel type MOS transistor N 6 and the word line RWL, in the equivalent circuit shown in FIG. 8.
- these metal wiring layers can be connected by a straight-line shaped metal wiring layer extending in a direction perpendicular to the first well boundary line.
- the third metal wiring layer AL 31 shown in FIG. 12 in a straight-line shape extending in a direction perpendicular to the first well boundary line.
- the third metal wiring layer AL 32 is connected with only the second metal wiring layer AL 29 as a lower layer, it is possible to dispose the third metal wiring layer AL 32 in the extension parallel with the third metal wiring layer AL 31 . This means that it is possible to further reduce the length of each of the first word line WWL and the second word line RWL within one memory cell.
- the N-channel type MOS transistor N 3 that functions as an access gate and the N-channel type MOS transistor N 1 that structures a flip-flop circuit share the n + diffusion area FL 22 at a connection point between respective semiconductor terminals.
- the n + diffusion areas FL 21 to FL 23 that become the respective semiconductor terminals are formed on the same straight line parallel with the first well boundary line. Therefore, it is possible to reduce the area occupied by the N-channel type MOS transistors N 1 and N 3 . This makes it possible to increase the integration degree of the memory cell array.
- the second metal-wiring layers AL 24 to AL 26 that function as the first positive-phase bit line WBL 1 , the negative-phase bit line WBL 2 , and the first positive-phase bit line WBL 2 in this order respectively are formed in parallel with the first and second well boundary lines respectively. Therefore, each bit line length can be reduced. As a result, it is possible to reduce the amount of wiring of the bit lines, which makes it possible to achieve a high-speed accessing. Particularly, each bit line length can be reduced to a double of the minimum pitch of the transistors based on the above arrangement.
- the third metal-wiring layers AL 31 and AL 32 that function as the first word line WWL and the second word line RWL respectively are formed so that these layers are orthogonal with the first and second well boundary lines respectively. Therefore, each word line length can be reduced. As a result, it is possible to reduce the amount of wiring of the word lines, which makes it possible to achieve a high-speed accessing.
- drain areas for forming the memory nodes MA and MB are made in a common n + diffusion area, it is possible to reduce the size of these areas. As a result, a parasitic capacitance can be reduced, which makes it possible to achieve a writing access at a higher speed.
- the polysilicon layer can be formed in a straight line, it is possible to take a large process margin for a mask deviation or the like at the time of forming a layout pattern, in the process of manufacturing a semiconductor device.
- FIG. 13 shows an equivalent circuit of the semiconductor memory device of the fourth embodiment.
- a first word line WWL a first positive-phase bit line WBL 1
- a first negative-phase bit line WBL 2 a first word line
- P-channel type MOS transistors P 1 and P 2 a first negative-phase bit line
- the gate of the N-channel type MOS transistor N 8 is connected to the memory node MA, and the source of the N-channel type MOS transistor N 8 is grounded. Further, the drain of the N-channel type MOS transistor N 8 is connected to the source of the N-channel type MOS transistor N 9 .
- the gate of the N-channel type MOS transistor N 9 is connected to a second word line RWL 1 , and the drain is connected to a second positive-phase bit line RBL 1 .
- the gate of the N-channel type MOS transistor N 10 is connected to the memory node MB, and the source of the N-channel type MOS transistor N 10 is grounded. Further, the drain of the N-channel type MOS transistor N 10 is connected to the source of an N-channel type MOS transistor N 11 . The gate of the N-channel type MOS transistor N 11 is connected to a third word line RWL 2 , and the drain is connected to a second negative-phase bit line RBL 2 .
- the read operation based on the second and third ports has a characteristic in that this operation can be carried out completely independent of the first port, without destroying the data of the memory nodes MA and MB of the memory cell.
- FIG. 14 to FIG. 17 are layout diagrams of the memory cell of the semiconductor memory device of the fourth embodiment.
- FIG. 6 explains various symbols like a contact hole, a via hole, etc. shown in FIG. 14 to FIG. 17.
- FIG. 14 shows layers including well areas formed on a semiconductor substrate, diffusion areas formed in the well areas, and a polysilicon wiring layer formed on the upper surface.
- first P-well area PW 1 and a second P-well area PW 2 by sandwiching the N-well area NW in a plain direction on the semiconductor substrate, as shown in FIG. 14, in a similar manner to that of the first embodiment. Further, these well areas are formed so that the first well boundary line and the second well boundary line are parallel with each other. Although not shown in FIG. 14, there exist a separation area between the N-well area NW and the first P-well area PW 1 and between the N-well area NW and the second P-well area PW 2 respectively.
- the N-channel type MOS transistors N 1 , N 3 , N 10 and N 11 shown in FIG. 13 are formed in the first P-well area PW 1 .
- the P-channel type MOS transistors P 1 and P 2 shown in FIG. 13 are formed in the N-well area NW.
- the N-channel type MOS transistors N 2 , N 4 , N 8 and N 9 shown in FIG. 13 are formed in the second P-well area PW 2 .
- each layer shown in FIG. 14 to FIG. 17 will be explained in sequence.
- two polysilicon wiring layers PL 21 and PL 22 are formed in the first P-well area PW 1 , extending in parallel in a direction perpendicular to the first well boundary line.
- a polysilicon wiring layer PL 11 is disposed in the area from the first P-well area PW 1 to the N-well area NW, extending in a straight line in a direction perpendicular to the first well boundary line.
- One end of the polysilicon wiring layer PL 11 is positioned on the second well boundary line as shown in FIG. 14.
- n + diffusion areas FL 22 and FL 23 by injecting an N-type impurity at positions sandwiching the polysilicon wiring layer PL 21 .
- an N-channel type MOS transistor N 3 that uses the polysilicon wiring layer PL 21 as a gate electrode.
- n + diffusion areas FL 21 and FL 22 are formed at positions sandwiching the polysilicon wiring layer PL 11 .
- an N-channel type MOS transistor N 1 that uses the polysilicon wiring layer PL 11 as a gate electrode.
- the polysilicon wiring layers PL 11 and PL 21 are disposed in parallel in the N-channel type MOS transistors N 1 and N 3 respectively, it is possible to dispose the n + diffusion areas FL 21 to FL 23 in a direction parallel with the first well boundary line and also in a straight line.
- the N-channel type MOS transistors N 1 and N 3 can share the n + diffusion area FL 22 .
- the sharing of this n + diffusion area FL 22 makes it possible to connect the drain of the N-channel type MOS transistors N 1 and the source of the N-channel type MOS transistors N 3 together, and also contributes to reduce the area occupied by the N-channel type MOS transistors N 1 and N 3 , according to the equivalent circuit shown in FIG. 13.
- n + diffusion areas FL 25 and FL 26 by injecting an N-type impurity at positions sandwiching the polysilicon wiring layer PL 22 .
- an N-channel type MOS transistor N 11 that uses the polysilicon wiring layer PL 22 as a gate electrode.
- n + diffusion areas FL 24 and FL 25 are formed at positions sandwiching the polysilicon wiring layer PL 11 .
- an N-channel type MOS transistor N 10 that uses the polysilicon wiring layer PL 11 as a gate electrode.
- the polysilicon wiring layers PL 22 and PL 11 are disposed in parallel in the N-channel type MOS transistors N 10 and N 11 respectively, it is possible to dispose the n + diffusion areas FL 24 to FL 26 in a direction parallel with the first well boundary line and also in a straight line. With this arrangement, the N-channel type MOS transistors N 10 and N 11 can share the n + diffusion area FL 25 . The sharing of this n + diffusion area FL 25 makes it possible to connect the drain of the N-channel type MOS transistors N 10 and the source of the N-channel type MOS transistors N 11 together, and also contributes to reduce the area occupied by the N-channel type MOS transistors N 10 and N 11 , according to the equivalent circuit shown in FIG. 13.
- the polysilicon wiring layers PL 11 , PL 33 and PL 31 are disposed on the same straight line, and the polysilicon wiring layers PL 21 , PL 22 and PL 12 are disposed on the same straight line.
- FIG. 15 shows layers including first metal-wiring layers formed on the layers shown in FIG. 14.
- the formation of the second metal wiring layers in the second P-well area PW 2 and the N-well area NW is as explained in the third embodiment with reference to FIG. 10. Therefore, their explanation will be omitted here.
- first metal-wiring layer AL 11 for electrically connecting the lower-layer n + diffusion area FL 22 , the p + diffusion area FL 12 , and the polysilicon wiring layer PL 12 .
- This first metal-wiring layer AL 11 makes it possible to connect the drain of the N-channel type MOS transistors N 1 , the source of the N-channel type MOS transistor N 3 , the drain of the P-channel type MOS transistor P 1 , and the input terminal of the second CMOS inverter, according to the equivalent circuit shown in FIG. 13.
- the contact points of the n + diffusion area FL 22 and the p + diffusion area FL 12 are disposed on the same straight line as described above. Therefore, it is possible to form a wire for connecting between these two points in a straight-line shape.
- first metal-wiring layer AL 13 for moving the connection point of the lower-layer polysilicon wiring layer PL 22
- first metal-wiring layer AL 10 for moving the connection point of the polysilicon wiring layer PL 21 .
- first metal-wiring layer AL 17 for electrically connecting the lower-layer p + diffusion areas FL 24 and FL 21 , and for moving the connection point with the upper layer.
- This first metal-wiring layer AL 17 makes it possible to connect the sources of the N-channel type MOS transistors N 1 and N 10 together, according to the equivalent circuit shown in FIG. 13.
- the n + diffusion areas FL 24 and FL 21 are disposed on the same straight line perpendicular to the first well boundary line. Therefore, the contact holes on these n + diffusion areas can also be formed on the same straight line on which a straight line connecting between these contact holes is perpendicular to the first well boundary line. In other words, it is possible to form the second metal-wiring layer AL 17 shown in FIG. 15 in a straight-line shape perpendicular to the first well boundary line.
- FIG. 16 shows layers including second metal-wiring layers formed on the layers shown in FIG. 15.
- a second metal-wiring layer AL 21 for applying a power source potential VDD to the p + diffusion area FL 11 via the first metal-wiring layer AL 15 shown in FIG. 15 and for applying a power source potential VDD to the p + diffusion area FL 14 via the first metal-wiring layer AL 16 .
- the second metal-wiring layer AL 21 functions as a power source potential VDD line, and achieves a connection between the source of the P-channel type MOS transistor P 1 and the power source and a connection between the source of the P-channel type MOS transistor P 2 and the power source, in the equivalent circuit shown in FIG. 13.
- a second metal-wiring layer AL 22 for applying a ground potential GND to the p + diffusion areas FL 21 and FL 24 via a first metal wiring layer AL 17 shown in FIG. 15, and a second metal-wiring layer AL 23 for applying a ground potential GND to the p + diffusion areas FL 31 and FL 34 respectively via a first metal wiring layer AL 18 shown in FIG. 15.
- the second metal-wiring layers AL 22 and AL 23 function as a ground potential GND line respectively, and achieve a grounding of each source of the N-channel type MOS transistors N 1 , N 2 , N 8 and N 10 respectively, in the equivalent circuit shown in FIG. 13.
- a second metal-wiring layer AL 24 that is connected with the lower-layer p + diffusion area FL 23 and functions as a first positive-phase bit line WBL 1
- a second metal-wiring layer AL 42 that is connected with the lower-layer p + diffusion area FL 26 and functions as a second negative-phase bit line RBL 2
- a second metal-wiring layer AL 25 that is connected with the p + diffusion area FL 36 and functions as a negative-phase bit line WBL 2
- a second metal-wiring layer AL 26 that is connected with the p + diffusion area FL 33 and functions as a second positive-phase bit line RBL 1 , via the contact holes and the first via holes shown in FIG. 15 respectively.
- these second metal-wiring layers AL 24 to AL 26 and AL 42 achieve a connection between the other semiconductor terminal end (drain) of the N-channel type MOS transistor N 3 and the first positive-phase bit line WBL 1 , a connection between the other semiconductor terminal end (drain) of the N-channel type MOS transistor N 4 and the negative-phase bit line WBL 2 , a connection between the other semiconductor terminal end (drain) of the N-channel type MOS transistor N 9 and the second positive-phase bit line RBL 1 , and a connection between the other semiconductor terminal end (drain) of the N-channel type MOS transistor N 11 and the second negative-phase bit line RBL 2 , respectively, in the equivalent circuit shown in FIG. 13.
- the second metal-wiring layers AL 24 to AL 26 and AL 42 in a straight-line shape respectively extending in a direction parallel with the first well boundary line. This means that it is possible to further reduce the length of each of the first positive-phase bit line WBL 1 , the negative-phase bit line WBL 2 , the second positive-phase bit line RBL 1 , and the second negative-phase bit line RBL 2 within one memory cell.
- a second metal-wiring layer AL 41 for moving the connection point between the lower-layer first metal wiring layer AL 13 and the upper layer
- a second metal-wiring layer AL 28 for moving the connection point between the lower-layer first metal wiring layer AL 19 and the upper layer
- a second metal-wiring layer AL 27 for moving the connection point between the lower-layer first metal wiring layer AL 10 and the upper layer.
- a second metal-wiring layer AL 29 for connecting between the polysilicon wiring layer PL 31 and the upper layer via the lower-layer first metal wiring layer AL 14 .
- FIG. 17 shows layers including third metal-wiring layers formed on the layers shown in FIG. 16.
- a third metal-wiring layer AL 31 for electrically connecting the polysilicon wiring layers PL 21 and PL 33 via the first metal wiring layer AL 10 and the second metal wiring layer AL 27 and also for functioning as a first word line WWL.
- the third metal-wiring layer AL 31 achieves a connection between the gates of the N-channel type MOS transistors N 3 and N 4 and the first word line WWL, in the equivalent circuit shown in FIG. 13.
- a third metal-wiring layer AL 32 for electrically connecting with the polysilicon wiring layer PL 31 via the first metal wiring layer AL 14 and the second metal wiring layer AL 29 and for functioning as a second word line RWL 1 .
- the third metal-wiring layer AL 32 achieves a connection between the gate of the N-channel type MOS transistor N 6 and the second word line RWL 1 , in the equivalent circuit shown in FIG. 13.
- a third metal-wiring layer AL 33 for electrically connecting with the polysilicon wiring layer PL 22 via the first metal wiring layer AL 13 and the second metal wiring layer AL 41 and for functioning as a third word line RWL 2 .
- the third metal-wiring layer AL 33 achieves a connection between the gate of the N-channel type MOS transistor N 11 and the third word line RWL 2 , in the equivalent circuit shown in FIG. 13.
- these metal wiring layers can be connected by a straight-line shaped metal wiring layer extending in a direction perpendicular to the first well boundary line.
- the third metal wiring layer AL 31 shown in FIG. 17 in a straight-line shape extending in a direction perpendicular to the first well boundary line.
- the third metal wiring layer AL 32 is connected with only the second metal wiring layer AL 29 as a lower layer
- the third metal wiring layer AL 33 is connected with only the second metal wiring layer AL 41 as a lower layer. Therefore, it is possible to dispose these third metal wiring layers in the extension parallel with the third metal wiring layer AL 31 . This means that it is possible to further reduce the length of each of the first word line WWL, the second word line RWL 1 , and the third word line RWL 2 , within one memory cell.
- FIG. 18 shows an equivalent circuit of the semiconductor memory device of the fifth embodiment.
- the equivalent circuit shown in FIG. 18 is different from that of the fourth embodiment only in that the gates of the N-channel type MOS transistors N 9 and N 11 are connected together, and the connection line is used as a common second word line RWL, in the equivalent circuit shown in FIG. 13. All other structures are as shown in FIG. 13, and therefore, their explanation will be omitted here.
- the operation is also similar to that of the equivalent circuit shown in FIG. 13 except that the read operation is carried out based on the difference between the potential of the second positive-phase bit line RBL 1 and the potential of the second negative-phase bit line RBL 2 .
- the layout structure is different only in the second metal wiring layer corresponding to that shown in FIG. 16 and the third metal wiring layer corresponding to that shown in FIG. 17. All other lower-layer structures are as shown in FIG. 14 and FIG. 15. Therefore, their explanation will be omitted here.
- FIGS. 19 and 20 are layout diagrams of the memory cell of the semiconductor memory device in the fifth embodiment. Particularly, FIG. 19 shows a layer including the second metal wiring layer corresponding to that shown FIG. 16. FIG. 20 shows a layer including the third metal wiring layer corresponding to that shown FIG. 17.
- a second metal-wiring layer AL 21 for applying a power source potential VDD to the p + diffusion area FL 11 via the first metal-wiring layer AL 15 shown in FIG. 15 and for applying a power source potential VDD to the p + diffusion area FL 14 via the first metal-wiring layer AL 16 .
- the second metal-wiring layer AL 21 functions as a power source potential VDD line, and achieves a connection between the source of the P-channel type MOS transistor P 1 and the power source and a connection between the source of the P-channel type MOS transistor P 2 and the power source, in the equivalent circuit shown in FIG. 18.
- a second metal-wiring layer AL 22 for applying a ground potential GND to the p + diffusion areas FL 21 and FL 24 via a first metal wiring layer AL 17 shown in FIG. 15, and a second metal-wiring layer AL 23 for applying a ground potential GND to the p + diffusion areas FL 31 and FL 34 respectively via a first metal wiring layer AL 18 shown in FIG. 15.
- the second metal-wiring layers AL 22 and AL 23 function as a ground potential GND line respectively, and achieve a grounding of each source of the N-channel type MOS transistors N 1 , N 2 , N 8 and N 10 respectively, in the equivalent circuit shown in FIG. 18.
- a second metal-wiring layer AL 24 that is connected with the lower-layer p + diffusion area FL 23 and functions as a first positive-phase bit line WBL 1
- a second metal-wiring layer AL 42 that is connected with the lower-layer p + diffusion area FL 26 and functions as a second negative-phase bit line RBL 2
- a second metal-wiring layer AL 25 that is connected with the p + diffusion area FL 36 and functions as a negative-phase bit line WBL 2
- a second metal-wiring layer AL 26 that is connected with the p + diffusion area FL 33 and functions as a second positive-phase bit line RBL 1 , via the contact holes and the first via holes shown in FIG. 15 respectively.
- these second metal-wiring layers AL 24 to AL 26 and AL 42 achieve a connection between the other semiconductor terminal end (drain) of the N-channel type MOS transistor N 3 and the first positive-phase bit line WBL 1 , a connection between the other semiconductor terminal end (drain) of the N-channel type MOS transistor N 4 and the negative-phase bit line WBL 2 , a connection between the other semiconductor terminal end (drain) of the N-channel type MOS transistor N 9 and the second positive-phase bit line RBL 1 , and a connection between the other semiconductor terminal end (drain) of the N-channel type MOS transistor N 11 and the second negative-phase bit line RBL 2 , respectively, in the equivalent circuit shown in FIG. 18.
- the second metal-wiring layers AL 24 to AL 26 and AL 42 in a straight-line shape respectively extending in a direction parallel with the first well boundary line. This means that it is possible to further reduce the length of each of the first positive-phase bit line WBL 1 , the negative-phase bit line WBL 2 , the second positive-phase bit line RBL 1 , and the second negative-phase bit line RBL 2 within one memory cell.
- a second metal-wiring layer AL 41 for moving the connection point between the lower-layer first metal wiring layer AL 13 and the upper layer
- a second metal-wiring layer AL 28 for moving the connection point between the lower-layer first metal wiring layer AL 19 and the upper layer
- a second metal-wiring layer AL 27 for moving the connection point between the lower-layer first metal wiring layer AL 10 and the upper layer.
- a second metal-wiring layer AL 29 for connecting between the polysilicon wiring layer PL 31 and the upper layer via the lower-layer first metal wiring layer AL 14 .
- FIG. 20 shows layers including third metal-wiring layers formed on the layers shown in FIG. 19.
- a third metal-wiring layer AL 31 for electrically connecting the polysilicon wiring layers PL 21 and PL 33 via the first metal wiring layer AL 10 and the second metal wiring layer AL 27 and also for functioning as a first word line WWL.
- the third metal-wiring layer AL 31 achieves a connection between the gates of the N-channel type MOS transistors N 3 and N 4 and the first word line WWL, in the equivalent circuit shown in FIG. 18.
- a third metal-wiring layer AL 32 for electrically connecting between the polysilicon wiring layers PL 22 and PL 31 via the first metal wiring layer AL 14 and the second metal wiring layer AL 29 and for functioning as a second word line RWL.
- the third metal-wiring layer AL 32 achieves a connection between the gates of the N-channel type MOS transistor N 9 and N 11 and the second word line RWL, in the equivalent circuit shown in FIG. 18.
- these metal wiring layers can be connected by a straight-line shaped metal wiring layer extending in a direction perpendicular to the first well boundary line.
- the third metal wiring layer AL 31 shown in FIG. 20 in a straight-line shape extending in a direction perpendicular to the first well boundary line.
- the first, third and fifth N-channel type MOS transistors that are electrically connected to the positive-phase bit line and the second, fourth and sixth N-channel type MOS transistors that are connected to the negative-phase bit line are formed in the divided P-well areas respectively. Therefore, when these well areas are disposed in a direction perpendicular to the positive-phase and negative-phase bit lines respectively, it is possible to use a layout having a short length for the bit lines. As a result, there is an effect that it is possible to achieve a high-speed accessing.
- first and second P-well areas are formed on the two sides of the N-well area, it is possible to make uniform the distances of wiring connection between the N-channel type MOS transistors formed in the first and second P-well areas respectively and the P-channel type MOS transistors formed in the N-well area. As a result, there is an effect that it is possible to employ an optimum layout for a shortest wiring.
- bit lines are parallel with the boundary lines between the first and second P-well areas and the N-well area respectively. Therefore, it is possible to provide a layout having each bit line formed in a shortest length by taking into consideration a reduction in the length of each word line.
- each word line is perpendicular to the boundary lines between the first and second P-well areas and the N-well area respectively. Therefore, it is possible to provide a layout having each word line formed in a shortest length by taking into consideration a reduction in the length of each bit line with priority.
- first P-channel type MOS transistor and the gate areas of the first, third and fourth N-channel type MOS transistors are formed to be positioned on the same straight line, it is possible to form wires for connecting between the gates in a straight-line shape.
- second P-channel type MOS transistor and the gate areas of the second, fifth and sixth N-channel type MOS transistors are also formed to be positioned on the same straight line, it is possible to form wires for connecting between the gates in a straight-line shape. As a result, there is an effect that it is possible to obtain shorter wiring.
- each source and each drain of the third and fifth N-channel type MOS transistors that function as an access gate are positioned on the same straight line, it is possible to reduce the disposition distance between the third and fifth N-channel type MOS transistors.
- each source and each drain of the fourth and sixth N-channel type MOS transistors are also positioned on the same straight line, it is possible to reduce the disposition distance between the fourth and sixth N-channel type MOS transistors. As a result, there is an effect that it is possible to improve the degree of integration of the memory cell.
- drain diffusion areas are formed in a common n + diffusion area for the third and fifth N-channel type MOS transistors and for the fourth and sixth N-channel type MOS transistors respectively, it is possible to reduce the size of the n + diffusion areas. As a result, there is an effect that it is possible to reduce a parasitic capacitance due to the n + diffusion area.
- the drain diffusion area of the first N-channel type MOS transistor and the drain diffusion areas of the third and fifth N-channel type MOS transistors are connected to each other by the upper-layer first metal-wiring layer
- the drain diffusion area of the second N-channel type MOS transistor and the drain diffusion areas of the fourth and sixth N-channel type MOS transistors are connected to each other by the upper-layer second metal-wiring layer. Therefore, it is possible to form the first and second metal-wiring layers in a straight-line shape according to the positions of the drain diffusion areas. As a result, there is an effect that it is possible to obtain shorter wiring.
- extension direction of the first and second metal-wiring layers is parallel with an extension direction of each word line, it is possible to optimize the length of the metal-wiring layers like the word lines.
- the extension lines of the bit lines, the power source line and the GND line are perpendicular to each word line. Therefore, it is possible to minimize the respective length of these lines. As a result, there is an effect that it is possible to achieve a high-speed accessing.
- drain diffusion areas are formed in a common n + diffusion area for the first, third and fifth N-channel type MOS transistors and for the second, fourth and sixth N-channel type MOS transistors respectively, it is possible to omit the metal-wiring layers between these drain diffusion areas.
- the first n + diffusion area and the drain diffusion area of the first P-channel type MOS transistor and the second n + diffusion area and the drain diffusion area of the second P-channel type MOS transistor are connected to each other by the upper-layer second metal-wiring layers respectively. Therefore, it is possible to form the metal-wiring layers in a straight-line shape according to the positions of the drain diffusion areas and the n + diffusion areas. As a result, there is an effect that it is possible to obtain shorter wiring.
- first, third, and the fifth N-channel type MOS transistors electrically connected to a positive-phase bit line, and second and fourth N-channel type MOS transistors connected to a negative-phase bit line are formed in separated P-well areas, respectively. Therefore, the juxtaposing direction of these well areas in particular is made perpendicular to the direction of the positive-phase and negative-phase bit lines, which makes it possible to apply a layout with the decreased length of the bitlines. As a result, there is an effect that it is possible to achieve a high-speed accessing.
- the first, third, and fifth N-channel type MOS transistors electrically connected to the positive-phase bit line, and the second, fourth, and seventh N-channel type MOS transistors connected to the negative-phase bit line are formed in the separated P-well areas, respectively. Therefore, the juxtaposing direction of these well areas in particular is made perpendicular to the direction of the positive-phase and negative-phase bit lines, which makes it possible to apply a layout with the decreased length of the bit lines. As a result, there is an effect that it is possible to achieve a high-speed accessing.
- the first, third, and fifth N-channel type MOS transistors electrically connected to the positive-phase bit line, and the second, fourth, and seventh N-channel type MOS transistors connected to the negative-phase bit line are formed in the separated P-well areas, respectively. Therefore, the juxtaposing direction of these well areas in particular is made perpendicular to the direction of the positive-phase and negative-phase bit lines, which makes it possible to apply a layout with the decreased length of the bitlines. As a result, there is an effect that it is possible to achieve a high-speed accessing.
- first and second P-well areas are disposed on both sides of an N-well area, the distances of connection wiring between the N-channel type MOS transistors formed in the first and second P-well areas respectively and the P-channel type MOS transistor formed in the N-well area can be made uniform. As a result, there is an effect that it is possible to employ an optimal layout with further shorter wiring.
- bit lines are parallel with each boundary line between the first and second P-well areas and the N-well area, it is possible to apply a layout with the minimized length of the bit lines when it is considered that the length of the word lines is also decreased.
- the respective gate areas of a first P-channel type MOS transistor, and the first, fourth and sixth N-channel type MOS transistors are formed so as to position on the same straight line. Therefore, the wiring to connect between these gates is formed in a straight-line shape. Further, the respective gate areas of a second P-channel type MOS transistor, and the second, third and fifth N-channel type MOS transistors are formed so as to also position on the same straight line. Therefore, the wiring to connect between these gates is formed in a straight-line shape. As a result, there is an effect that it is possible to obtain shorter wiring.
- respective ones of the semiconductor terminals are formed in a common n + diffusion area for the first and third N-channel type MOS transistors and for the fifth and sixth N-channel type MOS transistors. Therefore, it is possible to reduce an entire n + diffusion area. As a result, there is an effect that it is possible to reduce parasitic capacitance due to the n + diffusion area.
- the second P-channel type MOS transistor, and the second and fifth N-channel type MOS transistors have their respective gate areas connected by a straight line-shaped common polysilicon wiring. Therefore, it is possible to reduce the space between these MOS transistors. As a result, there is an effect that it is possible to improve the scale of integration of the memory cells.
- extension lines of the bit lines, a power source line, and a GND line respectively are perpendicular to each word line. Therefore, it is possible to minimize the length of these lines. As a result, there is an effect that it is possible to achieve a high-speed accessing.
- the respective gate areas of the first P-channel type MOS transistor, and the first, fourth, sixth and seventh N-channel type MOS transistors are formed so as to position on the same straight line. Therefore, it is possible to form the wiring to connect between these gates in a straight-line shape.
- the respective gate areas of the second P-channel type MOS transistor, and the second, third, fifth and eighth N-channel type MOS transistors are formed so as to also position on the same straight line. Therefore, it is possible to form the wiring to connect between these gates in a straight-line shape. As a result, there is an effect that it is possible to obtain shorter wiring.
- the drain of the second N-channel type MOS transistor and the source of the fourth N-channel type MOS transistor are positioned on the same straight line, it is possible to reduce the space between these second and fourth N-channel type MOS transistors.
- the drain of the fifth N-channel type MOS transistor and the source of the sixth N-channel type MOS transistor are also positioned on the same straight line, it is possible to reduce the space between these fifth and sixth N-channel type MOS transistors.
- the drain of the seventh N-channel type MOS transistor and the source of the eighth N-channel type MOS transistor are positioned on the same straight line as well, it is possible to reduce the space between these seventh and eighth N-channel type MOS transistors. As a result, there is an effect that it is possible to improve the scale of integration of the memory cells.
- respective ones of the semiconductor terminals are formed in a common n + diffusion area for the first and third N-channel type MOS transistors, for the fifth and sixth N-channel type MOS transistors, and for the seventh and eighth N-channel type MOS transistors. Therefore, it is possible to reduce an entire n + diffusion area. As a result, there is an effect that it is possible to reduce parasitic capacitance due to the n + diffusion area.
- the second P-channel type MOS transistor, and the second and fifth N-channel type MOS transistors have their respective gate areas connected by a straight line-shaped common polysilicon wiring.
- the first P-channel type MOS transistor, and the first and seventh N-channel type MOS transistors have their respective gate areas connected by a straight line-shaped common polysilicon wiring. Therefore, it is possible to reduce the space between these MOS transistors. As a result, there is an effect that it is possible to improve the scale of integration of the memory cells.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
- The present invention relates to a semiconductor memory device. More particularly this invention relates, to a layout of a multi-port SRAM (Static Random Access Memory) cell having CMOS construction.
- In recent years, there has been an increasing demand for a high-speed processing of electronic devices along with a reduction in weigh and sizes of these devices. The mounting of microcomputers on these electronic devices is now unavoidable. It is also essential to install large-capacity and high-speed processing memories on these microcomputers. Further, along with a rapid distribution of high-performance personal computers, there has also been an increasing demand for large-capacity cache memories. In other words, RAMs that are used by the CPU to execute control programs are required to have a large capacity with high-speed processing.
- DRAM (Dynamic RAM) and SRAM are generally used as a RAM. Particularly, SRAM is generally used for cache memories and the like that require a high-speed processing. The SPAM is known to have a high-resistance load type memory cell and a CMOS type memory cell. The high-resistance load type is constructed of four transistors and two high-resistance elements. The CMOS type is constructed of six transistors. Because of very small leakage current during data holding, the CMOS type SRAM has high reliability and has been used as a main SRAM at present.
- Generally, a reduction in the area of the memory cell means not only a reduction in the size of the memory cell array but also a realization of high-speed processing. In order to achieve a higher-speed operation of the SRAM than in the past, various layout proposals have been made so far.
- For example, according to the semiconductor memory device disclosed in Japanese Patent Application Laid-Open (JP-A) No. 10-178110, P-well areas and N-well area formed with inverters that constitute a memory cell are disposed so that their boundary lines are parallel with bit lines. Based on this arrangement, diffusion areas within the P-well areas and the N-well area and a cross-connected portion of two inverters are formed in simple shapes respectively having no bending. As a result, the cell area is reduced.
- FIG. 21 and FIG. 22 are layout diagrams of the semiconductor memory device disclosed in Japanese Patent Application Laid-Open (JP-A) No. 10-178110. FIG. 21 shows diffusion areas formed on the surface of a semiconductor substrate, a polycrystalline silicon film formed on the diffusion areas, and a ground including a first metal-wiring layer. FIG. 22 shows an upper ground including second and third metal-wiring layers formed on the upper layer.
- As shown in FIG. 21, in the center of the memory cell, there is disposed the N-well area in which P-channel type MOS transistors P101 and P102 are formed. On both sides of this N-well area, there are formed P-well areas in which N-channel type MOS transistors N101 and N103, and N102 and N104 are formed respectively.
- The P-channel type MOS transistors P101 and P102 and the N-channel type MOS transistors N101 and N102 are mutually connected in cross to form a CMOS inverter, that is, a flip-flop circuit. The N-channel type MOS transistors N103 and N104 correspond to an access gate (a transfer gate).
- As shown in FIG. 22, bit lines BL and /BL are separately formed as second metal-wiring layers. The bit lines BL and /BL are connected to one end of semiconductor terminals of the lower-layer access gate MOS transistors N103 and N104 respectively. A power source line Vdd is formed as a second metal-wiring layer in the center between the bit lines BL and /BL in parallel with these bit lines. The power source line Vdd is connected to one of semiconductor terminals of the lower-layer P-channel type MOS transistors P101 and P102. A word line WL is formed as a third metal-wiring layer in a direction orthogonal with the bit lines BL and /BL. The word line WL is connected to gates of the lower-layer N-channel type MOS transistor N103 and N104. Two ground lines GND are formed as third metal-wiring layers on both sides of the word line WL in parallel with this word line.
- As a result of forming the memory cell in this layout, an N-type diffusion area within the P-well area in which the MOS transistors N101 and N103 are formed and an N-type diffusion area in which the MOS transistors N102 and N104 are formed can be formed linearly in parallel with the bit lines BL and /BL. This construction can prevent a generation of an unnecessary area.
- The length of the cell in a lateral direction, that is, the length of the word line WL, is larger than the length of the cell in a longitudinal direction, that is, the length of the bit lines BL and /BL. Therefore, it becomes easy to provide a layout of a sense amplifier connected to the bit lines BL and /BL. At the same time, the number of cells to be connected to one word line can be reduced. As a result, it is possible to reduce a cell current that flows during the reading. In other words, it is possible to reduce power consumption.
- The above-described SRAM memory cell is an example of what is called one-port SRAM. In the meantime, in recent years, there has been introduced a multi-processor technique as one of means for achieving high-speed processing of computers. Based on this technique, a plurality of CPUs are required to share one memory area. In this aspect, various layouts have been proposed for a multi-port SRAM that makes it possible to have access to CPUs from two ports to the one memory cell.
- For example, according to the memory cell disclosed in Japanese Patent Application Laid-Open (JP-A) No. 07-7089, a multi-port SRAM construction is realized by disposing a second port in symmetry with a first port on the same layer and by having the two ports formed at the same time. FIG. 23 shows the layout of the memory cell disclosed in Japanese Patent Application Laid-Open (JP-A) No. 07-7089.
- As shown in FIG. 23, P-channel type MOS transistors P201 and P202 and N-channel type MOS transistors N201′, N202′, N201″ and N202″ are mutually connected in cross to form a CMOS inverter, that is, a flip-flop. N-channel type MOS transistors NA, NB, NA2 and NB2 correspond to access gates (transfer gates).
- In other words, N-channel type MOS transistors NA and NB make it possible to have an access from one gate via a word line WL1, and N-channel type MOS transistors NA2 and NB2 make it possible to have an access from the other gate via a word line WL2.
- Conventional memory cells have a disadvantage that the amount of wiring of the bit lines is large and a delay increases, as the memory cell has a larger length in the direction of the bit lines. The semiconductor memory device disclosed in Japanese Patent Application Laid-Open (JP-A) No. 10-178110 solves this problem for one-port SRAM.
- However, this semiconductor memory device does not solve the above problem for a multi-port SRAM generally having two sets of access gates and a drive-type MOS transistor. The memory cell disclosed in Japanese Patent Application Laid-Open (JP-A) No. 07-7089 shows a layout of a multi-port SRAM cell. However, this provides the layout for making it easy to add a second port without generating a large change in the layout of the one-port SRAM cell. This has not an object of reducing the multi-port SRAM cell in the direction of the bit lines.
- It is an object of the present invention to provide a semiconductor memory device having a memory cell with a short length in the direction of bit lines, in the construction of a P-well area formed with a pair of CMOS inverters and a N-well area that constitute a multi-port SRAM cell. In the semiconductor memory device of the present invention, the P-well area is divided into two P-well areas. The two P-well areas are disposed on the two sides of the N-well area. The boundaries between P and N-well areas are parallel to the bit lines, and a pair of access gates are formed in each of the two P-well areas.
- In the semiconductor memory device according to one aspect of the present invention, two P-well areas are provided on the two sides of the N-well area, three (first, third and fifth) N-channel type MOS transistors are electrically connected to the positive-phase bit line and are formed in one P-well area, and three (second, fourth and sixth) N-channel type MOS transistors are connected to the negative-phase bit line and are formed in the other P-well area. The P-well areas and the N-well area are disposed in a direction perpendicular to the positive-phase and negative-phase bit lines. Therefore, it is possible to provide a layout that requires shorter bit lines.
- Further, the first and second P-well areas are formed on both sides of the N-well area. According, it is possible to make uniform the distances of wiring connection between the N-channel type MOS transistors formed in the first and second P-well areas respectively and the P-channel type MOS transistors formed in the N-well area.
- Further, the first positive-phase bit line, first negative-phase bit line, the second positive-phase bit line, and the second negative-phase bit line extend parallel to boundary lines between the first and second P-well areas and the N-well area respectively. According, it is possible to provide a layout having each bit line formed in a shortest length by taking into consideration a reduction in the length of each word line.
- Further, the boundary lines between the first and second P-well areas and the N-well area are perpendicular to the direction in which the first and second word lines extend. Accordingly, it is possible to provide a layout having each word line formed in a shortest length by taking into consideration a reduction in the length of each bit line with priority.
- Further, the first P-channel type MOS transistor and the first, third and fourth N-channel type MOS transistors are formed so that respective gate areas are parallel with the extension direction of the first word line and are positioned on the same straight line, and the second P-channel type MOS transistor and the second, fifth and sixth N-channel type MOS transistors are formed so that respective gate areas are parallel with the extension direction of the second word line and are positioned on the same straight line. Accordingly, it is possible to form wires for connecting between the gates in a straight-line shape. Further, as the second P-channel type MOS transistor and the gate areas of the second, fifth and sixth N-channel type MOS transistors are positioned on the same straight line, it is possible to form wires for connecting between the gates in a straight-line shape.
- Further, the third and fifth N-channel type MOS transistors are formed in such a manner that respective source diffusion areas and drain diffusion areas are positioned on the same straight line, and are also disposed in parallel with the directions of the extension of the first and second positive-phase bit lines. In addition, the fourth and sixth N-channel type MOS transistors are formed in such a manner that respective source diffusion areas and drain diffusion areas are positioned on the same straight line, and are also disposed in parallel with the directions of the extension of the first and second negative-phase bit lines.
- Further, drain diffusion areas of the third and fifth N-channel type MOS transistors are formed in a common first n+ diffusion area, and drain diffusion areas of the fourth and sixth N-channel type MOS transistors are formed in a common second n+ diffusion area. Accordingly, it is possible to reduce the size of the n+ diffusion areas.
- Further, drain diffusion area of the first N-channel type MOS transistor and drain diffusion areas of the third and fifth N-channel type MOS transistors are connected to each other by an upper-layer first metal-wiring layer via contact holes, and a drain diffusion area of the second N-channel type MOS transistor and drain diffusion areas of the fourth and sixth N-channel type MOS transistors are connected to each other by an upper-layer second metal-wiring layer via contact holes. Accordingly, it is possible to form the first and second metal-wiring layers in a straight-line shape according to the positions of the drain diffusion areas.
- Further, the extension direction of the first and second metal-wiring layers is parallel with the extension direction of the first and second word lines. Accordingly, it is possible to optimize the length of the metal-wiring layers like the word lines.
- Further, extension directions of the first and second positive-phase bit line, the first and second negative-phase bit lines, the power source line and the GND line respectively are perpendicular to the first and second word lines. Accordingly, it is possible to minimize the respective length of these lines.
- Further, drain diffusion areas of the first, third and fifth N-channel type MOS transistors are formed in a common first n+ diffusion area, and drain diffusion areas of the second, fourth and sixth N-channel type MOS transistors are formed in a common second n+ diffusion area. Accordingly, it is possible to omit the metal-wiring layers between these drain diffusion areas.
- Further, the first n+ diffusion area and a drain diffusion area of the first P-channel type MOS transistor are connected to each other by an upper-layer first metal-wiring layer via contact holes, and the second n+ diffusion area and a drain diffusion area of the second P-channel type MOS transistor are connected to each other by an upper-layer second metal-wiring layer via contact holes. Accordingly, it is possible to form the metal-wiring layers in a straight-line shape according to the positions of the drain diffusion areas and the n+ diffusion areas.
- The semiconductor memory device according to another aspect of the present invention comprises a first word line, a second word line, a first positive-phase bit line, a first negative-phase bit line, and a second positive-phase bit line; a first CMOS inverter that structures a CMOS inverter by including a first N-channel type MOS transistor and a first P-channel type MOS transistor; a second CMOS inverter that structures a CMOS inverter by including a second N-channel type MOS transistor and a second P-channel type MOS transistor, and that has an input terminal of the CMOS inverter connected to an output terminal of the first CMOS inverter as a first memory node, and has an output terminal of the CMOS inverter connected to an input terminal of the first CMOS inverter as a second memory node; a third N-channel type MOS transistor that has a gate connected to the first word line, has a drain connected to the first positive-phase bit line, and has a source connected to the first memory node; a fourth N-channel type MOS transistor that has a gate connected to the first word line, has a drain connected to the first negative-phase bit line, and has a source connected to the second memory node; a fifth N-channel type MOS transistor that has a gate connected to the first memory node; and a sixth N-channel type MOS transistor that has a gate connected to the second word line, has a drain connected to the second positive-phase bit line, and has a source connected to a drain of the fifth N-channel type MOS transistor. In addition, first and second P-channel type MOS transistors are formed in an N-well area, the first and third N-channel type MOS transistors are formed in a first P-well area, and the second, fourth, fifth and sixth N-channel type MOS transistors are formed in a second P-well area.
- Further, the semiconductor memory device further comprises a third word line, a first positive-phase line, and a second negative-phase bit line; a seventh N-channel type MOS transistor that has a gate connected to the second memory node; and an eighth N-channel type MOS transistor that has a gate connected to the third word line, has a drain connected to the second negative-phase bit line, and has a source connected to a drain of the seventh N-channel type MOS transistor. The seventh and eighth N-channel type MOS transistors are formed in the first P-well area.
- Further, the second and third word lines are formed as one common word line.
- Further, the first and second P-well areas are formed at both sides of the N-well area.
- Further, the respective directions of the extensions of the first positive-phase bit line, the first negative-phase bit line, and the second positive-phase bit line are parallel with a boundary line between the first and second P-well areas and the N-well area.
- Further, a boundary line between the first and second P-well areas and the N-well area is orthogonal with directions of respective extensions of the first and second word lines.
- Further, the first P-channel type MOS transistor, and the first, fourth and sixth N-channel type MOS transistors are formed such that their respective gate areas are positioned on the same straight line, and are also disposed in parallel with the direction of the extension of the first word line. Further, the second P-channel type MOS transistor, and the second, third and fifth N-channel type MOS transistors are formed such that their respective gate areas are positioned on the same straight line, and are also disposed in parallel with the direction of the extension of the second word line.
- Further, the first and third N-channel type MOS transistors are formed such that a drain diffusion area of the first N-channel type MOS transistor and a source diffusion area of the third N-channel type MOS transistor are positioned on the same straight line, and also disposed in parallel with the direction of the extension of the first positive-phase bit line. Further, the second and fourth N-channel type MOS transistors are formed such that a drain diffusion area of the second N-channel type MOS transistor and a source diffusion area of the fourth N-channel type MOS transistor are positioned on the same straight line, and also disposed in parallel with the direction of the extension of the first negative-phase bit line. Further, the fifth and sixth N-channel type MOS transistors are formed such that a drain diffusion area of the fifth N-channel type MOS transistor and a source diffusion area of the sixth N-channel type MOS transistor are positioned on the same straight line, and also disposed in parallel with the direction of the extension of the second positive-phase bit line.
- Further, a drain diffusion area of the first N-channel type MOS transistor and a source diffusion area of the third N-channel type MOS transistor are formed in a common first n+ diffusion area. Further, a drain diffusion area of the second N-channel type MOS transistor and a source diffusion area of the fourth N-channel type MOS transistor are formed in a common second n+ diffusion area. Further, a drain diffusion area of the fifth N-channel type MOS transistor and a source diffusion area of the sixth N-channel type MOS transistor are formed in a common third n+ diffusion area.
- Further, the second P-channel type MOS transistor, and the second and fifth N-channel type MOS transistors have their respective gate areas connected by a straight line-shaped common polysilicon wiring.
- Further, the directions of the extensions of the first and second positive-phase bit lines, the first negative-phase bit line, a power source line, and a GND line respectively are perpendicular to the first and second word lines.
- Further, the first P-channel type MOS transistor, and the first, fourth, sixth and seventh N-channel type MOS transistors are formed such that their respective gate areas are in parallel with the direction of the extension of the first word line, and are also positioned on the same straight line. Further, the second P-channel type MOS transistor, and the second, third, fifth and eighth N-channel type MOS transistors are formed such that their respective gate areas are in parallel with the direction of the extension of the second word line, and are also positioned on the same straight line.
- Further, the first and third N-channel type MOS transistors are formed such that a drain diffusion area of the first N-channel type MOS transistor and a source diffusion area of the third N-channel type MOS transistor are in parallel with the direction of the extension of the first positive-phase bit line, and are also positioned on the same straight line. Further, the second and fourth N-channel type MOS transistors are formed such that a drain diffusion area of the second N-channel type MOS transistor and a source diffusion area of the fourth N-channel type MOS transistor are in parallel with the direction of the extension of the first negative-phase bit line, and are also positioned on the same straight line. Further, the fifth and sixth N-channel type MOS transistors are formed such that a drain diffusion area of the fifth N-channel type MOS transistor and a source diffusion area of the sixth N-channel type MOS transistor are in parallel with the direction of the extension of the second positive-phase bit line, and are also positioned on the same straight line. Further, the seventh and eighth N-channel type MOS transistors are formed such that a drain diffusion area of the seventh N-channel type MOS transistor and a source diffusion area of the eighth N-channel type MOS transistor are in parallel with the direction of the extension of the second negative-phase bit line, and are also positioned on the same straight line.
- Further, a drain diffusion area of the first N-channel type MOS transistor and a source diffusion area of the third N-channel type MOS transistor are formed in a common first n+ diffusion area. Further, a drain diffusion area of the second N-channel type MOS transistor and a source diffusion area of the fourth N-channel type MOS transistor are formed in a common second n+ diffusion area. Further, a drain diffusion area of the fifth N-channel type MOS transistor and a source diffusion area of the sixth N-channel type MOS transistor are formed in a common third n+ diffusion area. Further, a drain diffusion area of the seventh N-channel type MOS transistor and a source diffusion area of the eighth N-channel type MOS transistor are formed in a common fourth n+ diffusion area.
- Further, the second P-channel type MOS transistor, and the second and fifth N-channel type MOS transistors have their respective gate areas connected by a straight line-shaped common first polysilicon wiring. Further, the first P-channel type MOS transistor, and the first and seventh N-channel type MOS transistors have their respective gate areas connected by a straight line-shaped common second polysilicon wiring.
- Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.
- FIG. 1 is a diagram showing an equivalent circuit of a semiconductor memory device according to a first embodiment of the present invention.
- FIG. 2 is a diagram showing an example of the layout of a memory cell of the semiconductor memory device according to the first embodiment.
- FIG. 3 is a diagram showing an another example of the layout of the memory cell of the semiconductor memory device according to the first embodiment.
- FIG. 4 is a diagram showing still another example of the layout of the memory cell of the semiconductor memory device according to the first embodiment.
- FIG. 5 is a diagram showing still another example of the layout of the memory cell of the semiconductor memory device according to the first embodiment.
- FIG. 6 is an explanation of various symbols like a contact hole, a via hole, etc.
- FIG. 7 is a diagram showing an example of the layout of a memory cell of a semiconductor memory device according to a second embodiment of the invention.
- FIG. 8 is a diagram showing an equivalent circuit of a semiconductor memory device according to a third embodiment of the present invention.
- FIG. 9 is a diagram showing an example of the layout of a memory cell of the semiconductor memory device according to the third embodiment.
- FIG. 10 is a diagram showing another example of the layout of the memory cell of the semiconductor memory device according to the third embodiment.
- FIG. 11 is a diagram showing still another example of the layout of the memory cell of the semiconductor memory device according to the third embodiment.
- FIG. 12 is a diagram showing still another example of the layout of the memory cell of the semiconductor memory device according to the third embodiment.
- FIG. 13 is a diagram showing an equivalent circuit of a semiconductor memory device according to a fourth embodiment of the present invention.
- FIG. 14 is a diagram showing an example of the layout of the memory cell of the semiconductor memory device according to the fourth embodiment.
- FIG. 15 is a diagram showing another example of the layout of the memory cell of the semiconductor memory device according to the fourth embodiment.
- FIG. 16 is a diagram showing still another example of the layout of the memory cell of the semiconductor memory device according to the fourth embodiment.
- FIG. 17 is a diagram showing still another example of the layout of the memory cell of the semiconductor memory device according to the fourth embodiment.
- FIG. 18 is a diagram showing an equivalent circuit of a semiconductor memory device according to a fifth embodiment of the present invention.
- FIG. 19 is a diagram showing an example of the layout of the memory cell of the semiconductor memory device according to the fifth embodiment.
- FIG. 20 is a diagram showing another example of the layout of the memory cell of the semiconductor memory device according to the fifth embodiment.
- FIG. 21 is a layout diagram showing a diffusion area formed on the surface of a semiconductor substrate, a polycrystalline silicon film formed on the diffusion areas, and a ground including a first metal-wiring layer, according to a conventional semiconductor memory device.
- FIG. 22 is a layout diagram showing an upper ground including second and third metal-wiring layers formed on the upper layer, according to the conventional semiconductor memory device.
- FIG. 23 is a layout diagram showing a conventional memory cell.
- Preferred embodiments of the present invention will be explained below with reference to the accompanying drawings. The following embodiments will not limit the present invention.
- A semiconductor memory device of a first embodiment will be explained here. FIG. 1 shows an equivalent circuit of the semiconductor memory device of the first embodiment. A P-channel type MOS transistor P1 and an N-channel type MOS transistor N1 (N1′) constitute a first CMOS inverter. A P-channel type MOS transistor P2 and an N-channel type MOS transistor N2 (N2′) constitute a second CMOS inverter. Inputs and outputs of these CMOS inverters are connected in cross.
- In other words, these MOS transistors P1, P2, N1, N1′, N2 and N2′ constitute a flip-flop circuit. In FIG. 1, it is possible to carry out a writing and a reading in a logic state in a memory node MA which is an output point of the first CMOS inverter and input point of the second CMOS inverter, and in a memory node MB which is an output point of the second CMOS inverter and input point of the first CMOS inverter.
- N-channel type MOS transistors M3, N4, N5 and N6 function as access gates respectively. The gate of the N-channel type MOS transistor N3 is connected to a first word line WL0, the source is connected to the memory node MA, and the drain is connected to a first positive-phase bit line B100. The gate of the N-channel type MOS transistor N5 is connected to a second word line WL1, the source is connected to the memory node MA, and the drain is connected to a second positive-phase bit line BL10.
- The gate of the N-channel type MOS transistor N4 is connected to a first word line WL0, the source is connected to the memory node MB, and the drain is connected to a first negative-phase bit line BL01. The gate of the N-channel type MOS transistor N6 is connected to the second word line WL1, the source is connected to the memory node MB, and the drain is connected to a second negative-phase bit line BL11.
- In other words, it is possible to read a memory value of a first port by selecting the first word line WL0, the first positive-phase bit line BL00 and the first negative-phase bit line BL01. It is possible to read a memory value of a second port by selecting the second word line WL1, the second positive-phase bit line BL10 and the second negative-phase bit line BL11.
- The equivalent circuit itself shown in FIG. 1 is not different from the circuit of the conventional two-port SPAM cell. However, in the semiconductor memory device of the first embodiment, there is a characteristic in the construction of the memory cell. FIG. 2 to FIG. 5 are layout diagrams of the memory cell of the semiconductor memory device of the first embodiment. FIG. 6 explains various symbols like a contact hole, a via hole, etc. shown in FIG. 2 to FIG. 5. FIG. 2 shows layers including well areas formed on a semiconductor substrate, diffusion areas formed in the well areas, and a polysilicon wiring layer formed on the upper surface.
- In the memory cell of the semiconductor memory device of the first embodiment, there are formed a first P-well area PW1, an N-well area NW, and a second P-well area PW2 in this sequence in a plain direction on the semiconductor substrate, as shown in FIG. 2. In other words, the two P-well areas PW1 and PW2 are disposed separately on the two sides of the N-well area NW.
- Particularly, these well areas are formed so that a boundary line between the first P-well area PW1 and the N-well area NW (hereinafter to be referred to as a first well boundary line) and a boundary line between the second P-well area PW2 and the N-well area NW (hereinafter to be referred to as a second well boundary line) are parallel with each other. Although not shown in FIG. 2, there exist a separation area between the N-well area NW and the first P-well area PW1 and between the N-well area NW and the second P-well area PW2 respectively.
- The N-channel type MOS transistors N1, N1′, N3 and N5 shown in FIG. 1 are formed in the first P-well area PW1. The P-channel type MOS transistors P1 and P2 shown in FIG. 1 are formed in the N-well area NW. Further, the N-channel type MOS transistors N2, N2′, N4 and N6 shown in FIG. 1 are formed in the second P-well area PW2.
- The construction of each layer shown in FIG. 2 to FIG. 5 will be explained in sequence. First, in the layers shown in FIG. 2, two polysilicon wiring layers PL21 and PL22 are disposed in the first P-well area PW1 extending in a direction perpendicular to the first well boundary line. Similarly, two polysilicon wiring layers PL31 and PL32 are disposed in the second P-well area PW2 extending in a direction perpendicular to the second well boundary line.
- A piece type polysilicon wiring layer PL11 is formed in the area from the N-well area NW to the first P-well area PW1 in a direction perpendicular to the first well boundary line so that the piece end is positioned in the first P-well area PW1. As shown in FIG. 2, the piece end has a shape that two parallel axes (a main axis and a return axis) that constitute the piece end of the polysilicon wiring layer PL11 coincide with axes of the two polysilicon wiring layers PL21 and PL22 respectively. Further, the main axis of the polysilicon wiring layer PL11 coincides with the polysilicon wiring layer PL21. On the other hand, the other end of the polysilicon wiring layer PL11 is positioned on the second well boundary line.
- Similarly, a piece type polysilicon wiring layer PL12 is formed in the area from the N-well area NW to the second P-well area PW2 in a direction perpendicular to the second well boundary line so that the piece end is positioned in the second P-well area PW2. As shown in FIG. 2, the piece end has a shape that two parallel axes that constitute the piece end of the polysilicon wiring layer PL12 coincide with axes of the two polysilicon wiring layers PL31 and PL32 respectively. Further, the main axis of the polysilicon wiring layer PL12 coincides with the polysilicon wiring layer PL31. On the other hand, the other end of the polysilicon wiring layer PL12 is positioned on the first well boundary line.
- n+ diffusion areas FL21 and FL22 are formed in the first P-well area PW1 by injecting an N-type impurity at positions sandwiching the polysilicon wiring layer PL21. Thus, there is formed an N-channel type MOS transistor N3 that uses the polysilicon wiring layer PL21 as a gate electrode. Further, n+ diffusion areas FL22 and FL23 are formed at positions sandwiching the polysilicon wiring layer PL22. Thus, there is formed an N-channel type MOS transistor N5 that uses the polysilicon wiring layer PL22 as a gate electrode.
- Particularly, as the polysilicon wiring layers PL21 and PL22 are disposed in parallel in the N-channel type MOS transistors N3 and N5 respectively, it is possible to dispose the n+ diffusion areas FL21 to FL23 in a direction parallel with the first well boundary line and also in a straight line. With this arrangement, the N-channel type MOS transistors N3 and N5 can share the n+ diffusion area FL22. The sharing of this n+ diffusion area FL22 makes it possible to connect the sources of the N-channel type MOS transistors N3 and N5 together, and also contributes to reduce the area occupied by the N-channel type MOS transistors N3 and N5, according to the equivalent circuit shown in FIG. 1.
- Further, n+ diffusion areas FL24 and FL25 are formed in the first P-well area PW1 by injecting an N-type impurity at positions sandwiching the main axis of the piece end of the polysilicon wiring layer PL11. Thus, there is formed an N-channel type MOS transistor N1 that uses the main axis of the polysilicon wiring layer PL11 as a gate electrode. Further, n+ diffusion areas FL25 and FL26 are formed at positions sandwiching the return axis of the piece end of the polysilicon wiring layer PL11. Thus, there is formed an N-channel type MOS transistor N1′ that uses the return axis of the polysilicon wiring layer PL11 as a gate electrode. In other words, the piece end of the polysilicon wiring layer PL11 makes it possible to connect the gates of the N-channel type MOS transistors N1 and N1′ together, according to the equivalent circuit shown in FIG. 1.
- Similarly, like the N-channel type MOS transistors N3 and N5, the main axis and the return axis of the polysilicon wiring layer PL11 are disposed in parallel in the N-channel type MOS transistors N1 and N1′ respectively. Therefore, it is possible to dispose the n+ diffusion areas FL24 to FL26 in a direction parallel with the first well boundary line and also in a straight line. With this arrangement, the N-channel type MOS transistors N1 and N1′ can share the n+ diffusion area FL25. The sharing of this n+ diffusion area FL25 makes it possible to connect the drains of the N-channel type MOS transistors N1 and N1′ together, and also contributes to reduce the area occupied by the N-channel type MOS transistors N1 and N1′, according to the equivalent circuit shown in FIG. 1.
- Further, as shown in FIG. 2, the main axes of the polysilicon wiring layer PL21 and the polysilicon wiring layer PL11 are positioned on the same straight line, and the return axes of the polysilicon wiring layer PL22 and the polysilicon wiring layer PL11 are also positioned on the same straight line. Therefore, it is possible to reduce the disposition distance between the N-channel type MOS transistors N1 and N1′ and between the N-channel type MOS transistors N3 and MS respectively. As a result, it is possible to achieve a reduction in the area occupied by these four N-channel type MOS transistors in the first P-well area PW1.
- n+ diffusion areas FL31 and FL32 are similarly formed in the second P-well area PW2 by injecting an N-type impurity at positions sandwiching the polysilicon wiring layer PL31. Thus, there is formed an N-channel type MOS transistor N6 that uses the polysilicon wiring layer PL21 as a gate electrode. Further, n+ diffusion areas FL32 and FL33 are formed at positions sandwiching the polysilicon wiring layer PL32. Thus, there is formed an N-channel type MOS transistor N4 that uses the polysilicon wiring layer PL32 as a gate electrode.
- As the polysilicon wiring layers PL31 and PL32 are also disposed in parallel in the N-channel type MOS transistors N4 and N6 respectively, it is possible to dispose the n+ diffusion areas FL31 to FL33 in a direction parallel with the second well boundary line and also in a straight line. With this arrangement, the N-channel type MOS transistors N4 and N6 can share the n+ diffusion area FL32. The sharing of this n+ diffusion area FL32 makes it possible to connect the sources of the N-channel type MOS transistors N4 and N6 together, and also contributes to reduce the area occupied by the N-channel type MOS transistors N4 and N6, according to the equivalent circuit shown in FIG. 1.
- n+ diffusion areas FL34 and FL35 are formed in the second P-well area PW2 by injecting an N-type impurity at positions sandwiching the main axis of the piece end of the polysilicon wiring layer PL12. Thus, there is formed an N-channel type MOS transistor N2 that uses the main axis of the polysilicon wiring layer PL12 as a gate electrode. Further, n+ diffusion areas FL35 and FL36 are formed at positions sandwiching the return axis of the piece end of the polysilicon wiring layer PL12. Thus, there is formed an N-channel type MOS transistor N2′ that uses the return axis of the polysilicon wiring layer PL12 as a gate electrode. In other words, the piece end of the polysilicon wiring layer PL12 makes it possible to connect the gates of the N-channel type MOS transistors N2 and N2′ together, according to the equivalent circuit shown in FIG. 1.
- Similarly, like the N-channel type MOS transistors N4 and N6, the main axis and the return axis of the polysilicon wiring layer PL12 are disposed in parallel in the N-channel type MOS transistors N2 and N2′ respectively. Therefore, it is possible to dispose the n+ diffusion areas FL34 to FL36 in a direction parallel with the second well boundary line and also in a straight line. With this arrangement, the N-channel type MOS transistors N2 and N2′ can share the n+ diffusion area FL35. The sharing of this n+ diffusion area FL35 makes it possible to connect the drains of the N-channel type MOS transistors N2 and N2′ together, and also contributes to reduce the area occupied by the N-channel type MOS transistors N2 and N2′, according to the equivalent circuit shown in FIG. 1.
- Further, as shown in FIG. 2, the main axes of the polysilicon wiring layer PL31 and the polysilicon wiring layer PL12 are positioned on the same straight line, and the return axes of the polysilicon wiring layer PL32 and the polysilicon wiring layer PL12 are also positioned on the same straight line. Therefore, it is possible to reduce the disposition distance between the N-channel type MOS transistors N2 and N2′ and between the N-channel type MOS transistors N4 and N6 respectively. As a result, it is possible to achieve a reduction in the area occupied by these four N-channel type MOS transistors in the second P-well area PW2.
- p+ diffusion areas FL11 and FL12 are formed in the N-well area NW by injecting a P-type impurity at positions sandwiching the main axis of the polysilicon wiring layer PL11. Thus, there is formed a P-channel type MOS transistor P1 that uses the polysilicon wiring layer PL11 as a gate electrode. Further, p+ diffusion areas FL13 and FL14 are formed at positions sandwiching the main axis of the polysilicon wiring layer PL12. Thus, there is formed a P-channel type MOS transistor P2 that uses the polysilicon wiring layer PL12 as a gate electrode.
- Positions of the P-channel type MOS transistors P1 and P2 are determined based on the positions of the polysilicon wiring layers PL11 and PL12. Distance between the polysilicon wiring layers PL11 and PL12 can be reduced to about the size of the p+ diffusion area FL12 or the FL13 (minimum pitch of the transistor) as shown in FIG. 2. Particularly, when the sizes of the p+ diffusion areas FL12 and FL13 are set approximately equal to the sizes of the n+ diffusion areas FL22 and FL25 in the first P-well area PW1 and the n+ diffusion areas FL32 and FL35 in the second P-well area PW2, it is possible to minimize the total area required for the layout of the memory cell.
- The above arrangement also means that it is possible to dispose the main axes of the polysilicon wiring layers PL21 and PL11, the return axis of the PL12 and the PL32 on the same straight line, and it is also possible to dispose the main axes of the polysilicon wiring layers PL22 and PL12, the return axis of the PL11 and the PL31 on the same straight line.
- In order to have an electrical connection with the upper layer, there is one contact hole provided on each of the polysilicon wiring layers PL11, PL12, PL21, PL22, PL31 and PL32, the p+ diffusion areas FL11 to FL14, and the n+ diffusion areas FL21 to FL26 and FL31 to FL36 as shown in FIG. 2.
- Next, layers positioned above the layers shown in FIG. 2 will be explained. FIG. 3 shows layers including first metal-wiring layers formed on the layers shown in FIG. 2. As one of layers shown in FIG. 3, there is formed a first metal-wiring layer AL11 for electrically connecting the lower-layer items of the n+ diffusion areas FL22 and FL25, the p+ diffusion area FL12, and the polysilicon wiring layer PL12. This first metal-wiring layer AL11 makes it possible to connect the sources of the N-channel type MOS transistors N3 and N5, the drains of the N-channel type MOS transistors N1 and N1′, the output terminal of the first CMOS inverter, and the input terminal of the second CMOS inverter, according to the equivalent circuit shown in FIG. 1.
- Further, there is formed a first metal-wiring layer AL12 for electrically connecting between the lower-layer items of the n+ diffusion areas FL32 and FL35, the p+ diffusion area FL13, and the polysilicon wiring layer PL11. This first metal-wiring layer AL12 makes it possible to connect between the sources of the N-channel type MOS transistors N4 and N6, the drains of the N-channel type MOS transistors N2 and N2′, the output terminal of the second CMOS inverter, and the input terminal of the first CMOS inverter, according to the equivalent circuit shown in FIG. 1.
- Particularly, in the first metal-wiring layer AL11, the contact points of the n+ diffusion areas FL32 and FL35 and the p+ diffusion area FL13 are disposed on the same straight line as described above. Therefore, it is possible to form a wire for connecting between these three points in a straight-line shape. The above similarly applies to the first metal-wiring layer AL12.
- Further, as layers shown in FIG. 3, there are formed a first metal-wiring layer AL15 for moving the connection point of the lower-layer p+ diffusion area FL11, and a first metal-wiring layer AL16 for moving the connection point of the lower-layer p+ diffusion area FL14. There are also formed a first metal-wiring layer AL17 for moving the connection point of the lower-layer n+ diffusion area FL23, and a first metal-wiring layer AL18 for moving the connection point of the lower-layer n+ diffusion area FL33.
- Next, layers positioned above the layers shown in FIG. 3 will be explained. FIG. 4 shows layers including second metal-wiring layers formed on the layers shown in FIG. 3. As one of layers shown in FIG. 4, there is formed a second metal-wiring layer AL21 for applying a power source potential VDD to the p+ diffusion area FL11 via the first metal-wiring layer AL15 shown in FIG. 3 and for applying a power source potential VDD to the p+ diffusion area FL14 via the first metal-wiring layer AL16. In other words, the second metal-wiring layer AL21 functions as a power source potential VDD line, and achieves a connection between the source of the P-channel type MOS transistor P1 and the power source and a connection between the source of the P-channel type MOS transistor P2 and the power source, in the equivalent circuit shown in FIG. 1.
- Further, there are formed second metal-wiring layers AL22 and AL23 for applying a ground potential GND to the p+ diffusion areas FL24 and FL26 and to the p+ diffusion areas FL34 and FL36 respectively via contact holes and first via holes shown in FIG. 3. In other words, the second metal-wiring layers AL22 and AL23 function as a ground potential GND line respectively, and achieve a grounding of each source of the N-channel type MOS transistors N1, N1′, N2 and N2′ respectively, in the equivalent circuit shown in FIG. 1.
- Particularly, as shown in FIG. 2, the n+ diffusion areas FL24 and FL26 are disposed on a straight line parallel with the first well boundary line. Therefore, the contact holes on the n+ diffusion areas may be formed at positions where a straight line connecting between the contact holes is parallel with the first well boundary line. In other words, it is possible to form the second metal-wiring layer AL22 shown in FIG. 4 in a straight-line shape parallel with the first well boundary line. This similarly applies to the second metal-wiring layer AL23.
- Further, as layers shown in FIG. 4, there are formed a second metal-wiring layer AL24 that is connected with the lower-layer p+ diffusion area FL21 and functions as a first positive-phase bit line BL00, a second metal-wiring layer AL25 that is connected with the lower-layer p+ diffusion area FL26 and functions as a second positive-phase bit line BL10, a second metal-wiring layer AL26 that is connected with the lower-layer p+ diffusion area FL36 and functions as a first negative-phase bit line BL01, and a second metal-wiring layer AL27 that is connected with the lower-layer p+ diffusion area FL31 and functions as a second negative-phase bit line BL11, via the contact holes and the first via holes shown in FIG. 3 respectively.
- In other words, these second metal-wiring layers AL24 to AL27 achieve a connection between the other semiconductor end (drain) of the N-channel type MOS transistor N3 and the first positive-phase bit line BL00, a connection between the other semiconductor end (drain) of the N-channel type MOS transistor N5 and the second positive-phase bit line BL10, a connection between the other semiconductor end (drain) of the N-channel type MOS transistor N4 and the first negative-phase bit line BL01, and a connection between the other semiconductor end (drain) of the N-channel type MOS transistor N6 and the second negative-phase bit line BL11, respectively, in the equivalent circuit shown in FIG. 1.
- Particularly, it is possible to form the second metal-wiring layers AL24 to AL27 in a straight-line shape respectively extending in a direction parallel with the first well boundary line. This means that it is possible to further reduce the length of each of the first positive-phase bit line BL00, the second positive-phase bit line BL10, the first negative-phase bit line BL01 and the second negative-phase bit line BL11, within one memory cell.
- Next, layers positioned above the layers shown in FIG.4 will be explained. FIG. 5 shows layers including third metal-wiring layers formed on the layers shown in FIG. 4. As one of layers shown in FIG. 5, there is formed a third metal-wiring layer AL31 for electrically connecting the polysilicon wiring layers PL21 and PL32 via the first via hole and a second via hole and for functioning as a first word line WL0. In other words, the third metal-wiring layer AL31 achieves a connection between the gates of the N-channel type MOS transistors N3 and N4 and the first word line WL0, in the equivalent circuit shown in FIG. 1.
- Further, there is formed a third metal-wiring layer AL32 for electrically connecting the polysilicon wiring layers PL22 and PL31 via the first via hole and the second via hole and for functioning as a second word line WL1. In other words, the third metal-wiring layer AL32 achieves a connection between the gates of the N-channel type MOS transistors N5 and N6 and the second word line WL1, in the equivalent circuit shown in FIG. 1.
- Particularly, as shown in FIG. 2, the polysilicon wiring layers PL21 and PL32 are disposed on the same straight line extending in a direction perpendicular to the first well boundary line. Therefore, it is possible to form the contact holes on the polysilicon wiring layers at positions where a straight line connecting between these contact holes is perpendicular to the first well boundary line. In other words, the third metal-wiring layer AL31 shown in FIG. 5 can be formed in a straight-line shape extending in a direction perpendicular to the first well boundary line. This similarly applies to the third metal-wiring layer AL32. This means that it is possible to further reduce the length of each of the first word line WLQ and the second word line WL1 within one memory cell.
- As explained above, according to the semiconductor memory device of the first embodiment, the N-channel type MOS transistors N3 and N5 (or N4 and N6) functioning as access gates share the common n+ diffusion area FL22 (or FL32) at a connection point between these semiconductors. Similarly, the n+ diffusion areas FL21 to FL23 (or FL31 to FL33) that become the respective semiconductor terminals are formed on the same straight line parallel with the first well boundary line. Therefore, it is possible to reduce the area occupied by the N-channel type MOS transistors N3 and N5 (or N4 and N6). This makes it possible to increase the integration degree of the memory cell array.
- Further, the second metal-wiring layers AL24 to AL27 that function as the first positive-phase bit line BL00, the second positive-phase bit line BL10, the first negative-phase bit line BL01 and the second negative-phase bit line BL11 in this order respectively are formed in parallel with the boundary lines between the first P-well area PW1, the second P-well area PW2 and the N-well area NW respectively. Therefore, each bit line length can be reduced. As a result, it is possible to reduce the amount of wiring of the bit lines, which makes it possible to achieve a high-speed accessing.
- Further, the third metal-wiring layers AL31 and AL32 that function as the first word line WL0 and the second word line WL1 respectively are formed so that these layers are orthogonal with the boundary lines between the first P-well area PW1 and the second P-well area PW2 and the N-well area NW respectively. Therefore, each word line length can be reduced. As a result, it is possible to reduce the amount of wiring of the word lines, which makes it possible to achieve a high-speed accessing.
- Further, as the N-channel type MOS transistors N1 and N2 (or N1′ and N2′) are provided in the two different P-well areas, it is possible to take a large width for each transistor. As a result, extraction of bit lines becomes faster, which makes it possible to achieve an access at a higher speed.
- Further, as the N-channel type MOS transistors N1 and N1′ (or N2 and N2′) that function as driver transistors are formed in parallel, it is possible to take a large width W for each transistor. As a result, extraction of bit lines becomes faster, which makes it possible to achieve a reading access at a higher speed.
- Further, based on the above-described division (providing indifferent areas) of the N-channel type MOS transistors, it is possible to take a large transistor ratio for the N-channel type MOS transistors N3 and N5 that function as access gates and for the N-channel type MOS transistors N1 and N1′ that function as driver transistors respectively. Therefore, it is possible to improve the stability of the cell. This similarly applies to the N-channel type MOS transistors N4 and N6 and the N-channel type MOS transistors N2 and N2′ respectively.
- Further, as the drain areas for forming the memory nodes MA and MB are made in a common n+ diffusion area, it is possible to reduce the size of these areas. As a result, a parasitic capacitance can be reduced, which makes it possible to achieve a writing access at a higher speed.
- Further, the drain areas for forming the memory nodes MA and MB are made in a common n+ diffusion area. Therefore, it is possible to reduce the size of these areas. As a result, a parasitic capacitance can be reduced, which makes it possible to achieve a writing access at a higher speed.
- A semiconductor memory device of a second embodiment will be explained here. FIG. 7 is a layout diagram showing a memory cell of the semiconductor memory device of the second embodiment. FIG. 7 equivalent to FIG. 2.
- The semiconductor memory device of the second embodiment is characterized by the following. Drain diffusion areas of N-channel type MOS transistors N3 and N5 and drain diffusion areas of N-channel type MOS transistors N1 and N1′ are formed in a P-well area PW1 by a common n+ diffusion area FL41. Further, drain diffusion areas of N-channel type MOS transistors N4 and N6 and drain diffusion areas of N-channel type MOS transistors N2 and N2′ are formed in a P-well area PW2 by a common n+ diffusion area FL 42.
- Further, along with the above arrangement, polysilicon wiring layers PL51 and PL52 are formed in place of the polysilicon wiring layers PL11 and PL12 shown in FIG. 2. The layouts of other upper-layer metal-wiring layers are similar to those shown in FIG. 3 to FIG. 5, and therefore, their explanation will be omitted.
- As explained above, according to the semiconductor memory device of the second embodiment, it is possible to obtain all the effects of the first embodiment, based on the sharing of the n+ diffusion areas as explained above.
- It should be noted that the N-channel type MOS transistors N1′ and N2′ can be omitted from both the first and second embodiments.
- Next, a semiconductor memory device of a third embodiment will be explained. The third embodiment is for explaining a layout structure of other equivalent circuit that structures a two-port SRAM cell. FIG. 8 shows an equivalent circuit of the semiconductor memory device of the third embodiment. As shown in FIG. 8, a P-channel type MOS transistor P1 and an N-channel type MOS transistor N1 constitute a first CMOS inverter. A P-channel type MOS transistor P2 and an N-channel type MOS transistor N2 constitute a second CMOS inverter. Input/output terminals of these CMOS inverters are connected in cross.
- In other words, these MOS transistors P1, P2, N1, and N2 constitute a flip-flop circuit. In FIG. 8, it is possible to carry out a writing and a reading in a logic state in a memory node MA which is an output point of the first CMOS inverter and input point of the second CMOS inverter, and in a memory node MB which is an output point of the second CMOS inverter and input point of the first CMOS inverter.
- N-channel type MOS transistors N3 and N4 function as access gates respectively. The gate of the N-channel type MOS transistor N3 is connected to a first word line WWL, the source is connected to the memory node MA, and the drain is connected to a first positive-phase bit line WBL1. The gate of the N-channel type MOS transistor N4 is connected to the first word line WWL, the source is connected to the memory node MA, and the gate is connected to a negative-phase bit line WBL2.
- The gate of the N-channel type MOS transistor N8 is connected to the memory node MA, and the source of the N-channel type MOS transistor N8 is grounded. Further, the drain of the N-channel type MOS transistor N8 is connected to the source of an N-channel type MOS transistor N9. The gate of the N-channel type MOS transistor N9 is connected to the second word line RWL, and the drain is connected to a second positive-phase bit line RBL.
- In other words, it is possible to read and write a memory value of a first port by selecting the word line WWL, the first positive-phase bit line WBL1 and the negative-phase bit line WBL2. It is possible to read a memory value of a second port by selecting the second word line RWL and the second positive-phase bit line RBL. Particularly, the read operation based on this second port has a characteristic in that this operation can be carried out completely independent of the first port, without destroying the data of the memory nodes MA and MB of the memory cell.
- The equivalent circuit itself shown in FIG. 8 has a known structure as the conventional two-port SRAM cell. However, in the semiconductor memory device of the third embodiment, there is a characteristic in the construction of the memory cell. FIG. 9 to FIG. 12 are layout diagrams of the memory cell of the semiconductor memory device of the third embodiment. FIG. 6 explains various symbols like a contact hole, a via hole, etc. shown in FIG. 9 to FIG. 12.
- FIG. 9 shows layers including well areas formed on a semiconductor substrate, diffusion areas formed in the well areas, and a polysilicon wiring layer formed on the upper surface.
- In the memory cell of the semiconductor memory device of the third embodiment, there are formed a first P-well area PW1 and a second P-well area PW2 by sandwiching the N-well area NW in a plain direction on the semiconductor substrate, as shown in FIG. 9, in a similar manner to that of the first embodiment. Further, these well areas are formed so that the first well boundary line and the second well boundary line are parallel with each other. Although not shown in FIG. 9, there exist a separation area between the N-well area NW and the first P-well area PW1 and between the N-well area NW and the second P-well area PW2 respectively.
- In FIG. 9, the N-channel type MOS transistors N1 and N3 shown in FIG. 8 are formed in the first P-well area PW1. The P-channel type MOS transistors P1 and P2 shown in FIG. 8 are formed in the N-well area NW. Further, the N-channel type MOS transistors N2, N4, N8 and N9 shown in FIG. 8 are formed in the second P-well area PW2.
- The construction of each layer shown in FIG. 9 to FIG. 12 will be explained in sequence. First, in the layers shown in FIG. 9, a polysilicon wiring layer PL21 is formed in the first P-well area PW1, extending in a direction perpendicular to the first well boundary line.
- Further, a polysilicon wiring layer PL11 is disposed in the area from the first P-well area PW1 to the N-well area NW, extending in a straight line in a direction perpendicular to the first well boundary line. One end of the polysilicon wiring layer PL11 is positioned on the second well boundary line as shown in FIG. 9.
- There are formed n+ diffusion areas FL22 and FL23 in the first P-well area PW1 by injecting an N-type impurity at positions sandwiching the polysilicon wiring layer PL21. Thus, there is formed an N-channel type MOS transistor N3 that uses the polysilicon wiring layer PL21 as a gate electrode. Further, n+ diffusion areas FL21 and FL22 are formed at positions sandwiching the polysilicon wiring layer PL11. Thus, there is formed an N-channel type MOS transistor N1 that uses the polysilicon wiring layer PL11 as a gate electrode.
- Particularly, as the polysilicon wiring layers PL11 and PL21 are disposed in parallel in the N-channel type MOS transistors N1 and N3 respectively, it is possible to dispose the n+ diffusion areas FL21 to FL23 in a direction parallel with the first well boundary line and also in a straight line. With this arrangement, the N-channel type MOS transistors N1 and N3 can share the n+ diffusion area FL22. The sharing of this n+ diffusion area FL22 makes it possible to connect the drain of the N-channel type MOS transistors N1 and the source of the N-channel type MOS transistors N3 together, and also contributes to reduce the area occupied by the N-channel type MOS transistors N1 and N3, according to the equivalent circuit shown in FIG. 8.
- In the mean time, two polysilicon wiring layers PL31 and PL33 are disposed in the second P-well area PW2, extending in a direction perpendicular to the second well boundary line. Further, a polysilicon wiring layer PL12 is formed in the area from the second P-well area PW2 to the N-well area NW, extending in a direction perpendicular to the second well boundary line. One end of the polysilicon wiring layer PL12 is positioned on the first well boundary line as shown in FIG. 9.
- There are formed n+ diffusion areas FL36 and FL35 by injecting an N-type impurity at positions sandwiching the polysilicon wiring layer PL33. Thus, there is formed an N-channel type MOS transistor N4 that uses the polysilicon wiring layer PL33 as a gate electrode. Further, n+ diffusion areas FL34 and FL35 are formed at positions sandwiching the polysilicon wiring layer PL12. Thus, there is formed an N-channel type MOS transistor N2 that uses the polysilicon wiring layer PL12 as a gate electrode.
- As the polysilicon wiring layers PL33 and PL12 are disposed in parallel in the N-channel type MOS transistors N2 and N4 respectively, it is possible to dispose the n+ diffusion areas FL34 to FL36 in a direction parallel with the second well boundary line and also in a straight line. With this arrangement, the N-channel type MOS transistors N2 and N4 can share the n+ diffusion area FL35. The sharing of this n+ diffusion area FL35 makes it possible to connect the drain of the N-channel type MOS transistors N2 and the source of the N-channel type MOS transistors N4 together, and also contributes to reduce the area occupied by the N-channel type MOS transistors N2 and N4, according to the equivalent circuit shown in FIG. 8.
- Referring to FIG. 9, n+ diffusion areas FL33 and FL32 are formed by injecting an N-type impurity at positions sandwiching the polysilicon wiring layer PL31. Thus, there is formed an N-channel type MOS transistor N9 that uses the polysilicon wiring layer PL31 as a gate electrode. Further, n+ diffusion areas FL32 and FL31 are formed at positions sandwiching the polysilicon wiring layer PL12. Thus, there is formed an N-channel type MOS transistor N8 that uses the polysilicon wiring layer PL12 as a gate electrode.
- These N-channel type MOS transistors N8 and N9 have the polysilicon wiring layer PL31 and PL12 disposed in parallel with each other. Therefore, it is possible to dispose the n+ diffusion areas FL31 to FL33 in a direction parallel with the second well boundary line and also in a straight line. With this arrangement, the N-channel type MOS transistors N8 and N9 can share the n+ diffusion area FL32. The sharing of this n+ diffusion area FL32 makes it possible to connect the drain of the N-channel type MOS transistors N8 and the source of the N-channel type MOS transistor N9 together, and also contributes to reduce the area occupied by the N-channel type MOS transistors N8 and N9, according to the equivalent circuit shown in FIG. 8.
- In the N-well area NW, p+ diffusion areas FL11 and FL12 are formed by injecting a P-type impurity at positions sandwiching the polysilicon wiring layer PL11. Thus, there is formed a P-channel type MOS transistor P1 that uses the polysilicon wiring layer PL11 as a gate electrode. Further, p+ diffusion areas FL13 and FL14 are formed at positions sandwiching the polysilicon wiring layer PL12. Thus, there is formed a P-channel type MOS transistor P2 that uses the polysilicon wiring layer PL12 as a gate electrode.
- Positions of the P-channel type MOS transistors P1 and P2 are determined based on the positions of the polysilicon wiring layers PL11 and PL12. Distance between the polysilicon wiring layers PL11 and PL12 can be reduced to about the size of the p+ diffusion area FL12 or the FL13 (minimum pitch of the transistor) as shown in FIG. 9, like in the first embodiment. Particularly, when the sizes of the p+ diffusion areas FL12 and FL13 are set approximately equal to the sizes of the n+ diffusion area FL22 in the first P-well area PW1 and the n+ diffusion areas FL32 and FL35 in the second P-well area PW2, it is possible to minimize the total area required for the layout of the memory cell.
- The above arrangement also means that it is possible to dispose the polysilicon wiring layers PL11, PL33 and PL31 on the same straight line, and it is also possible to dispose the polysilicon wiring layers PL21 and PL12 on the same straight line.
- In order to have an electrical connection with the upper layer, there is one contact hole provided on each of the polysilicon wiring layers PL11, PL12, PL21, PL31 and PL33, the p+ diffusion areas FL11 to FL14, and the n+ diffusion areas FL21 to FL23 and FL33 to FL36, as shown in FIG. 9. There are also two contact holes provided in the n+ diffusion area FL31.
- Next, layers positioned above the layers shown in FIG. 9 will be explained. FIG. 10 shows layers including first metal-wiring layers formed on the layers shown in FIG. 9. As one of layers shown in FIG. 10, there is formed a first metal-wiring layer AL11 for electrically connecting the lower-layer n+ diffusion area FL22, the p+ diffusion area FL12, and the polysilicon wiring layer PL12. This first metal-wiring layer AL11 makes it possible to connect the drain of the N-channel type MOS transistors N1, the source of the N-channel type MOS transistor N3, the drain of the P-channel type MOS transistor P1, and the input terminal of the second CMOS inverter, according to the equivalent circuit shown in FIG. 8.
- Further, there is formed a first metal-wiring layer AL12 for electrically connecting between the lower-layer n+ diffusion area FL35, the p+ diffusion area FL13, and the polysilicon wiring layer PL11. This second metal-wiring layer AL12 makes it possible to connect between the drain of the N-channel type MOS transistor N2, the sources of the N-channel type MOS transistor N4, the drain of the P-channel type MOS transistor P2, and the input terminal of the first CMOS inverter, according to the equivalent circuit shown in FIG. 8.
- Particularly, in the first metal-wiring layer AL11, the contact points of the n+ diffusion area FL22 and the p+ diffusion area FL12 are disposed on the same straight line as described above. Therefore, it is possible to form a wire for connecting between these two points in a straight-line shape. The above similarly applies to the first metal-wiring layer AL12.
- Further, in layers shown in FIG. 10, there are formed a first metal-wiring layer AL15 for moving the connection point of the lower-layer p+ diffusion area FL11, and a first metal-wiring layer AL16 for moving the connection point of the p+ diffusion area FL14. There are also formed a first metal-wiring layer AL13 for moving the connection point of the lower-layer polysilicon wiring layer PL21, a first metal-wiring layer AL14 for moving the connection point of the polysilicon wiring layer PL31, and a first metal-wiring layer AL19 for moving the connection point of the polysilicon wiring layer PL33.
- Further, on the same layer, there is formed a first metal-wiring layer AL18 for electrically connecting the lower-layer p+ diffusion areas FL34 and FL31, and for moving the connection point with the upper layer. This first metal-wiring layer AL18 makes it possible to connect the sources of the N-channel type MOS transistors N2 and N8 together, according to the equivalent circuit shown in FIG. 8.
- Particularly, as shown in FIG. 9, the n+ diffusion areas FL34 and FL31 are disposed on the same straight line perpendicular to the second well boundary line. Therefore, the contact holes on these n+ diffusion area scan also be formed on the same straight line on which a straight line connecting between these contact holes is perpendicular to the second well boundary line. In other words, it is possible to form the second metal-wiring layer AL18 shown in FIG. 10 in a straight-line shape perpendicular to the second well boundary line.
- Next, layers positioned above the layers shown in FIG. 10 will be explained. FIG. 11 shows layers including second metal-wiring layers formed on the layers shown in FIG. 10. As one of layers shown in FIG. 11, there is formed a second metal-wiring layer AL21 for applying a power source potential VDD to the p+ diffusion area FL11 via the first metal-wiring layer AL15 shown in FIG. 10 and for applying a power source potential VDD to the p+ diffusion area FL14 via the first metal-wiring layer AL16. In other words, the second metal-wiring layer AL21 functions as a power source potential VDD line, and achieves a connection between the source of the P-channel type MOS transistor P1 and the power source and a connection between the source of the P-channel type MOS transistor P2 and the power source, in the equivalent circuit shown in FIG. 8.
- Further, there are formed a second metal-wiring layer AL22 for applying a ground potential GND to the p+ diffusion area FL21 via a first metal wiring layer AL17 shown in FIG. 10, and a second metal-wiring layer AL23 for applying a ground potential GND to the p+ diffusion areas FL31 and FL34 respectively via a first metal wiring layer AL18 shown in FIG. 10. In other words, the second metal-wiring layers AL22 and AL23 function as a ground potential GND line respectively, and achieve a grounding of each source of the N-channel type MOS transistors N1, N2 and N8 respectively, in the equivalent circuit shown in FIG. 8.
- Further, as layers shown in FIG. 11, there are formed a second metal-wiring layer AL24 that is connected with the lower-layer p+ diffusion area FL23 and functions as a first positive-phase bit line WBL1, a second metal-wiring layer AL25 that is connected with the p+ diffusion area FL36 and functions as a negative-phase bit line WBL2, and a second metal-wiring layer AL26 that is connected with the p+ diffusion area FL33 and functions as a second positive-phase bit line RBL, via the contact holes and the first via holes shown in FIG. 10 respectively.
- In other words, these second metal-wiring layers AL24 to AL26 achieve a connection between the other semiconductor terminal end (drain) of the N-channel type MOS transistor N3 and the first positive-phase bit line WBL1, a connection between the other semiconductor terminal end (drain) of the N-channel type MOS transistor N4 and the negative-phase bit line WBL2, and a connection between the other semiconductor terminal end (drain) of the N-channel type MOS transistor N9 and the second positive-phase bit line RBL, respectively, in the equivalent circuit shown in FIG. 8.
- Particularly, it is possible to form the second metal-wiring layers AL24 to AL26 in a straight-line shape respectively extending in a direction parallel with the first well boundary line. This means that it is possible to further reduce the length of each of the first positive-phase bit line WBL1, the negative-phase bit line WBL2, and the second positive-phase bit line RBL, within one memory cell.
- Further, as layers shown in FIG. 11, there are formed a second metal-wiring layer AL27 for moving the connection point between the lower-layer first metal wiring layer AL13 and the upper layer, a second metal-wiring layer AL28 for moving the connection point between the lower-layer first metal wiring layer AL19 and the upper layer, and a second metal-wiring layer AL29 for moving the connection point between the lower-layer first metal wiring layer AL14 and the upper layer.
- Next, layers positioned above the layers shown in FIG. 11 will be explained. FIG. 12 shows layers including third metal-wiring layers formed on the layers shown in FIG. 11. As one of layers shown in FIG. 12, there is formed a third metal-wiring layer AL31 for electrically connecting the polysilicon wiring layers PL21 and PL33 via the first metal wiring layer AL13 and the second metal wiring layer AL27 and also for functioning as a word line WWL. In other words, the third metal-wiring layer AL31 achieves a connection between the gates of the N-channel type MOS transistors N3 and N4 and the word line WWL, in the equivalent circuit shown in FIG. 8.
- Further, there is formed a third metal-wiring layer AL32 for electrically connecting with the polysilicon wiring layer PL31 via the first metal wiring layer AL14 and the second metal wiring layer AL29 and for functioning as a word line RWL. In other words, the third metal-wiring layer AL32 achieves a connection between the gate of the N-channel type MOS transistor N6 and the word line RWL, in the equivalent circuit shown in FIG. 8.
- Particularly, as shown in FIG. 12, from the positional relationship between the second metal wiring layers AL27 and AL28, these metal wiring layers can be connected by a straight-line shaped metal wiring layer extending in a direction perpendicular to the first well boundary line. In other words, it is possible to form the third metal wiring layer AL31 shown in FIG. 12 in a straight-line shape extending in a direction perpendicular to the first well boundary line. In the mean time, as the third metal wiring layer AL32 is connected with only the second metal wiring layer AL29 as a lower layer, it is possible to dispose the third metal wiring layer AL32 in the extension parallel with the third metal wiring layer AL31. This means that it is possible to further reduce the length of each of the first word line WWL and the second word line RWL within one memory cell.
- As explained above, according to the semiconductor memory device of the third embodiment, the N-channel type MOS transistor N3 that functions as an access gate and the N-channel type MOS transistor N1 that structures a flip-flop circuit share the n+ diffusion area FL22 at a connection point between respective semiconductor terminals. At the same time, the n+ diffusion areas FL21 to FL23 that become the respective semiconductor terminals are formed on the same straight line parallel with the first well boundary line. Therefore, it is possible to reduce the area occupied by the N-channel type MOS transistors N1 and N3. This makes it possible to increase the integration degree of the memory cell array.
- Further, the second metal-wiring layers AL24 to AL26 that function as the first positive-phase bit line WBL1, the negative-phase bit line WBL2, and the first positive-phase bit line WBL2 in this order respectively are formed in parallel with the first and second well boundary lines respectively. Therefore, each bit line length can be reduced. As a result, it is possible to reduce the amount of wiring of the bit lines, which makes it possible to achieve a high-speed accessing. Particularly, each bit line length can be reduced to a double of the minimum pitch of the transistors based on the above arrangement.
- Further, the third metal-wiring layers AL31 and AL32 that function as the first word line WWL and the second word line RWL respectively are formed so that these layers are orthogonal with the first and second well boundary lines respectively. Therefore, each word line length can be reduced. As a result, it is possible to reduce the amount of wiring of the word lines, which makes it possible to achieve a high-speed accessing.
- Further, as the drain areas for forming the memory nodes MA and MB are made in a common n+ diffusion area, it is possible to reduce the size of these areas. As a result, a parasitic capacitance can be reduced, which makes it possible to achieve a writing access at a higher speed.
- Further, as the polysilicon layer can be formed in a straight line, it is possible to take a large process margin for a mask deviation or the like at the time of forming a layout pattern, in the process of manufacturing a semiconductor device.
- Next, a semiconductor memory device of a fourth embodiment will be explained. The fourth embodiment is for explaining a layout structure of other equivalent circuit that structures a three-port SRAM cell. FIG. 13 shows an equivalent circuit of the semiconductor memory device of the fourth embodiment. In FIG. 13, a first word line WWL, a first positive-phase bit line WBL1, a first negative-phase bit line WBL2, P-channel type MOS transistors P1 and P2, and N-channel type MOS transistors N1 to N4 areas shown in FIG. 8. Therefore, their explanation will be omitted here.
- In FIG. 13, in addition to the above-described structure, the gate of the N-channel type MOS transistor N8 is connected to the memory node MA, and the source of the N-channel type MOS transistor N8 is grounded. Further, the drain of the N-channel type MOS transistor N8 is connected to the source of the N-channel type MOS transistor N9. The gate of the N-channel type MOS transistor N9 is connected to a second word line RWL1, and the drain is connected to a second positive-phase bit line RBL1.
- The gate of the N-channel type MOS transistor N10 is connected to the memory node MB, and the source of the N-channel type MOS transistor N10 is grounded. Further, the drain of the N-channel type MOS transistor N10 is connected to the source of an N-channel type MOS transistor N11. The gate of the N-channel type MOS transistor N11 is connected to a third word line RWL2, and the drain is connected to a second negative-phase bit line RBL2.
- In other words, it is possible to read and write a memory value of a first port by selecting the word line WWL, the first positive-phase bit line WBL1 and the negative-phase bit line WBL2. It is possible to read a memory value of a second port by selecting the second word line RWL1 and the second positive-phase bit line RBL1. Further, it is possible to read a memory value of a third port by selecting the third word line RWL2 and the second negative-phase bit line RBL2. Particularly, the read operation based on the second and third ports has a characteristic in that this operation can be carried out completely independent of the first port, without destroying the data of the memory nodes MA and MB of the memory cell.
- The equivalent circuit itself shown in FIG. 13 has a known structure as the conventional three-port SRAM cell. However, in the semiconductor memory device of the fourth embodiment, there is a characteristic in the construction of the memory cell. FIG. 14 to FIG. 17 are layout diagrams of the memory cell of the semiconductor memory device of the fourth embodiment. FIG. 6 explains various symbols like a contact hole, a via hole, etc. shown in FIG. 14 to FIG. 17.
- FIG. 14 shows layers including well areas formed on a semiconductor substrate, diffusion areas formed in the well areas, and a polysilicon wiring layer formed on the upper surface.
- In the memory cell of the semiconductor memory device of the fourth embodiment as well, there are formed a first P-well area PW1 and a second P-well area PW2 by sandwiching the N-well area NW in a plain direction on the semiconductor substrate, as shown in FIG. 14, in a similar manner to that of the first embodiment. Further, these well areas are formed so that the first well boundary line and the second well boundary line are parallel with each other. Although not shown in FIG. 14, there exist a separation area between the N-well area NW and the first P-well area PW1 and between the N-well area NW and the second P-well area PW2 respectively.
- In FIG. 14, the N-channel type MOS transistors N1, N3, N10 and N11 shown in FIG. 13 are formed in the first P-well area PW1. The P-channel type MOS transistors P1 and P2 shown in FIG. 13 are formed in the N-well area NW. Further, the N-channel type MOS transistors N2, N4, N8 and N9 shown in FIG. 13 are formed in the second P-well area PW2.
- The construction of each layer shown in FIG. 14 to FIG. 17 will be explained in sequence. First, in the layers shown in FIG. 14, two polysilicon wiring layers PL21 and PL22 are formed in the first P-well area PW1, extending in parallel in a direction perpendicular to the first well boundary line.
- Further, a polysilicon wiring layer PL11 is disposed in the area from the first P-well area PW1 to the N-well area NW, extending in a straight line in a direction perpendicular to the first well boundary line. One end of the polysilicon wiring layer PL11 is positioned on the second well boundary line as shown in FIG. 14.
- There are formed n+ diffusion areas FL22 and FL23 by injecting an N-type impurity at positions sandwiching the polysilicon wiring layer PL21. Thus, there is formed an N-channel type MOS transistor N3 that uses the polysilicon wiring layer PL21 as a gate electrode. Further, n+ diffusion areas FL21 and FL22 are formed at positions sandwiching the polysilicon wiring layer PL11. Thus, there is formed an N-channel type MOS transistor N1 that uses the polysilicon wiring layer PL11 as a gate electrode.
- Particularly, as the polysilicon wiring layers PL11 and PL21 are disposed in parallel in the N-channel type MOS transistors N1 and N3 respectively, it is possible to dispose the n+ diffusion areas FL21 to FL23 in a direction parallel with the first well boundary line and also in a straight line. With this arrangement, the N-channel type MOS transistors N1 and N3 can share the n+ diffusion area FL22. The sharing of this n+ diffusion area FL22 makes it possible to connect the drain of the N-channel type MOS transistors N1 and the source of the N-channel type MOS transistors N3 together, and also contributes to reduce the area occupied by the N-channel type MOS transistors N1 and N3, according to the equivalent circuit shown in FIG. 13.
- In FIG. 14, there are formed n+ diffusion areas FL25 and FL26 by injecting an N-type impurity at positions sandwiching the polysilicon wiring layer PL22. Thus, there is formed an N-channel type MOS transistor N11 that uses the polysilicon wiring layer PL22 as a gate electrode. Further, n+ diffusion areas FL24 and FL25 are formed at positions sandwiching the polysilicon wiring layer PL11. Thus, there is formed an N-channel type MOS transistor N10 that uses the polysilicon wiring layer PL11 as a gate electrode.
- As the polysilicon wiring layers PL22 and PL11 are disposed in parallel in the N-channel type MOS transistors N10 and N11 respectively, it is possible to dispose the n+ diffusion areas FL24 to FL26 in a direction parallel with the first well boundary line and also in a straight line. With this arrangement, the N-channel type MOS transistors N10 and N11 can share the n+ diffusion area FL25. The sharing of this n+ diffusion area FL25 makes it possible to connect the drain of the N-channel type MOS transistors N10 and the source of the N-channel type MOS transistors N11 together, and also contributes to reduce the area occupied by the N-channel type MOS transistors N10 and N11, according to the equivalent circuit shown in FIG. 13.
- In the mean while, the formation of the diffusion area and the polysilicon wiring layer in the second P-well area PW2 and the N-well area NW is as explained in the third embodiment with reference to FIG. 9. Therefore, their explanation will be omitted here.
- Therefore, as shown in FIG. 14, the polysilicon wiring layers PL11, PL33 and PL31 are disposed on the same straight line, and the polysilicon wiring layers PL21, PL22 and PL12 are disposed on the same straight line.
- In order to have an electrical connection with the upper layer, there is one contact hole provided on each of the polysilicon wiring layers PL11, PL12, PL21, PL22, PL31 and PL33, the p+ diffusion areas FL11 to FL14, and the n+ diffusion areas FL21 to FL23, FL26, and FL33 to FL36, as shown in FIG. 14. There are also two contact holes provided in the n+ diffusion areas FL24 and FL31.
- Next, layers positioned above the layers shown in FIG. 14 will be explained. FIG. 15 shows layers including first metal-wiring layers formed on the layers shown in FIG. 14. In the layers shown in FIG. 15, the formation of the second metal wiring layers in the second P-well area PW2 and the N-well area NW is as explained in the third embodiment with reference to FIG. 10. Therefore, their explanation will be omitted here.
- In layers shown in FIG. 15, in the first P-well area PW1, there is formed a first metal-wiring layer AL11 for electrically connecting the lower-layer n+ diffusion area FL22, the p+ diffusion area FL12, and the polysilicon wiring layer PL12. This first metal-wiring layer AL11 makes it possible to connect the drain of the N-channel type MOS transistors N1, the source of the N-channel type MOS transistor N3, the drain of the P-channel type MOS transistor P1, and the input terminal of the second CMOS inverter, according to the equivalent circuit shown in FIG. 13.
- Particularly, in the first metal-wiring layer AL11, the contact points of the n+ diffusion area FL22 and the p+ diffusion area FL12 are disposed on the same straight line as described above. Therefore, it is possible to form a wire for connecting between these two points in a straight-line shape.
- Further, in layers shown in FIG. 15, there are formed a first metal-wiring layer AL13 for moving the connection point of the lower-layer polysilicon wiring layer PL22, and a first metal-wiring layer AL10 for moving the connection point of the polysilicon wiring layer PL21.
- Further, on the same layer, there is formed a first metal-wiring layer AL17 for electrically connecting the lower-layer p+ diffusion areas FL24 and FL21, and for moving the connection point with the upper layer. This first metal-wiring layer AL17 makes it possible to connect the sources of the N-channel type MOS transistors N1 and N10 together, according to the equivalent circuit shown in FIG. 13.
- Particularly, as shown in FIG. 14, the n+ diffusion areas FL24 and FL21 are disposed on the same straight line perpendicular to the first well boundary line. Therefore, the contact holes on these n+ diffusion areas can also be formed on the same straight line on which a straight line connecting between these contact holes is perpendicular to the first well boundary line. In other words, it is possible to form the second metal-wiring layer AL17 shown in FIG. 15 in a straight-line shape perpendicular to the first well boundary line.
- Next, layers positioned above the layers shown in FIG. 15 will be explained. FIG. 16 shows layers including second metal-wiring layers formed on the layers shown in FIG. 15. As one of layers shown in FIG. 16, there is formed a second metal-wiring layer AL21 for applying a power source potential VDD to the p+ diffusion area FL11 via the first metal-wiring layer AL15 shown in FIG. 15 and for applying a power source potential VDD to the p+ diffusion area FL14 via the first metal-wiring layer AL16. In other words, the second metal-wiring layer AL21 functions as a power source potential VDD line, and achieves a connection between the source of the P-channel type MOS transistor P1 and the power source and a connection between the source of the P-channel type MOS transistor P2 and the power source, in the equivalent circuit shown in FIG. 13.
- Further, there are formed a second metal-wiring layer AL22 for applying a ground potential GND to the p+ diffusion areas FL21 and FL24 via a first metal wiring layer AL17 shown in FIG. 15, and a second metal-wiring layer AL23 for applying a ground potential GND to the p+ diffusion areas FL31 and FL34 respectively via a first metal wiring layer AL18 shown in FIG. 15. In other words, the second metal-wiring layers AL22 and AL23 function as a ground potential GND line respectively, and achieve a grounding of each source of the N-channel type MOS transistors N1, N2, N8 and N10 respectively, in the equivalent circuit shown in FIG. 13.
- Further, as layers shown in FIG. 16, there are formed a second metal-wiring layer AL24 that is connected with the lower-layer p+ diffusion area FL23 and functions as a first positive-phase bit line WBL1, a second metal-wiring layer AL42 that is connected with the lower-layer p+ diffusion area FL26 and functions as a second negative-phase bit line RBL2, a second metal-wiring layer AL25 that is connected with the p+ diffusion area FL36 and functions as a negative-phase bit line WBL2, and a second metal-wiring layer AL26 that is connected with the p+ diffusion area FL33 and functions as a second positive-phase bit line RBL1, via the contact holes and the first via holes shown in FIG. 15 respectively.
- In other words, these second metal-wiring layers AL24 to AL26 and AL42 achieve a connection between the other semiconductor terminal end (drain) of the N-channel type MOS transistor N3 and the first positive-phase bit line WBL1, a connection between the other semiconductor terminal end (drain) of the N-channel type MOS transistor N4 and the negative-phase bit line WBL2, a connection between the other semiconductor terminal end (drain) of the N-channel type MOS transistor N9 and the second positive-phase bit line RBL1, and a connection between the other semiconductor terminal end (drain) of the N-channel type MOS transistor N11 and the second negative-phase bit line RBL2, respectively, in the equivalent circuit shown in FIG. 13.
- Particularly, it is possible to form the second metal-wiring layers AL24 to AL26 and AL42 in a straight-line shape respectively extending in a direction parallel with the first well boundary line. This means that it is possible to further reduce the length of each of the first positive-phase bit line WBL1, the negative-phase bit line WBL2, the second positive-phase bit line RBL1, and the second negative-phase bit line RBL2 within one memory cell.
- Further, as layers shown in FIG. 16, there are formed a second metal-wiring layer AL41 for moving the connection point between the lower-layer first metal wiring layer AL13 and the upper layer, a second metal-wiring layer AL28 for moving the connection point between the lower-layer first metal wiring layer AL19 and the upper layer, and a second metal-wiring layer AL27 for moving the connection point between the lower-layer first metal wiring layer AL10 and the upper layer. Further, there is formed a second metal-wiring layer AL29 for connecting between the polysilicon wiring layer PL31 and the upper layer via the lower-layer first metal wiring layer AL14.
- Next, layers positioned above the layers shown in FIG. 16 will be explained. FIG. 17 shows layers including third metal-wiring layers formed on the layers shown in FIG. 16. As one of layers shown in FIG. 17, there is formed a third metal-wiring layer AL31 for electrically connecting the polysilicon wiring layers PL21 and PL33 via the first metal wiring layer AL10 and the second metal wiring layer AL27 and also for functioning as a first word line WWL. In other words, the third metal-wiring layer AL31 achieves a connection between the gates of the N-channel type MOS transistors N3 and N4 and the first word line WWL, in the equivalent circuit shown in FIG. 13.
- Further, there is formed a third metal-wiring layer AL32 for electrically connecting with the polysilicon wiring layer PL31 via the first metal wiring layer AL14 and the second metal wiring layer AL29 and for functioning as a second word line RWL1. In other words, the third metal-wiring layer AL32 achieves a connection between the gate of the N-channel type MOS transistor N6 and the second word line RWL1, in the equivalent circuit shown in FIG. 13.
- Further, there is formed a third metal-wiring layer AL33 for electrically connecting with the polysilicon wiring layer PL22 via the first metal wiring layer AL13 and the second metal wiring layer AL41 and for functioning as a third word line RWL2. In other words, the third metal-wiring layer AL33 achieves a connection between the gate of the N-channel type MOS transistor N11 and the third word line RWL2, in the equivalent circuit shown in FIG. 13.
- Particularly, as shown in FIG. 17, from the positional relationship between the second metal wiring layers AL27 and AL28, these metal wiring layers can be connected by a straight-line shaped metal wiring layer extending in a direction perpendicular to the first well boundary line. In other words, it is possible to form the third metal wiring layer AL31 shown in FIG. 17 in a straight-line shape extending in a direction perpendicular to the first well boundary line. In the mean time, the third metal wiring layer AL32 is connected with only the second metal wiring layer AL29 as a lower layer, and the third metal wiring layer AL33 is connected with only the second metal wiring layer AL41 as a lower layer. Therefore, it is possible to dispose these third metal wiring layers in the extension parallel with the third metal wiring layer AL31. This means that it is possible to further reduce the length of each of the first word line WWL, the second word line RWL1, and the third word line RWL2, within one memory cell.
- As explained above, according to the semiconductor memory device of the fourth embodiment, it is also possible to obtain the effect of the third embodiment in the three-port SRAM cell as well.
- Next, a semiconductor memory device of a fifth embodiment will be explained. The fifth embodiment is for explaining a layout structure of other equivalent circuit that structures a differential-reading-type two-port SRAM cell. FIG. 18 shows an equivalent circuit of the semiconductor memory device of the fifth embodiment.
- The equivalent circuit shown in FIG. 18 is different from that of the fourth embodiment only in that the gates of the N-channel type MOS transistors N9 and N11 are connected together, and the connection line is used as a common second word line RWL, in the equivalent circuit shown in FIG. 13. All other structures are as shown in FIG. 13, and therefore, their explanation will be omitted here.
- Accordingly, the operation is also similar to that of the equivalent circuit shown in FIG. 13 except that the read operation is carried out based on the difference between the potential of the second positive-phase bit line RBL1 and the potential of the second negative-phase bit line RBL2.
- The layout structure is different only in the second metal wiring layer corresponding to that shown in FIG. 16 and the third metal wiring layer corresponding to that shown in FIG. 17. All other lower-layer structures are as shown in FIG. 14 and FIG. 15. Therefore, their explanation will be omitted here.
- Therefore, layers positioned above the layers shown in FIG. 15 will be explained. FIGS. 19 and 20 are layout diagrams of the memory cell of the semiconductor memory device in the fifth embodiment. Particularly, FIG. 19 shows a layer including the second metal wiring layer corresponding to that shown FIG. 16. FIG. 20 shows a layer including the third metal wiring layer corresponding to that shown FIG. 17.
- First, as one of layers shown in FIG. 19, there is formed a second metal-wiring layer AL21 for applying a power source potential VDD to the p+ diffusion area FL11 via the first metal-wiring layer AL15 shown in FIG. 15 and for applying a power source potential VDD to the p+ diffusion area FL14 via the first metal-wiring layer AL16. In other words, the second metal-wiring layer AL21 functions as a power source potential VDD line, and achieves a connection between the source of the P-channel type MOS transistor P1 and the power source and a connection between the source of the P-channel type MOS transistor P2 and the power source, in the equivalent circuit shown in FIG. 18.
- Further, there are formed a second metal-wiring layer AL22 for applying a ground potential GND to the p+ diffusion areas FL21 and FL24 via a first metal wiring layer AL17 shown in FIG. 15, and a second metal-wiring layer AL23 for applying a ground potential GND to the p+ diffusion areas FL31 and FL34 respectively via a first metal wiring layer AL18 shown in FIG. 15. In other words, the second metal-wiring layers AL22 and AL23 function as a ground potential GND line respectively, and achieve a grounding of each source of the N-channel type MOS transistors N1, N2, N8 and N10 respectively, in the equivalent circuit shown in FIG. 18.
- Further, as layers shown in FIG. 19, there are formed a second metal-wiring layer AL24 that is connected with the lower-layer p+ diffusion area FL23 and functions as a first positive-phase bit line WBL1, a second metal-wiring layer AL42 that is connected with the lower-layer p+ diffusion area FL26 and functions as a second negative-phase bit line RBL2, a second metal-wiring layer AL25 that is connected with the p+ diffusion area FL36 and functions as a negative-phase bit line WBL2, and a second metal-wiring layer AL26 that is connected with the p+ diffusion area FL33 and functions as a second positive-phase bit line RBL1, via the contact holes and the first via holes shown in FIG. 15 respectively.
- In other words, these second metal-wiring layers AL24 to AL26 and AL42 achieve a connection between the other semiconductor terminal end (drain) of the N-channel type MOS transistor N3 and the first positive-phase bit line WBL1, a connection between the other semiconductor terminal end (drain) of the N-channel type MOS transistor N4 and the negative-phase bit line WBL2, a connection between the other semiconductor terminal end (drain) of the N-channel type MOS transistor N9 and the second positive-phase bit line RBL1, and a connection between the other semiconductor terminal end (drain) of the N-channel type MOS transistor N11 and the second negative-phase bit line RBL2, respectively, in the equivalent circuit shown in FIG. 18.
- Particularly, it is possible to form the second metal-wiring layers AL24 to AL26 and AL42 in a straight-line shape respectively extending in a direction parallel with the first well boundary line. This means that it is possible to further reduce the length of each of the first positive-phase bit line WBL1, the negative-phase bit line WBL2, the second positive-phase bit line RBL1, and the second negative-phase bit line RBL2 within one memory cell.
- Further, as layers shown in FIG. 19, there are formed a second metal-wiring layer AL41 for moving the connection point between the lower-layer first metal wiring layer AL13 and the upper layer, a second metal-wiring layer AL28 for moving the connection point between the lower-layer first metal wiring layer AL19 and the upper layer, and a second metal-wiring layer AL27 for moving the connection point between the lower-layer first metal wiring layer AL10 and the upper layer. Further, there is formed a second metal-wiring layer AL29 for connecting between the polysilicon wiring layer PL31 and the upper layer via the lower-layer first metal wiring layer AL14.
- Next, layers positioned above the layers shown in FIG. 19 will be explained. FIG. 20 shows layers including third metal-wiring layers formed on the layers shown in FIG. 19. As one of layers shown in FIG. 20, there is formed a third metal-wiring layer AL31 for electrically connecting the polysilicon wiring layers PL21 and PL33 via the first metal wiring layer AL10 and the second metal wiring layer AL27 and also for functioning as a first word line WWL. In other words, the third metal-wiring layer AL31 achieves a connection between the gates of the N-channel type MOS transistors N3 and N4 and the first word line WWL, in the equivalent circuit shown in FIG. 18.
- Further, there is formed a third metal-wiring layer AL32 for electrically connecting between the polysilicon wiring layers PL22 and PL31 via the first metal wiring layer AL14 and the second metal wiring layer AL29 and for functioning as a second word line RWL. In other words, the third metal-wiring layer AL32 achieves a connection between the gates of the N-channel type MOS transistor N9 and N11 and the second word line RWL, in the equivalent circuit shown in FIG. 18.
- Particularly, as shown in FIG. 20, from the positional relationship between the second metal wiring layers AL27 and AL28, these metal wiring layers can be connected by a straight-line shaped metal wiring layer extending in a direction perpendicular to the first well boundary line. In other words, it is possible to form the third metal wiring layer AL31 shown in FIG. 20 in a straight-line shape extending in a direction perpendicular to the first well boundary line. This similarly applies to the third metal-wiring layer AL32. This means that it is possible to further reduce the length of each of the first word line WWL and the second word line RWL, within one memory cell.
- As explained above, according to the semiconductor memory device of the fifth embodiment, it is also possible to obtain the effect of the third embodiment in the differential-reading type two-port SRAM cell that can execute a reading operation at a higher speed, as well.
- As explained above, according to the present invention, the first, third and fifth N-channel type MOS transistors that are electrically connected to the positive-phase bit line and the second, fourth and sixth N-channel type MOS transistors that are connected to the negative-phase bit line are formed in the divided P-well areas respectively. Therefore, when these well areas are disposed in a direction perpendicular to the positive-phase and negative-phase bit lines respectively, it is possible to use a layout having a short length for the bit lines. As a result, there is an effect that it is possible to achieve a high-speed accessing.
- Further, as the first and second P-well areas are formed on the two sides of the N-well area, it is possible to make uniform the distances of wiring connection between the N-channel type MOS transistors formed in the first and second P-well areas respectively and the P-channel type MOS transistors formed in the N-well area. As a result, there is an effect that it is possible to employ an optimum layout for a shortest wiring.
- Further, the extension directions of the bit lines are parallel with the boundary lines between the first and second P-well areas and the N-well area respectively. Therefore, it is possible to provide a layout having each bit line formed in a shortest length by taking into consideration a reduction in the length of each word line.
- Further, the extension direction of each word line is perpendicular to the boundary lines between the first and second P-well areas and the N-well area respectively. Therefore, it is possible to provide a layout having each word line formed in a shortest length by taking into consideration a reduction in the length of each bit line with priority.
- Further, as the first P-channel type MOS transistor and the gate areas of the first, third and fourth N-channel type MOS transistors are formed to be positioned on the same straight line, it is possible to form wires for connecting between the gates in a straight-line shape. Further, as the second P-channel type MOS transistor and the gate areas of the second, fifth and sixth N-channel type MOS transistors are also formed to be positioned on the same straight line, it is possible to form wires for connecting between the gates in a straight-line shape. As a result, there is an effect that it is possible to obtain shorter wiring.
- Further, as each source and each drain of the third and fifth N-channel type MOS transistors that function as an access gate are positioned on the same straight line, it is possible to reduce the disposition distance between the third and fifth N-channel type MOS transistors. Further, as each source and each drain of the fourth and sixth N-channel type MOS transistors are also positioned on the same straight line, it is possible to reduce the disposition distance between the fourth and sixth N-channel type MOS transistors. As a result, there is an effect that it is possible to improve the degree of integration of the memory cell.
- Further, as the drain diffusion areas are formed in a common n+ diffusion area for the third and fifth N-channel type MOS transistors and for the fourth and sixth N-channel type MOS transistors respectively, it is possible to reduce the size of the n+ diffusion areas. As a result, there is an effect that it is possible to reduce a parasitic capacitance due to the n+ diffusion area.
- Further, the drain diffusion area of the first N-channel type MOS transistor and the drain diffusion areas of the third and fifth N-channel type MOS transistors are connected to each other by the upper-layer first metal-wiring layer, and the drain diffusion area of the second N-channel type MOS transistor and the drain diffusion areas of the fourth and sixth N-channel type MOS transistors are connected to each other by the upper-layer second metal-wiring layer. Therefore, it is possible to form the first and second metal-wiring layers in a straight-line shape according to the positions of the drain diffusion areas. As a result, there is an effect that it is possible to obtain shorter wiring.
- Further, as the extension direction of the first and second metal-wiring layers is parallel with an extension direction of each word line, it is possible to optimize the length of the metal-wiring layers like the word lines.
- Further, the extension lines of the bit lines, the power source line and the GND line are perpendicular to each word line. Therefore, it is possible to minimize the respective length of these lines. As a result, there is an effect that it is possible to achieve a high-speed accessing.
- Further, as the drain diffusion areas are formed in a common n+ diffusion area for the first, third and fifth N-channel type MOS transistors and for the second, fourth and sixth N-channel type MOS transistors respectively, it is possible to omit the metal-wiring layers between these drain diffusion areas.
- Further, the first n+ diffusion area and the drain diffusion area of the first P-channel type MOS transistor and the second n+ diffusion area and the drain diffusion area of the second P-channel type MOS transistor are connected to each other by the upper-layer second metal-wiring layers respectively. Therefore, it is possible to form the metal-wiring layers in a straight-line shape according to the positions of the drain diffusion areas and the n+ diffusion areas. As a result, there is an effect that it is possible to obtain shorter wiring.
- According to another aspect of this invention, in a circuit that structures a dual port SRAM cell with fifth and sixth N-channel type MOS transistors formed as reading ports, first, third, and the fifth N-channel type MOS transistors electrically connected to a positive-phase bit line, and second and fourth N-channel type MOS transistors connected to a negative-phase bit line are formed in separated P-well areas, respectively. Therefore, the juxtaposing direction of these well areas in particular is made perpendicular to the direction of the positive-phase and negative-phase bit lines, which makes it possible to apply a layout with the decreased length of the bitlines. As a result, there is an effect that it is possible to achieve a high-speed accessing.
- Further, in a circuit that structures a three port SPAM cell in which the fifth and sixth N-channel type MOS transistors are formed as first reading ports, and seventh and eighth N-channel type MOS transistors are formed as second reading ports, the first, third, and fifth N-channel type MOS transistors electrically connected to the positive-phase bit line, and the second, fourth, and seventh N-channel type MOS transistors connected to the negative-phase bit line are formed in the separated P-well areas, respectively. Therefore, the juxtaposing direction of these well areas in particular is made perpendicular to the direction of the positive-phase and negative-phase bit lines, which makes it possible to apply a layout with the decreased length of the bit lines. As a result, there is an effect that it is possible to achieve a high-speed accessing.
- Further, in a circuit that structures a difference reading type of dual port SRAM cell for performing reading operation based on a potential difference between a second positive-phase bit line and a second negative-phase bit line, the first, third, and fifth N-channel type MOS transistors electrically connected to the positive-phase bit line, and the second, fourth, and seventh N-channel type MOS transistors connected to the negative-phase bit line are formed in the separated P-well areas, respectively. Therefore, the juxtaposing direction of these well areas in particular is made perpendicular to the direction of the positive-phase and negative-phase bit lines, which makes it possible to apply a layout with the decreased length of the bitlines. As a result, there is an effect that it is possible to achieve a high-speed accessing.
- Further, as first and second P-well areas are disposed on both sides of an N-well area, the distances of connection wiring between the N-channel type MOS transistors formed in the first and second P-well areas respectively and the P-channel type MOS transistor formed in the N-well area can be made uniform. As a result, there is an effect that it is possible to employ an optimal layout with further shorter wiring.
- Further, as the extension direction of the bit lines is parallel with each boundary line between the first and second P-well areas and the N-well area, it is possible to apply a layout with the minimized length of the bit lines when it is considered that the length of the word lines is also decreased.
- Further, as the extension direction of the word lines is perpendicular to each boundary line between the first and second P-well areas and the N-well area, it is possible to apply a layout with the minimized length of the word lines when it is considered that the length of the bit lines should preferentially be decreased.
- Further, the respective gate areas of a first P-channel type MOS transistor, and the first, fourth and sixth N-channel type MOS transistors are formed so as to position on the same straight line. Therefore, the wiring to connect between these gates is formed in a straight-line shape. Further, the respective gate areas of a second P-channel type MOS transistor, and the second, third and fifth N-channel type MOS transistors are formed so as to also position on the same straight line. Therefore, the wiring to connect between these gates is formed in a straight-line shape. As a result, there is an effect that it is possible to obtain shorter wiring.
- Further, as the drain of the second N-channel type MOS transistor and the source of the fourth N-channel type MOS transistor are positioned on the same straight line, it is possible to reduce the space between these second and fourth N-channel type MOS transistors. Further, as the drain of the fifth N-channel type MOS transistor and the source of the sixth N-channel type MOS transistor are positioned on the same straight line, it is possible to reduce the space between these fifth and sixth N-channel type MOS transistors. As a result, there is an effect that it is possible to improve the scale of integration of memory cells.
- Further, respective ones of the semiconductor terminals are formed in a common n+ diffusion area for the first and third N-channel type MOS transistors and for the fifth and sixth N-channel type MOS transistors. Therefore, it is possible to reduce an entire n+ diffusion area. As a result, there is an effect that it is possible to reduce parasitic capacitance due to the n+ diffusion area.
- Further, the second P-channel type MOS transistor, and the second and fifth N-channel type MOS transistors have their respective gate areas connected by a straight line-shaped common polysilicon wiring. Therefore, it is possible to reduce the space between these MOS transistors. As a result, there is an effect that it is possible to improve the scale of integration of the memory cells.
- Further, the extension lines of the bit lines, a power source line, and a GND line respectively are perpendicular to each word line. Therefore, it is possible to minimize the length of these lines. As a result, there is an effect that it is possible to achieve a high-speed accessing.
- Further, the respective gate areas of the first P-channel type MOS transistor, and the first, fourth, sixth and seventh N-channel type MOS transistors are formed so as to position on the same straight line. Therefore, it is possible to form the wiring to connect between these gates in a straight-line shape. Further, the respective gate areas of the second P-channel type MOS transistor, and the second, third, fifth and eighth N-channel type MOS transistors are formed so as to also position on the same straight line. Therefore, it is possible to form the wiring to connect between these gates in a straight-line shape. As a result, there is an effect that it is possible to obtain shorter wiring.
- Further, as the drain of the second N-channel type MOS transistor and the source of the fourth N-channel type MOS transistor are positioned on the same straight line, it is possible to reduce the space between these second and fourth N-channel type MOS transistors. As the drain of the fifth N-channel type MOS transistor and the source of the sixth N-channel type MOS transistor are also positioned on the same straight line, it is possible to reduce the space between these fifth and sixth N-channel type MOS transistors. Further, as the drain of the seventh N-channel type MOS transistor and the source of the eighth N-channel type MOS transistor are positioned on the same straight line as well, it is possible to reduce the space between these seventh and eighth N-channel type MOS transistors. As a result, there is an effect that it is possible to improve the scale of integration of the memory cells.
- Further, respective ones of the semiconductor terminals are formed in a common n+ diffusion area for the first and third N-channel type MOS transistors, for the fifth and sixth N-channel type MOS transistors, and for the seventh and eighth N-channel type MOS transistors. Therefore, it is possible to reduce an entire n+ diffusion area. As a result, there is an effect that it is possible to reduce parasitic capacitance due to the n+ diffusion area.
- Further, the second P-channel type MOS transistor, and the second and fifth N-channel type MOS transistors have their respective gate areas connected by a straight line-shaped common polysilicon wiring. Further, the first P-channel type MOS transistor, and the first and seventh N-channel type MOS transistors have their respective gate areas connected by a straight line-shaped common polysilicon wiring. Therefore, it is possible to reduce the space between these MOS transistors. As a result, there is an effect that it is possible to improve the scale of integration of the memory cells.
- Although the invention has been described with respect to a specific embodiment for a complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modifications and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.
Claims (27)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/056,111 US6535453B2 (en) | 2000-05-16 | 2002-01-28 | Semiconductor memory device |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000143861 | 2000-05-16 | ||
JP2000-143861 | 2000-05-16 | ||
JP2001-003500 | 2001-01-11 | ||
JP2001003500A JP4885365B2 (en) | 2000-05-16 | 2001-01-11 | Semiconductor device |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/056,111 Continuation US6535453B2 (en) | 2000-05-16 | 2002-01-28 | Semiconductor memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010043487A1 true US20010043487A1 (en) | 2001-11-22 |
US6347062B2 US6347062B2 (en) | 2002-02-12 |
Family
ID=26591985
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/824,008 Expired - Lifetime US6347062B2 (en) | 2000-05-16 | 2001-04-03 | Semiconductor memory device |
US10/056,111 Expired - Lifetime US6535453B2 (en) | 2000-05-16 | 2002-01-28 | Semiconductor memory device |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/056,111 Expired - Lifetime US6535453B2 (en) | 2000-05-16 | 2002-01-28 | Semiconductor memory device |
Country Status (4)
Country | Link |
---|---|
US (2) | US6347062B2 (en) |
JP (1) | JP4885365B2 (en) |
KR (1) | KR100419687B1 (en) |
DE (1) | DE10123514B4 (en) |
Cited By (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050124095A1 (en) * | 2003-12-05 | 2005-06-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Sram device having high aspect ratio cell boundary |
US20070007603A1 (en) * | 2005-07-07 | 2007-01-11 | Takayuki Yamada | Semiconductor device |
US7405994B2 (en) | 2005-07-29 | 2008-07-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dual port cell structure |
WO2009155474A2 (en) * | 2008-06-19 | 2009-12-23 | Texas Instruments Incorporated | Memory cell employing reduced voltage |
US20100254210A1 (en) * | 2006-11-29 | 2010-10-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multiple-Port SRAM Device |
US20110157965A1 (en) * | 2009-12-24 | 2011-06-30 | Renesas Electronics Corporation | Semiconductor device |
US20110157963A1 (en) * | 2009-12-30 | 2011-06-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Sram word-line coupling noise restriction |
US8406028B1 (en) * | 2011-10-31 | 2013-03-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Word line layout for semiconductor memory |
DE102013102427A1 (en) * | 2013-01-02 | 2014-07-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dual-port SRAM connection structure |
US20160064067A1 (en) * | 2014-08-26 | 2016-03-03 | Qualcomm Incorporated | Three-port bit cell having increased width |
WO2016089574A1 (en) * | 2014-12-03 | 2016-06-09 | Qualcomm Incorporated | Three port sram bit cells with first and second read wordline and write wordline on different metal layers and associated landing pads split across boundary edges of each sram bit cell |
WO2016089587A1 (en) * | 2014-12-03 | 2016-06-09 | Qualcomm Incorporated | Static random access memory (sram) bit cells with wordlines on separate metal layers for increased performance, and related methods |
CN105845172A (en) * | 2015-02-04 | 2016-08-10 | 台湾积体电路制造股份有限公司 | Multiple-port sram device |
WO2016130194A1 (en) * | 2015-02-12 | 2016-08-18 | Qualcomm Incorporated | Metal layers for a three-port bit cell |
US9515076B2 (en) | 2013-08-06 | 2016-12-06 | Renesas Electronics Corporation | Semiconductor integrated circuit device |
TWI602192B (en) * | 2011-04-12 | 2017-10-11 | 瑞薩電子股份有限公司 | Semiconductor integrated circuit device |
TWI607550B (en) * | 2011-07-26 | 2017-12-01 | 瑞薩電子股份有限公司 | Semiconductor device |
US10032781B2 (en) | 2011-07-29 | 2018-07-24 | Renesas Electronics Corporation | Static random access memory device with halo regions having different impurity concentrations |
US10211206B1 (en) * | 2017-11-01 | 2019-02-19 | Globalfoundries Inc. | Two-port vertical SRAM circuit structure and method for producing the same |
CN111129005A (en) * | 2019-12-25 | 2020-05-08 | 上海华力集成电路制造有限公司 | Layout structure of double-port static random access memory unit |
US10971502B2 (en) * | 2019-02-12 | 2021-04-06 | United Microelectronics Corp. | SRAM structure |
US11502006B2 (en) * | 2017-12-07 | 2022-11-15 | Micron Technology, Inc. | Apparatuses having an interconnect extending from an upper conductive structure, through a hole in another conductive structure, and to an underlying structure |
Families Citing this family (78)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA2299991A1 (en) * | 2000-03-03 | 2001-09-03 | Mosaid Technologies Incorporated | A memory cell for embedded memories |
TW522546B (en) * | 2000-12-06 | 2003-03-01 | Mitsubishi Electric Corp | Semiconductor memory |
JP3637299B2 (en) * | 2001-10-05 | 2005-04-13 | 松下電器産業株式会社 | Semiconductor memory device |
JP2003133529A (en) * | 2001-10-24 | 2003-05-09 | Sony Corp | Information memory and manufacturing method therefor |
JP2003152111A (en) * | 2001-11-13 | 2003-05-23 | Mitsubishi Electric Corp | Semiconductor storage device |
JP2003218238A (en) * | 2001-11-14 | 2003-07-31 | Mitsubishi Electric Corp | Semiconductor memory device |
US6737685B2 (en) * | 2002-01-11 | 2004-05-18 | International Business Machines Corporation | Compact SRAM cell layout for implementing one-port or two-port operation |
JP4073691B2 (en) * | 2002-03-19 | 2008-04-09 | 株式会社ルネサステクノロジ | Semiconductor memory device |
JP4278338B2 (en) * | 2002-04-01 | 2009-06-10 | 株式会社ルネサステクノロジ | Semiconductor memory device |
KR100468780B1 (en) * | 2002-12-18 | 2005-01-29 | 삼성전자주식회사 | Double port semiconductor memory device |
JP4418153B2 (en) * | 2002-12-27 | 2010-02-17 | 株式会社ルネサステクノロジ | Semiconductor device |
KR100539229B1 (en) | 2003-01-30 | 2005-12-27 | 삼성전자주식회사 | Semiconductor memory device including a dual port |
JP4416428B2 (en) | 2003-04-30 | 2010-02-17 | 株式会社ルネサステクノロジ | Semiconductor memory device |
JP2005333084A (en) * | 2004-05-21 | 2005-12-02 | Nec Electronics Corp | Semiconductor memory |
WO2006016403A1 (en) * | 2004-08-10 | 2006-02-16 | Fujitsu Limited | Semiconductor storage device |
US7365432B2 (en) * | 2004-08-23 | 2008-04-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory cell structure |
JP2006127737A (en) * | 2004-09-30 | 2006-05-18 | Nscore:Kk | Nonvolatile memory circuit |
WO2006120739A1 (en) | 2005-05-11 | 2006-11-16 | Fujitsu Limited | Semiconductor device and production method therefor |
JP4578329B2 (en) | 2005-06-03 | 2010-11-10 | ルネサスエレクトロニクス株式会社 | Semiconductor memory device |
US7763534B2 (en) | 2007-10-26 | 2010-07-27 | Tela Innovations, Inc. | Methods, structures and designs for self-aligning local interconnects used in integrated circuits |
US8839175B2 (en) | 2006-03-09 | 2014-09-16 | Tela Innovations, Inc. | Scalable meta-data objects |
US8653857B2 (en) * | 2006-03-09 | 2014-02-18 | Tela Innovations, Inc. | Circuitry and layouts for XOR and XNOR logic |
US9035359B2 (en) | 2006-03-09 | 2015-05-19 | Tela Innovations, Inc. | Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods |
US9563733B2 (en) | 2009-05-06 | 2017-02-07 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
US9230910B2 (en) | 2006-03-09 | 2016-01-05 | Tela Innovations, Inc. | Oversized contacts and vias in layout defined by linearly constrained topology |
US9009641B2 (en) | 2006-03-09 | 2015-04-14 | Tela Innovations, Inc. | Circuits with linear finfet structures |
US8541879B2 (en) | 2007-12-13 | 2013-09-24 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
US7917879B2 (en) | 2007-08-02 | 2011-03-29 | Tela Innovations, Inc. | Semiconductor device with dynamic array section |
US7446352B2 (en) | 2006-03-09 | 2008-11-04 | Tela Innovations, Inc. | Dynamic array architecture |
US8448102B2 (en) | 2006-03-09 | 2013-05-21 | Tela Innovations, Inc. | Optimizing layout of irregular structures in regular layout context |
US8658542B2 (en) | 2006-03-09 | 2014-02-25 | Tela Innovations, Inc. | Coarse grid design methods and structures |
US7956421B2 (en) | 2008-03-13 | 2011-06-07 | Tela Innovations, Inc. | Cross-coupled transistor layouts in restricted gate level layout architecture |
JP5061490B2 (en) * | 2006-04-06 | 2012-10-31 | ソニー株式会社 | Semiconductor device and manufacturing method thereof |
US7898894B2 (en) * | 2006-04-12 | 2011-03-01 | International Business Machines Corporation | Static random access memory (SRAM) cells |
US7269056B1 (en) * | 2006-04-27 | 2007-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Power grid design for split-word line style memory cell |
US7606057B2 (en) * | 2006-05-31 | 2009-10-20 | Arm Limited | Metal line layout in a memory cell |
JP2008027493A (en) * | 2006-07-19 | 2008-02-07 | Toshiba Corp | Semiconductor memory device |
JP2008130670A (en) * | 2006-11-17 | 2008-06-05 | Seiko Epson Corp | Semiconductor device, logic circuit, and electronic instrument |
US7839697B2 (en) | 2006-12-21 | 2010-11-23 | Panasonic Corporation | Semiconductor memory device |
JP2008159669A (en) * | 2006-12-21 | 2008-07-10 | Matsushita Electric Ind Co Ltd | Semiconductor memory |
US7738282B2 (en) * | 2007-02-15 | 2010-06-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cell structure of dual port SRAM |
US8667443B2 (en) * | 2007-03-05 | 2014-03-04 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
JP2009016809A (en) * | 2007-06-07 | 2009-01-22 | Toshiba Corp | Semiconductor memory device |
KR100849794B1 (en) * | 2007-07-04 | 2008-07-31 | 주식회사 하이닉스반도체 | Semiconductor memory device with ferroelectric device |
KR100865633B1 (en) * | 2007-07-19 | 2008-10-27 | 주식회사 동부하이텍 | Dual port sram |
US8453094B2 (en) | 2008-01-31 | 2013-05-28 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
US7939443B2 (en) | 2008-03-27 | 2011-05-10 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
JP2009238332A (en) | 2008-03-27 | 2009-10-15 | Renesas Technology Corp | Semiconductor memory device |
JP5231924B2 (en) * | 2008-10-03 | 2013-07-10 | 株式会社東芝 | Semiconductor memory device |
GB2460049A (en) * | 2008-05-13 | 2009-11-18 | Silicon Basis Ltd | Reading from an SRAM cell using a read bit line |
MY152456A (en) | 2008-07-16 | 2014-09-30 | Tela Innovations Inc | Methods for cell phasing and placement in dynamic array architecture and implementation of the same |
US9122832B2 (en) | 2008-08-01 | 2015-09-01 | Tela Innovations, Inc. | Methods for controlling microloading variation in semiconductor wafer layout and fabrication |
US8009463B2 (en) * | 2009-07-31 | 2011-08-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Cell structure for dual port SRAM |
US8189368B2 (en) * | 2009-07-31 | 2012-05-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Cell structure for dual port SRAM |
US8661392B2 (en) | 2009-10-13 | 2014-02-25 | Tela Innovations, Inc. | Methods for cell boundary encroachment and layouts implementing the Same |
WO2011077664A1 (en) | 2009-12-25 | 2011-06-30 | パナソニック株式会社 | Semiconductor device |
US9362290B2 (en) | 2010-02-08 | 2016-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory cell layout |
US8675397B2 (en) * | 2010-06-25 | 2014-03-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cell structure for dual-port SRAM |
US8315084B2 (en) * | 2010-03-10 | 2012-11-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fully balanced dual-port memory cell |
US8942030B2 (en) * | 2010-06-25 | 2015-01-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for SRAM cell circuit |
CN102243888A (en) * | 2010-05-13 | 2011-11-16 | 黄效华 | Storage cell with balance load of multi-port register |
JP5433788B2 (en) * | 2010-08-05 | 2014-03-05 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
US9159627B2 (en) | 2010-11-12 | 2015-10-13 | Tela Innovations, Inc. | Methods for linewidth modification and apparatus implementing the same |
US8576655B2 (en) | 2011-06-21 | 2013-11-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor memories |
US9099199B2 (en) * | 2012-03-15 | 2015-08-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory cell and memory array |
US9036404B2 (en) * | 2012-03-30 | 2015-05-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for SRAM cell structure |
JP6151504B2 (en) * | 2012-10-17 | 2017-06-21 | ルネサスエレクトロニクス株式会社 | Semiconductor memory device |
JP6501688B2 (en) * | 2015-09-29 | 2019-04-17 | ルネサスエレクトロニクス株式会社 | Semiconductor memory device and test method thereof |
TWI726869B (en) | 2016-02-24 | 2021-05-11 | 聯華電子股份有限公司 | Layout structure for sram and manufacturing methods thereof |
JP2016146504A (en) * | 2016-04-06 | 2016-08-12 | ルネサスエレクトロニクス株式会社 | Semiconductor device and semiconductor chip |
TWI681542B (en) * | 2016-05-04 | 2020-01-01 | 聯華電子股份有限公司 | Layout pattern for sram |
US10074605B2 (en) | 2016-06-30 | 2018-09-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory cell and array structure having a plurality of bit lines |
US10461086B2 (en) | 2016-10-31 | 2019-10-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory cell structure |
US9935112B1 (en) * | 2017-05-19 | 2018-04-03 | Globalfoundries Inc. | SRAM cell having dual pass gate transistors and method of making the same |
JP6383073B2 (en) * | 2017-09-27 | 2018-08-29 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
JP6586204B2 (en) * | 2018-08-02 | 2019-10-02 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
JP7370730B2 (en) * | 2019-05-14 | 2023-10-30 | ルネサスエレクトロニクス株式会社 | semiconductor storage device |
US11955169B2 (en) * | 2021-03-23 | 2024-04-09 | Qualcomm Incorporated | High-speed multi-port memory supporting collision |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5325338A (en) * | 1991-09-04 | 1994-06-28 | Advanced Micro Devices, Inc. | Dual port memory, such as used in color lookup tables for video systems |
US5338963A (en) | 1993-04-05 | 1994-08-16 | International Business Machines Corporation | Soft error immune CMOS static RAM cell |
JP3780003B2 (en) * | 1993-06-15 | 2006-05-31 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit device |
JP3771283B2 (en) | 1993-09-29 | 2006-04-26 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit device |
JPH097373A (en) * | 1995-06-20 | 1997-01-10 | Oki Electric Ind Co Ltd | Semiconductor memory device |
US5561638A (en) * | 1995-11-30 | 1996-10-01 | Northern Telecom Limited | Multi-port SRAM core array |
JP3824343B2 (en) | 1996-03-29 | 2006-09-20 | 富士通株式会社 | Semiconductor device |
US5742557A (en) * | 1996-06-20 | 1998-04-21 | Northern Telecom Limited | Multi-port random access memory |
KR100230426B1 (en) * | 1996-06-29 | 1999-11-15 | 윤종용 | Static random access memory device with improved integrated ratio |
JP3523762B2 (en) | 1996-12-19 | 2004-04-26 | 株式会社東芝 | Semiconductor storage device |
JP3036588B2 (en) * | 1997-02-03 | 2000-04-24 | 日本電気株式会社 | Semiconductor storage device |
KR100289386B1 (en) * | 1997-12-27 | 2001-06-01 | 김영환 | Multi-port sram |
KR100502672B1 (en) * | 1998-04-21 | 2005-10-05 | 주식회사 하이닉스반도체 | Full CMOS SRAM Cells |
JP2000031300A (en) * | 1998-07-09 | 2000-01-28 | Fujitsu Ltd | Static semiconductor memory device |
JP3852729B2 (en) * | 1998-10-27 | 2006-12-06 | 富士通株式会社 | Semiconductor memory device |
-
2001
- 2001-01-11 JP JP2001003500A patent/JP4885365B2/en not_active Expired - Lifetime
- 2001-04-03 US US09/824,008 patent/US6347062B2/en not_active Expired - Lifetime
- 2001-05-11 KR KR10-2001-0025724A patent/KR100419687B1/en active IP Right Grant
- 2001-05-15 DE DE10123514A patent/DE10123514B4/en not_active Expired - Lifetime
-
2002
- 2002-01-28 US US10/056,111 patent/US6535453B2/en not_active Expired - Lifetime
Cited By (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7233032B2 (en) * | 2003-12-05 | 2007-06-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | SRAM device having high aspect ratio cell boundary |
US20050124095A1 (en) * | 2003-12-05 | 2005-06-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Sram device having high aspect ratio cell boundary |
US20070007603A1 (en) * | 2005-07-07 | 2007-01-11 | Takayuki Yamada | Semiconductor device |
US7554163B2 (en) * | 2005-07-07 | 2009-06-30 | Panasonic Corporation | Semiconductor device |
US7405994B2 (en) | 2005-07-29 | 2008-07-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dual port cell structure |
US9905290B2 (en) * | 2006-11-29 | 2018-02-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiple-port SRAM device |
US20160358646A1 (en) * | 2006-11-29 | 2016-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiple-Port SRAM Device |
US8934287B2 (en) * | 2006-11-29 | 2015-01-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multiple-port SRAM device |
US20100254210A1 (en) * | 2006-11-29 | 2010-10-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multiple-Port SRAM Device |
US20140063919A1 (en) * | 2006-11-29 | 2014-03-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multiple-port sram device |
US8605491B2 (en) * | 2006-11-29 | 2013-12-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multiple-port SRAM device |
WO2009155474A2 (en) * | 2008-06-19 | 2009-12-23 | Texas Instruments Incorporated | Memory cell employing reduced voltage |
CN102047339A (en) * | 2008-06-19 | 2011-05-04 | 德克萨斯仪器股份有限公司 | Memory cell employing reduced voltage |
US7864600B2 (en) | 2008-06-19 | 2011-01-04 | Texas Instruments Incorporated | Memory cell employing reduced voltage |
WO2009155474A3 (en) * | 2008-06-19 | 2010-03-25 | Texas Instruments Incorporated | Memory cell employing reduced voltage |
US20090316500A1 (en) * | 2008-06-19 | 2009-12-24 | Mikan Jr Donald George | Memory Cell Employing Reduced Voltage |
US8363456B2 (en) | 2009-12-24 | 2013-01-29 | Renesas Electronics Corporation | Semiconductor device |
US20110157965A1 (en) * | 2009-12-24 | 2011-06-30 | Renesas Electronics Corporation | Semiconductor device |
US20110157963A1 (en) * | 2009-12-30 | 2011-06-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Sram word-line coupling noise restriction |
US8218354B2 (en) * | 2009-12-30 | 2012-07-10 | Taiwan Semicondcutor Manufacturing Co., Ltd. | SRAM word-line coupling noise restriction |
TWI602192B (en) * | 2011-04-12 | 2017-10-11 | 瑞薩電子股份有限公司 | Semiconductor integrated circuit device |
TWI607550B (en) * | 2011-07-26 | 2017-12-01 | 瑞薩電子股份有限公司 | Semiconductor device |
US10510761B2 (en) | 2011-07-29 | 2019-12-17 | Renesas Electronics Corporation | Static random access memory device with halo regions having different impurity concentrations |
US10217751B2 (en) | 2011-07-29 | 2019-02-26 | Renesas Electronics Corporation | Static random access memory device with halo regions having different impurity concentrations |
US10032781B2 (en) | 2011-07-29 | 2018-07-24 | Renesas Electronics Corporation | Static random access memory device with halo regions having different impurity concentrations |
US8406028B1 (en) * | 2011-10-31 | 2013-03-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Word line layout for semiconductor memory |
DE102013102427A1 (en) * | 2013-01-02 | 2014-07-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dual-port SRAM connection structure |
DE102013102427B4 (en) * | 2013-01-02 | 2017-08-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dual-port SRAM connection structure |
US9515076B2 (en) | 2013-08-06 | 2016-12-06 | Renesas Electronics Corporation | Semiconductor integrated circuit device |
US9711512B2 (en) | 2013-08-06 | 2017-07-18 | Renesas Electronics Corporation | Semiconductor integrated circuit device |
US9972629B2 (en) | 2013-08-06 | 2018-05-15 | Renesas Electronics Corporation | Semiconductor integrated circuit device |
US20160064067A1 (en) * | 2014-08-26 | 2016-03-03 | Qualcomm Incorporated | Three-port bit cell having increased width |
US9536596B2 (en) * | 2014-08-26 | 2017-01-03 | Qualcomm Incorporated | Three-port bit cell having increased width |
WO2016032645A1 (en) * | 2014-08-26 | 2016-03-03 | Qualcomm Incorporated | Three-port bit cell having increased width |
WO2016089587A1 (en) * | 2014-12-03 | 2016-06-09 | Qualcomm Incorporated | Static random access memory (sram) bit cells with wordlines on separate metal layers for increased performance, and related methods |
CN107004439A (en) * | 2014-12-03 | 2017-08-01 | 高通股份有限公司 | With different metal layer on the first and second readout word lines and write word line and across each SRAM bit cell boundary edge split associated landing pads three port SRAM bit locations |
WO2016089574A1 (en) * | 2014-12-03 | 2016-06-09 | Qualcomm Incorporated | Three port sram bit cells with first and second read wordline and write wordline on different metal layers and associated landing pads split across boundary edges of each sram bit cell |
CN105845172A (en) * | 2015-02-04 | 2016-08-10 | 台湾积体电路制造股份有限公司 | Multiple-port sram device |
US20190035796A1 (en) * | 2015-02-12 | 2019-01-31 | Qualcomm Incorporated | Metal layers for a three-port bit cell |
KR102504733B1 (en) * | 2015-02-12 | 2023-02-27 | 퀄컴 인코포레이티드 | Metal Layers for 3-Port Bit Cell |
CN107210295A (en) * | 2015-02-12 | 2017-09-26 | 高通股份有限公司 | Metal level for three port bit locations |
KR20170116021A (en) * | 2015-02-12 | 2017-10-18 | 퀄컴 인코포레이티드 | Metal layers for 3-port bit cells |
US10141317B2 (en) | 2015-02-12 | 2018-11-27 | Qualcomm Incorporated | Metal layers for a three-port bit cell |
US9524972B2 (en) | 2015-02-12 | 2016-12-20 | Qualcomm Incorporated | Metal layers for a three-port bit cell |
WO2016130194A1 (en) * | 2015-02-12 | 2016-08-18 | Qualcomm Incorporated | Metal layers for a three-port bit cell |
US10211206B1 (en) * | 2017-11-01 | 2019-02-19 | Globalfoundries Inc. | Two-port vertical SRAM circuit structure and method for producing the same |
US11502006B2 (en) * | 2017-12-07 | 2022-11-15 | Micron Technology, Inc. | Apparatuses having an interconnect extending from an upper conductive structure, through a hole in another conductive structure, and to an underlying structure |
US10971502B2 (en) * | 2019-02-12 | 2021-04-06 | United Microelectronics Corp. | SRAM structure |
CN111129005A (en) * | 2019-12-25 | 2020-05-08 | 上海华力集成电路制造有限公司 | Layout structure of double-port static random access memory unit |
US11133322B2 (en) * | 2019-12-25 | 2021-09-28 | Shanghai Huali Integrated Circuit Corporation | Dual-port static random access memory cell layout structure |
Also Published As
Publication number | Publication date |
---|---|
JP4885365B2 (en) | 2012-02-29 |
US20020064080A1 (en) | 2002-05-30 |
US6535453B2 (en) | 2003-03-18 |
US6347062B2 (en) | 2002-02-12 |
DE10123514B4 (en) | 2005-07-28 |
KR100419687B1 (en) | 2004-02-21 |
JP2002043441A (en) | 2002-02-08 |
DE10123514A1 (en) | 2001-11-22 |
KR20010106233A (en) | 2001-11-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6347062B2 (en) | Semiconductor memory device | |
US8238142B2 (en) | Semiconductor memory device | |
US6822300B2 (en) | Semiconductor memory device | |
USRE41963E1 (en) | Semiconductor memory device | |
JP5596335B2 (en) | Semiconductor device | |
US6606276B2 (en) | SRAM device using MIS transistors | |
US6590802B2 (en) | Semiconductor storage apparatus | |
US6885609B2 (en) | Semiconductor memory device supporting two data ports | |
US20220108992A1 (en) | Semiconductor storage device | |
US20030025217A1 (en) | Full CMOS SRAM cell | |
US6469356B2 (en) | Semiconductor memory device having different distances between gate electrode layers | |
US6538338B2 (en) | Static RAM semiconductor memory device having reduced memory | |
JP6096271B2 (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MITSUBISHI DENKI KABUSHIKI KAISHA, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NII, KOJI;MIYANISHI, ATSUSHI;REEL/FRAME:011668/0988 Effective date: 20010312 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MITSUBISHI DENKI KABUSHIKI KAISHA;REEL/FRAME:025980/0219 Effective date: 20110307 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN Free format text: CHANGE OF ADDRESS;ASSIGNOR:RENESAS ELECTRONICS CORPORATION;REEL/FRAME:044928/0001 Effective date: 20150806 |