JP6586204B2 - Semiconductor device - Google Patents

Description

    The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device having an SRAM.

  SRAM (Static Random Access Memory) is a kind of semiconductor memory, and stores data using flip-flops. That is, in the SRAM, data (“1” or “0”) is stored in two cross-connected inverters formed by four transistors. In addition, since two transistors are required for read and write access, in a typical SRAM, a memory cell is composed of six transistors.

  For example, the following Patent Document 1 (Japanese Patent Laid-Open No. 2001-28401) discloses a semiconductor memory device having a static RAM memory cell composed of six transistors (FIG. 1).

  In Patent Document 2 (Japanese Patent Laid-Open No. 2002-237539), an NMOS transistor (N1, N4) is formed in one P well region (PW0), and an NMOS transistor (N2, N3) is formed in an N well region. An SRAM memory cell formed in the other P-well region (PW1) sandwiching (NW) is disclosed (see FIG. 32), thereby improving the soft error resistance.

  In the following Patent Document 3 (Japanese Patent Laid-Open No. 7-7089), two divided driver NMOSs (transistor regions N1 ′, N1 ″, N2 ′, and N2 ″) are arranged on separate P-wells. An SRAM memory cell has been disclosed (see FIG. 5), thereby taking measures against soft errors. In this SRAM cell, the gate direction of the word line access transistors (NA1) and (NB1) is orthogonal to the gate direction of the driver NMOS (transistor regions N1 ′, N1 ″, N2 ′, and N2 ″). It has become a direction.

  Further, in the following Patent Document 4 (Japanese Patent Laid-Open No. 2002-43441), an N-channel MOS having a gate electrode as the main axis of the polysilicon wiring layer (PL11) formed in the first P-well region (PW1). An SRAM memory cell having an N-channel MOS transistor (N1 ′) having a gate electrode as a folding axis of the transistor (N1) and the polysilicon wiring layer (PL11) is disclosed (FIG. 1, FIG. 2, paragraph [0062] reference).

  Further, in the following Patent Document 5 (Japanese Patent Laid-Open No. 2000-36543), in the layout of the SRAM memory cell, two word lines (21a, 21b) are orthogonal to each other near both ends of the p-type active region (13). The common gate lines (22a, 22b) are connected to the p-type active region (13) between the word lines (21a, 21b). An SRAM memory cell is disclosed that is orthogonal to both of the n-type active regions (14) and wired in parallel to each other so as to be equidistant with the word lines (21a, 21b) (see FIG. 4). In addition, the code | symbol, figure number, etc. which are described in each literature are shown in parentheses.

JP 2001-28401 A JP 2002-237539 A JP 7-7089 A JP 2002-43441 A JP 2000-36543 A

  For example, as described in Patent Document 1 (FIG. 1 and the like), an SRAM memory cell has a complicated pattern configuration. With the recent miniaturization of semiconductor devices, for example, elements such as variations in gate width. There are problems such as an increase in variation in characteristics and difficulty in simulating memory characteristics.

  The variation in the element characteristics is caused by the shape of the active region and the shape of the gate electrode, as will be described in detail later.

  Therefore, it is desired to improve the controllability of the element characteristics and facilitate the simulation by optimizing the shape of the active region and the shape of the gate electrode.

  An object of the present invention is to provide a semiconductor device having good characteristics. In particular, it is an object to provide a cell layout capable of improving the characteristics of a semiconductor device having SRAM memory cells.

  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  Among the inventions disclosed in this application, a semiconductor device described in a typical embodiment includes memory cells having the following (a1) to (a8).

  (A1) is a first conductivity type first MIS transistor connected between the first potential and the first node.

  (A2) is a second conductivity type first MIS transistor connected between the first node and a second potential different from the first potential.

  (A3) is a second conductivity type second MIS transistor connected in parallel with the second conductivity type first MIS transistor between the first node and the second potential.

  (A4) is a first conductivity type second MIS transistor connected between the first potential and the second node.

  (A5) is a second conductivity type third MIS transistor connected between the second node and the second potential.

  (A6) is a second conductivity type fourth MIS transistor connected in parallel with the second conductivity type third MIS transistor between the second node and the second potential.

  (A7) is a second conductivity type fifth MIS transistor connected between the first node and the first bit line.

  (A8) is a second conductivity type sixth MIS transistor connected between the second node and the second bit line.

  Furthermore, it has the following active regions (b1) to (b4).

  (B1) is an integrated first active region in which the second conductivity type first MIS transistor and the second conductivity type fifth MIS transistor are arranged.

  (B2) is a second active region in which the patterns of the first active region and the active region are separated and the second conductivity type second MIS transistor is disposed.

  (B3) is an integral third active region in which the second conductivity type third MIS transistor and the second conductivity type sixth MIS transistor are arranged.

  (B4) is a fourth active region in which the patterns of the third active region and the active region are separated and the second conductivity type fourth transistor is disposed.

  The first to fourth active regions are arranged so as to be separated from each other in the first direction.

  A first gate line is disposed on the first active region so as to extend in the first direction.

  A second gate wiring is arranged on the first active region and the second active region so as to extend in the first direction.

  A third gate line is arranged on the third active region so as to extend in the first direction.

  A fourth gate wiring is arranged on the third active region and the fourth active region so as to extend in the first direction.

  Among the inventions disclosed in the present application, a semiconductor device shown in another representative embodiment includes the above (a1) to (a8). Further, the semiconductor device has active regions (b1) and (b2). (B1) is an integrated first active region in which the first transistor, the fourth transistor, and the fifth transistor are disposed. (B2) is an integrated second active region in which the third transistor, the second transistor, and the sixth transistor are arranged. With respect to the active region, (c) the first and second active regions are arranged in the first direction. Further, (d1) a first gate line is disposed on the first active region so as to extend in the first direction, and (d2) a second gate line is disposed on the first active region and the second active region. Are arranged so as to extend in the first direction. (D3) a third gate wiring is disposed on the first active region and the second active region so as to extend in the first direction; and (d4) a fourth gate wiring is disposed on the second active region. Are arranged so as to extend in the first direction.

  Among the inventions disclosed in the present application, a semiconductor device shown in another representative embodiment includes the above (a1) to (a8). Further, the semiconductor device has active regions (b1) and (b2). (B1) is an integrated first active region in which the first transistor, the fourth transistor, and the fifth transistor are disposed. (B2) is an integrated second active region in which the third transistor, the second transistor, and the sixth transistor are arranged. Regarding the active region, (c) the first active region and the second active region are arranged so as to be aligned in the first direction. Further, (d1) a first gate line is disposed on the first active region so as to extend in the first direction, and (d2) a second gate line is disposed on the first active region and the second active region. Are arranged so as to extend in the first direction. (D3) a third gate wiring is disposed on the first active region and the second active region so as to extend in the first direction; and (d4) a fourth gate wiring is disposed on the first active region. Are arranged so as to extend in the first direction.

  Among the inventions disclosed in the present application, according to the semiconductor device described in the following representative embodiment, the characteristics can be improved.

3 is an equivalent circuit diagram showing the SRAM memory cell according to the first embodiment; FIG. 4 is a plan view showing the configuration of the SRAM memory cell according to the first embodiment; FIG. 4 is a plan view showing the configuration of the SRAM memory cell according to the first embodiment; FIG. 4 is a plan view showing the configuration of the SRAM memory cell according to the first embodiment; FIG. 4 is a circuit diagram in which transistors are arranged corresponding to the layout of the SRAM memory cell according to the first embodiment; FIG. 3 is a cross-sectional view showing the configuration of the SRAM memory cell according to the first embodiment; FIG. 3 is a cross-sectional view showing the configuration of the SRAM memory cell according to the first embodiment; FIG. 3 is a cross-sectional view showing the configuration of the SRAM memory cell according to the first embodiment; FIG. 3 is a cross-sectional view showing the configuration of the SRAM memory cell according to the first embodiment; FIG. 3 is a cross-sectional view showing the configuration of the SRAM memory cell according to the first embodiment; FIG. 3 is a cross-sectional view showing the configuration of the SRAM memory cell according to the first embodiment; FIG. FIG. 3 is a plan view showing a concept of the SRAM memory cell array according to the first embodiment; 3 is a plan view showing the configuration of the SRAM memory cell array according to the first embodiment; FIG. 3 is a plan view showing the configuration of the SRAM memory cell array according to the first embodiment; FIG. FIG. 3 is a plan view conceptually showing the position of a tap cell region in the SRAM memory cell array according to the first embodiment; 3 is a plan view showing the configuration of the SRAM tap cell (F ′) according to the first embodiment; FIG. 3 is a plan view showing the configuration of the SRAM tap cell (F ′) according to the first embodiment; FIG. FIG. 3 is a plan view showing the concept of the SRAM memory cell and tap cell formation region in the first embodiment; 3 is a plan view showing the configuration of the SRAM memory cell and tap cell formation region in the first embodiment; FIG. 3 is a plan view showing the configuration of the SRAM memory cell and tap cell formation region in the first embodiment; FIG. 7 is a plan view showing a configuration of an SRAM memory cell according to a second embodiment; FIG. 7 is a plan view showing a configuration of an SRAM memory cell according to a second embodiment; FIG. FIG. 12 is a plan view showing the configuration of the SRAM tap cell according to the third embodiment. FIG. 12 is a plan view showing the configuration of the SRAM tap cell according to the third embodiment. FIG. 10 is a circuit diagram showing an SRAM memory cell according to a third embodiment; FIG. 10 is a plan view showing a configuration of an SRAM memory cell according to a fourth embodiment. FIG. 10 is a plan view showing a configuration of an SRAM memory cell according to a fourth embodiment. FIG. 10 is a plan view showing a configuration of an SRAM memory cell according to a fourth embodiment. FIG. 16 is a circuit diagram in which transistors are arranged corresponding to the layout of the SRAM memory cell according to the fourth embodiment. FIG. 16 is a plan view showing the configuration of the SRAM memory cell according to the fifth embodiment; FIG. 16 is a plan view showing the configuration of the SRAM memory cell according to the fifth embodiment; FIG. 16 is a plan view showing the configuration of the SRAM memory cell according to the fifth embodiment; FIG. 16 is a circuit diagram in which transistors are arranged corresponding to the layout of the SRAM memory cell according to the fifth embodiment. FIG. 25 is a plan view showing the configuration of the SRAM memory cell according to the sixth embodiment; FIG. 25 is a plan view showing the configuration of the SRAM memory cell according to the sixth embodiment; FIG. 25 is a plan view showing the configuration of the SRAM memory cell according to the sixth embodiment; FIG. 20 is a circuit diagram in which transistors are arranged corresponding to the layout of the SRAM memory cell according to the sixth embodiment. FIG. 24 is a plan view showing the configuration of the SRAM memory cell according to the seventh embodiment; FIG. 24 is a plan view showing the configuration of the SRAM memory cell according to the seventh embodiment; FIG. 24 is a plan view showing the configuration of the SRAM memory cell according to the seventh embodiment; FIG. 16 is a circuit diagram in which transistors are arranged corresponding to the layout of the SRAM memory cell according to the seventh embodiment. FIG. 38 is a plan view showing the configuration of the SRAM tap cell (F ′) according to the seventh embodiment; FIG. 38 is a plan view showing the configuration of the SRAM tap cell (F ′) according to the seventh embodiment; FIG. 29 is a plan view showing the configuration of the SRAM memory cell according to the eighth embodiment; FIG. 29 is a plan view showing the configuration of the SRAM memory cell according to the eighth embodiment; FIG. 29 is a plan view showing the configuration of the SRAM memory cell according to the eighth embodiment; FIG. 25 is a circuit diagram in which transistors are arranged corresponding to the layout of the SRAM memory cell according to the eighth embodiment. FIG. 22 is an equivalent circuit diagram showing an SRAM memory cell according to the ninth embodiment; FIG. 38 is a plan view showing the configuration of the SRAM memory cell according to the ninth embodiment; FIG. 38 is a plan view showing the configuration of the SRAM memory cell according to the ninth embodiment; FIG. 38 is a plan view showing the configuration of the SRAM memory cell according to the ninth embodiment; FIG. 25 is a circuit diagram in which transistors are arranged corresponding to the layout of the SRAM memory cell according to the ninth embodiment. FIG. 38 is a plan view showing the configuration of the SRAM memory cell according to the tenth embodiment; FIG. 38 is a plan view showing the configuration of the SRAM memory cell according to the tenth embodiment; FIG. 38 is a plan view showing the configuration of the SRAM memory cell according to the tenth embodiment; FIG. 38 is a circuit diagram in which transistors are arranged corresponding to the layout of the SRAM memory cell according to the tenth embodiment. FIG. 22 is an equivalent circuit diagram showing an SRAM memory cell according to the eleventh embodiment; FIG. 38 is a plan view showing the configuration of the SRAM memory cell according to the eleventh embodiment; FIG. 38 is a plan view showing the configuration of the SRAM memory cell according to the eleventh embodiment; FIG. 38 is a plan view showing the configuration of the SRAM memory cell according to the eleventh embodiment; FIG. 44 is a circuit diagram in which transistors are arranged corresponding to the layout of the SRAM memory cell according to the eleventh embodiment; FIG. 38 shows a layout configuration of a semiconductor chip in a twelfth embodiment. 3 is a plan view showing a configuration example of a part of the SRAM memory cell according to the first embodiment; FIG. The top view of the memory cell of SRAM of a comparative example is shown. It is a top view which shows a part of SRAM memory cell of a comparative example.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Are partly or entirely modified, application examples, detailed explanations, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Furthermore, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same or related reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted. In addition, when there are a plurality of similar members (parts), a symbol may be added to the generic symbol to indicate an individual or specific part. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment 1)
[Circuit configuration]
The semiconductor device (semiconductor memory device, semiconductor integrated circuit device) of the present embodiment has an SRAM memory cell. FIG. 1 is an equivalent circuit diagram showing the SRAM memory cell of the present embodiment. As shown in the figure, the memory cell is arranged at an intersection between a pair of bit lines (bit line BL, bit line / (bar) BL) and a word line WL. This memory cell includes a pair of load transistors (load MOS, load transistor, load MISFET) TP1, TP2, a pair of access transistors (access MOS, access transistor, access MISFET, transfer transistor) TNA1, TNA2, and a pair of Driver transistors (driver MOS, driving transistor, driving MISFET) TND2 and TND4 are provided.

  In this embodiment, the driver transistor TND1 connected in parallel with the driver transistor TND2 is provided. The driver transistor TND3 is connected in parallel with the driver transistor TND4. Of the eight transistors constituting the memory cell, the load transistors (TP1, TP2) are p-type (p-channel type) transistors that are the first conductivity type, and access transistors (TNA1, TNA2) and driver transistors. (TND1, TND2, TND3, TND4) are n-type (n-channel type) transistors which are the second conductivity type.

  MOS is an abbreviation for Metal Oxide Semiconductor, and MISFET is an abbreviation for Metal Insulator Semiconductor Field Effect Transistor. Hereinafter, the load transistor, the access transistor, and the driver transistor may be simply referred to as “transistors”. In addition, each transistor may be indicated only by the sign of each transistor.

  Of the eight transistors constituting the memory cell, TND2 and TP1 constitute a CMOS (Complementary MOS) inverter (may be a CMIS inverter), and TND4 and TP2 constitute another CMOS inverter. is doing. The mutual input / output terminals (storage nodes A and B) of the pair of CMOS inverters are cross-coupled to form a flip-flop circuit as an information storage unit for storing 1-bit information.

  Here, in the SRAM memory cell of the present embodiment, since TND1 is provided in parallel with TND2, and TND3 is provided in parallel with TND4, a CMOS inverter is configured by TND1, TND2, and TP1, and TND3, It can also be seen that another CMOS inverter is configured with TND4 and TP2.

  Therefore, the connection relation of the eight transistors constituting the SRAM memory cell of this embodiment will be described in detail as follows.

  TP1 is connected between the power supply potential (VDD, first power supply potential) and the storage node A, and the storage node A and the ground potential (VSS, GND, reference potential, second power supply potential lower than the first power supply potential, TND1 and TND2 are connected in parallel between the first power supply potential and a second power supply potential different from the first power supply potential, and the gate electrodes of TP1, TND1 and TND2 are connected to the storage node B.

  TP2 is connected between the power supply potential and storage node B, TND3 and TND4 are connected in parallel between storage node B and the ground potential, and the gate electrodes of TP2, TND3, and TND4 are connected to storage node A. The

  TNA1 is connected between bit line BL and storage node A, TNA2 is connected between bit line / BL and storage node B, and the gate electrodes of TNA1 and TNA2 are connected to word line WL (word Line).

  As described above, in the SRAM memory cell of the present embodiment, the driver transistors are divided (TND1 and TND2, TND3 and TND4).

  Note that, as a way of interpretation, since the gate electrodes of TND1 and TND2 are common, it can be regarded as one transistor, but here, it will be described as two transistors. The same applies to TND3 and TND4.

[Circuit operation]
The circuit operation of the SRAM memory cell will be described. When the storage node A of the CMOS inverter is at the high potential (H), TND3 and TND4 are turned on, so that the storage node B of the other CMOS inverter is at the low potential (L). Therefore, TND1 and TND2 are turned off, and the high potential (H) of storage node A is held. That is, the state of the mutual storage nodes A and B is maintained by a latch circuit in which a pair of CMOS inverters are cross-coupled, and information is stored while the power supply voltage is applied.

  On the other hand, a word line WL is connected to each gate electrode of TNA1 and TNA2. That is, when the word line WL is at a high potential (H), TNA1 and TNA2 are turned on, and the flip-flop circuit and the bit lines (BL, / BL) are electrically connected, so that the storage nodes A, B Potential state (H or L) appears on the bit lines BL and / BL and is read as information of the memory cell.

  In order to write information into the memory cell, the word line WL is set to a high potential (H) and the TNA1 and TNA2 are turned on to electrically connect the flip-flop circuit and the bit lines (BL, / BL). Connection is made, information on the bit lines BL, / BL (a combination of H and L, or a combination of L and H) is transmitted to the storage nodes A and B, and the information is stored as described above.

[Structure of SRAM]
[Configuration of memory cell]
2 to 4 are plan views showing the configuration of the SRAM memory cell according to the present embodiment. FIG. 2 shows the arrangement of the active region Ac, the gate electrode G, and the first plug P1. FIG. 3 shows an arrangement of the first plug P1, the first layer wiring M1, and the second plug P2. FIG. 4 shows the arrangement of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3. Therefore, in FIG. 2 and FIG. 3, the positional relationship of the display pattern in each figure becomes clear by overlapping the plan views with the first plug P1 as a reference. In FIGS. 3 and 4, the positional relationship of the display patterns in each figure becomes clear by overlapping the plan views with the second plug P2 as a reference. Note that a rectangular area surrounded by an alternate long and short dash line in the figure indicates a 1 (1 bit) memory cell area.

  6 to 11 are cross-sectional views showing the configuration of the SRAM memory cell according to the present embodiment. 6 corresponds to the A-A 'cross section of FIG. 2, FIG. 7 corresponds to the B-B' cross section of FIG. 2, and FIG. 8 corresponds to the C-C 'cross section of FIG. 9 corresponds to the A-A ′ cross section of FIG. 2, FIG. 10 corresponds to the B-B ′ cross section of FIG. 2, and FIG. 11 corresponds to the C-C ′ cross section of FIG. 9 to 11 also show the upper layer pattern from the first plug P1 shown in FIG. 2, and FIGS. 9 to 11 show the case where the plan views shown in FIGS. It corresponds to the AA ′ cross section, BB ′ cross section and CC ′ cross section, respectively.

[Memory cell pattern layout]
[Ac, G, P1]
As shown in FIG. 2, the semiconductor substrate includes a p-type well (P-well, first region, first conductivity type first well), an n-type well (N-well, second region, second conductivity type first well). 2 wells) and a p-type well (P-well, third region, first conductivity type third well) are arranged side by side in the X direction (first direction). In FIG. 2, only 1 (1 bit) memory cell region is shown, but as will be described later, the memory cells are arranged in the X direction (first direction) and the Y direction (second direction intersecting the first direction). Since these are repeatedly arranged (see FIG. 12), these wells (P-well, N-well, P-well) extend in the Y direction. Note that the exposed regions of these wells become active regions (active regions, transistor formation regions, Ac).

  In addition, six active regions (AcP2, AcP1, AcN1, AcN2, AcP3, AcP4) are arranged in the X direction on the semiconductor substrate. An element isolation region (STI) is formed between these active regions (Ac). In other words, the active region (Ac) is partitioned by the element isolation region (STI) or the pattern of the active region is isolated. Each well (P-well, N-well, P-well) is connected at the lower part of the element isolation region STI (see FIG. 6).

  In other words, AcP2 and AcP1 are arranged so as to be separated from each other in the X direction (first direction).

  Similarly, AcN1 and AcN2, and AcP3 and AcP4 are also arranged so as to be separated from each other in the X direction (first direction).

  Furthermore, in other words, AcP2 is arranged so as to sandwich element isolation between AcP1 and the X direction (first direction).

  Similarly, AcN2 is arranged so as to sandwich element isolation in the X direction (first direction) with AcN1.

  Further, AcP4 is arranged so as to sandwich element isolation in the X direction (first direction) with AcP3.

  Further describing each active region, the active region AcP2 is an exposed region of a p-type well (P-well) and has a substantially rectangular shape having a long side in the Y direction. The active region AcP1 is disposed next to the active region AcP2, is an exposed region of a p-type well (P-well), and has a substantially rectangular shape having a long side in the Y direction. In FIG. 2, for the sake of convenience, only 1 (1 bit) memory cell region is shown, but as will be described later, the memory cells are repeatedly arranged in the X direction and the Y direction (see FIGS. 12 and 13). In the memory cell array, the active region AcP1 extends in a line shape in the Y direction (see FIG. 13). The “line shape” can also be considered as “a substantially rectangular shape having long sides in the Y direction”.

  The active region AcN1 is an exposed region of an n-type well (N-well) and has a substantially rectangular shape having a long side in the Y direction. The active region AcN2 is an exposed region of an n-type well (N-well) and has a substantially rectangular shape having a long side in the Y direction.

  The active region AcP3 is an exposed region of a p-type well (P-well) located on the right side of the n-type well in the drawing, and has a substantially rectangular shape having a long side in the Y direction. The active region AcP4 is disposed next to the active region AcP3, is an exposed region of the p-type well (P-well), and has a substantially rectangular shape having a long side in the Y direction. In the memory cell array, the active region AcP3 extends in a line shape in the Y direction as in the case of AcP1 (see FIG. 13).

  On the above six active regions (AcP2, AcP1, AcN1, AcN2, AcP3, AcP4), gate electrodes (gate wiring, straight gate) G are respectively connected via gate insulating films (GO, see FIG. 7 etc.). The eight transistors described above in the section of “Circuit Configuration” extend to extend across the active region in the X direction. Note that the active regions (Ac) on both sides of the gate electrode G become the source / drain regions of the transistor (see FIG. 7 and the like).

  Hereinafter, the gate electrode G will be described in detail. For gate electrodes, the symbol “G” is used as a generic term. However, in the following description, when an individual gate electrode is indicated, a symbol (1 to 4 etc.) is added to the symbol (G). Shall be shown. Also in the corresponding drawings, there are cases where a generic code (G) is used and symbols (1 to 4 etc.) are added to the code (G). Further, in this specification, in addition to G (gate electrode), P1 (first plug), M1 (first layer wiring) and M2 (second layer wiring) are also provided with symbols (numbers and alphabets) as symbols. It may be added and shown.

  Specifically, a common gate electrode G1 is arranged so as to cross over the active regions AcP2, AcP1, and AcN1. As a result, TND2 is disposed on the active region AcP2, TND1 is disposed on the active region AcP1, and TP1 is disposed on the active region AcN1, and these gate electrodes (G) are connected. TP1 is disposed in the active region AcN1, and P-type source / drain regions of TP1 are provided on both sides of the gate electrode G.

  On the active region AcP1, another gate electrode G2 is arranged in parallel with the common gate electrode G1. Thereby, TNA1 is arranged on the active region AcP1, and the N-type source / drain region of TNA1 and the N-type source / drain region of TND1 are connected (shared).

  A common gate electrode G3 is arranged so as to cross over the active regions AcP4, AcP3 and AcN2. As a result, TND4 is disposed on the active region AcP4, TND3 is disposed on the active region AcP3, and TP2 is disposed on the active region AcN2, and these gate electrodes (G) are connected. TP2 is disposed in the active region AcN2, and P-type source / drain regions of TP2 are provided on both sides of the gate electrode G.

  On the active region AcP3, another gate electrode G4 is arranged in parallel with the common gate electrode G3. As a result, TNA2 is arranged on active region AcP3, and the N-type source / drain region of TNA2 and the N-type source / drain region of TND3 are connected (shared).

  The four gate electrodes G (G1 to G4) are arranged two by two on the same line (in a straight line). Specifically, the common gate electrode G1 crossing over the active regions AcP2, AcP1 and AcN1 and the gate electrode G4 on the active region AcP3 are arranged on the same line extending in the X direction. The common gate electrode G3 crossing over the active regions AcP4, AcP3 and AcN2 and the gate electrode G2 on the active region AcP1 are arranged on the same line extending in the X direction.

  As described above, in this embodiment, the driver transistors are divided (TND1 and TND2, TND3 and TND4), and arranged on different active regions (AcP2 and AcP1, AcP4 and AcP3). Furthermore, by extending these active regions (AcP2 and AcP1, AcP4 and AcP3) in the Y direction, a simple layout is obtained and the processing accuracy is improved.

  FIG. 64 shows a plan view of an SRAM memory cell of a comparative example of the present embodiment. The equivalent circuit of this memory cell is obtained by omitting TND2 and TND4 in the circuit diagram shown in FIG. In this case, in order to improve the driving capability of the driver transistors TND1 and TND3, it is necessary to devise such as increasing the width (gate width, channel width) of the active region or increasing the gate length.

  It is preferable that the driving capability of the driver transistors (TND1, TND3) be larger than the driving capability of the access transistors (TNA1, TNA2). For example, the gate width of the access transistor and the gate width of the driver transistor are preferably 1: 2. A ratio of these drive capacities expressed as a gate width ratio is called a “β ratio”. The “β ratio” will be described in detail later.

  Therefore, in this case, as shown in FIG. 64, corners (bent portions, stepped portions) are generated in the shape of the active region (Ac). However, in reality, patterning (processing) according to a desired shape (reticle pattern) is difficult. For example, as shown in FIG. 65, corners are not formed with good accuracy, and the width of the active region gradually increases. The smooth shape becomes larger. FIG. 65 is a plan view showing a part of the SRAM memory cell of the comparative example of the present embodiment. In such a case, the gate width varies depending on the location in TNA1, and the transistor characteristics of TNA1 deteriorate. Further, in the memory cell array, the processing accuracy is often different for each memory cell, resulting in manufacturing variations. In such a case, the variation of the characteristic for every memory cell becomes large, which causes a product defect. Furthermore, such a problem becomes particularly noticeable with the miniaturization of memory cells.

  In contrast, in the present embodiment, as described above, the driver transistors are divided (TND1 and TND2, TND3 and TND4), and are arranged on different active regions (AcP2 and AcP1, AcP4 and AcP3). Therefore, the drive capability of the driver transistors (TND1, TND3) can be made larger than the drive capability of the access transistors (TNA1, TNA2). For example, by setting the width (length in the X direction) of the active regions (AcP2 and AcP1, AcP4 and AcP3) to 1: 1, the gate width of the access transistor and the gate width of the driver transistor can be easily set to 1: 2. It can be.

  Further, by dividing the active region (TND1 and TND2, TND3 and TND4), each active region can be formed into a substantially rectangular shape. In other words, the shape without the corner can be obtained. Therefore, the processing accuracy is improved, and the characteristics of each transistor formed on the active region (Ac) can be improved. In addition, manufacturing variations can be reduced and the operating characteristics of the SRAM memory cell array can be improved. In addition, the manufacturing yield can be improved.

  Further, in one of the divided active regions (TND1 and TND2, TND3 and TND4) (AcP1 or AcP3 in FIG. 2), in addition to the driver transistors (TND1, TND3), access transistors (TNA1, TNA2) are also arranged. Therefore, the number of active regions can be reduced. As a result, a simple layout can be realized, and the memory cell area can be reduced.

  Further, by extending the active region (Ac) in the Y direction, the gate electrode (G) can be extended in the X direction, and not only the processing accuracy of the active region (Ac) but also the gate electrode (G). The machining accuracy can be improved. In particular, a multiple exposure technique may be used for processing a fine pattern. For example, after performing exposure in a line in the X direction, exposure in the Y direction, that is, exposure of an area to be separated is performed. By using such a double exposure technique, the processing accuracy of the photoresist film can be improved, and in turn, the processing accuracy of the underlying etching target film can be improved. When such a multiple exposure technique is used, the pattern shape is preferably a line shape. Therefore, by arranging the active region (Ac) and the gate electrode (G) linearly as described above, the multiple exposure technique can be easily adopted and the processing accuracy can be improved. Moreover, simulation model creation becomes easy and the verification accuracy can be improved.

[P1, M1, P2]
As shown in FIG. 3, the first plug P1 is formed on the source / drain regions of the eight transistors (TND2, TNA1, TND1, TP1, TP2, TND3, TNA2, TND4) described with reference to FIG. Be placed. The first plugs P1 are also disposed on the four gate electrodes described with reference to FIG.

  A first layer wiring M1 is disposed on the first plug P1, and electrical connection between the first plugs P1 is achieved.

  Specifically, the first plug P1a on one source / drain region of TND2, the first plug P1b on the common source / drain region of TND1 and TNA1, and the first plug P1c on one source / drain region of TP1. , And the first plug P1d on the common gate electrode G3 of TP2, TND3, and TND4 is connected by a first layer wiring (first node wiring) M1A. The first layer wiring M1A (first node wiring) can be associated with the storage node A in FIG. The above "one" indicates the upper source / drain region in FIG.

  A first plug P1e on one source / drain region of TND4, a first plug P1f on a common source / drain region of TND3 and TNA2, a first plug P1g on one source / drain region of TP2, and TP1 The first plug P1h on the common gate electrode G1 of TND1 and TND2 is connected by the first layer wiring (second node wiring) M1B. The first layer wiring M1B (second node wiring) can be associated with the storage node B of FIG. The first layer wiring M1 (M1A, M1B) corresponding to the storage node (A or B) is arranged so as to extend mainly in the X direction. Here, “one” means the lower source / drain region in FIG.

  The first plug P1i on the other source / drain region of TND2 and the first plug P1j on the other source / drain region of TND1 are connected by the first layer wiring M1S. The first layer wiring M1 can be associated with the ground potential (VSS) in FIG. 1, and is connected to the ground potential line (LVSS) as will be described later.

  The first plug P1k on the other source / drain region of TND4 and the first plug P1m on the other source / drain region of TND3 are connected by a first layer wiring M1S. The first layer wiring M1S can be associated with the ground potential (VSS) in FIG. 1, and is connected to the ground potential line (LVSS) as described later.

  The first layer wiring M1 (M1BL, M1D) is disposed on the first plug P1n on the other source / drain region of TNA1 and the first plug P1o on the other source / drain region of TP1. . Further, the first layer wiring M1 (M1BL, M1D) is disposed on the first plug P1p on the other source / drain region of TNA2 and the first plug P1q on the other source / drain region of TP2, respectively. .

  Further, the first layer wiring M1W is arranged on the first plug P1r on the gate electrode G2 of TNA1 and the first plug P1s on the gate electrode G4 of TNA2. The first layer wiring M1W connected to the gate electrodes G (G2, G4) is arranged to extend in the Y direction at the end of the memory cell region in the X direction. M1 (M1S, M1D, M1BL) is arranged so as to extend mainly in the X direction, similarly to the first layer wiring M1 (M1A, M1B) corresponding to the storage node (A or B).

  The connection state by the first layer wiring M1 between the plurality of first plugs P1 can be variously modified as long as the connection state of the circuit diagram shown in FIG. 1 is satisfied. A simple layout can be realized by extending the first layer wiring M1 in the Y direction at the end and extending the first layer wiring M1 in the X direction inside the memory cell region. .

[P2, M2, P3, M3]
As shown in FIG. 4, among the first layer wiring M1 described with reference to FIG. 3, the first layer other than the first layer wiring M1 (M1A, M1B) corresponding to the storage node (A or B). A second plug P2 is disposed on the wiring M1 (M1S, M1D, M1BL, M1W), and a second layer wiring M2 is disposed above the second plug P2.

  Specifically, the first layer wiring M1W connected to the gate electrode G (G2) of TNA1 is connected to the second layer wiring M2W via the second plug P2. The first layer wiring M1W connected to the gate electrode G (G4) of TNA2 is connected to the second layer wiring M2W via the second plug P2. These two second layer wirings M2W are arranged so as to extend in the Y direction at both ends in the X direction of the memory cell region. Further, a third plug P3 is disposed on the two second layer wirings M2W, and a third layer wiring M3 (WL) is disposed in the X direction so as to connect the two third plugs P3. . The third layer wiring M3 (WL) is a word line. Therefore, the second layer wiring M2W is sometimes referred to as “second layer wiring connected to the word line”.

  The first layer wiring M1S connected to the other source / drain region of TND2 and the other source / drain region of TND1 is connected to the second layer wiring M2 (LVSS) via the second plug P2. . The second layer wiring M2 (LVSS) is a ground potential line (second power supply potential line to which a second power supply potential is supplied). The first layer wiring M1S connected to the other source / drain region of TND4 and the other source / drain region of TND3 is connected to the second layer wiring M2 (LVSS) via the second plug P2. The second layer wiring M2 (LVSS) is a ground potential line. These two ground potential lines are arranged so as to respectively extend in the Y direction inside the two second layer wirings M2 (M2W) arranged at both ends of the memory cell region described above.

  Further, the first layer wiring M1BL connected to the other source / drain region of the TNA1 is connected to the second layer wiring M2 (BL, first bit line) via the second plug P2. This second layer wiring M2 (BL) is one bit line of the bit line pair. The first layer wiring M1BL connected to the other source / drain region of TNA2 is connected to the second layer wiring M2 (/ BL) via the second plug P2. The second layer wiring M2 (/ BL, second bit line) is another bit line. These two bit lines (BL, / BL, bit line pair) are arranged so as to extend in the Y direction, respectively, inside the two ground potential lines (LVSS).

  Further, the second plug P2 on the first layer wiring M1D connected to the other source / drain region of TP1, and the second plug P2 on the first layer wiring M1D connected to the other source / drain region of TP2. The second layer wiring M2 (LVDD) is arranged so as to be connected to each other. The second layer wiring M2 (LVDD) is a power supply potential line (a first power supply potential line to which a first power supply potential is supplied). This power supply potential line extends mainly in the Y direction between the two bit lines (BL, / BL) described above, but the line portion extending in the Y direction and the second plug P2 from this line portion. And a protrusion that covers the top.

  The connection state of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3 can be variously modified as long as the connection state of the circuit diagram shown in FIG. 1 is satisfied. As described above, a simple layout can be realized by extending the second layer wiring M2 mainly in the Y direction and extending the third layer wiring M3 mainly in the X direction. 2 to 4 show only a memory cell area of 1 (1 bit) for convenience, but the memory cells are repeatedly arranged in the X direction and the Y direction as will be described later. The ground potential lines (LVSS), bit lines (BL, / BL), and power supply potential lines (LVDD) extend in the Y direction, and the word lines (WL) extend in the X direction (see FIG. 14).

  In the present embodiment, since the active regions are divided and arranged (AcP2 and AcP1, AcP4 and AcP3), driver transistors (TND1, TND2, TND3) corresponding to the element isolation regions (STI) located between the active regions. And TND4) are formed in a larger area. By using this area, the second layer wiring M2W (second layer wiring connected to the word line) and the bit lines (BL, / BL) are used as described above. A ground potential line (LVSS) can be provided therebetween. As a result, the shielding effect of the ground potential line (LVSS) occurs, and the interaction (crosstalk noise) between the second layer wiring M2W (second layer wiring connected to the word line) and the bit lines (BL, / BL). Can be reduced.

  Further, the distance (d1) between the ground potential line (LVSS) and the bit lines (BL, / BL) can be increased, and the wiring capacitance between these wirings can be reduced. Further, the distance (d2) between the power supply potential line (LVDD) and the bit lines (BL, / BL) can be increased, and the wiring capacitance between these wirings can be reduced. In particular, since the bit lines (BL, / BL) are wirings that play an important role in reading and writing data, a potential change due to noise or the like greatly affects the memory operation. Therefore, the interval (d1) between the ground potential line (LVSS) and the bit lines (BL, / BL) and the interval (d2) between the power supply potential line (LVDD) and the bit lines (BL, / BL) are increased. Thus, the operating characteristics of the memory can be improved. For example, when the distance between the second layer wiring M2W (second layer wiring connected to the word line) and the bit lines (BL, / BL) is d3, the memory can be obtained by setting d3 <d1, d3 <d2. The operating characteristics can be improved.

  Each pattern described with reference to FIGS. 2 to 4 is arranged point-symmetrically with respect to the center point of the memory cell region.

  For reference, eight transistors (TND2, TNA1, TND1, TP1, TP2, TND3, TNA2, TND4) are arranged in correspondence with the above “memory cell pattern layout”, and their connection states are clearly shown. A circuit diagram is shown in FIG.

[Memory cell cross-sectional structure]
Next, the structure of the SRAM memory cell according to the present embodiment will be clarified by describing the cross-sectional structure of the layout described above with reference to the cross-sectional views of FIGS.

  As shown in FIGS. 6 to 8, an element isolation region STI is formed in the semiconductor substrate 1. The active region (Ac) is partitioned by the element isolation region STI. That is, a region surrounded by the element isolation region STI becomes an active region (Ac). As described above, six active regions (AcP2, AcP1, AcN1, AcN2, AcP3, AcP4) are arranged side by side in the X direction, and the state can be seen from the cross-sectional view shown in FIG.

  This element isolation region STI can be formed using an STI (shallow trench isolation) method. That is, an element isolation trench is formed in the semiconductor substrate 1 using a photolithography technique and an etching technique. Then, a silicon oxide film is formed on the semiconductor substrate so as to fill the element isolation trench, and then an unnecessary silicon oxide film formed on the semiconductor substrate is formed by chemical mechanical polishing (CMP). Remove. As a result, the element isolation region STI in which the silicon oxide film is buried only in the element isolation trench can be formed. The element isolation region STI may be formed using a LOCOS (local Oxidation of silicon) method.

  Further, in the semiconductor substrate 1, a p-type well (P-well) containing a p-type impurity (for example, boron) and an n-type well (N) containing an n-type impurity (for example, phosphorus or arsenic) are included. -Well) is formed. The p-type well (P-well) can be formed by introducing a p-type impurity into the active region (Ac) using, for example, an ion implantation method, and the n-type well (N-well) is formed by, for example, The n-type impurity can be formed by introducing an n-type impurity into the active region (Ac) using an ion implantation method. As described above, these wells are connected at the lower part of the element isolation region STI, and extend in the Y direction with a predetermined width (see FIGS. 6 and 12, etc.). Further, three wells (P-well, N-well, P-well) are arranged in the X direction. In other words, the p-type well (P-well) is disposed on both sides of the n-type well (N-well). A semiconductor region for channel formation (not shown) may be formed on the surface of each well. This channel forming semiconductor region is formed to adjust the threshold voltage for forming the channel.

  A gate insulating film GO is formed on the main surface of the active region (Ac). For example, a silicon oxide film can be used as the gate insulating film GO. The gate insulating film GO can be formed using, for example, a thermal oxidation method, a CVD method, or the like.

  A gate electrode G is formed on the gate insulating film GO (FIGS. 7 and 8). As the gate electrode G, for example, a polycrystalline silicon film can be used. For example, the gate electrode G can be formed by depositing and patterning a polycrystalline silicon film on the semiconductor substrate 1 including the gate insulating film GO by the CVD method or the like. Note that the gate electrode G may be formed of a laminated film of a polycrystalline silicon film and a metal film.

  Alternatively, the gate insulating film may be changed to a high-K film and the gate electrode may have a metal gate structure.

  Here, patterning refers to a step of exposing and developing a photoresist film on a processing target film to obtain a desired shape, and then etching the processing target film using the photoresist film as a mask. When patterning the gate electrode (G), the gate electrode (G) arranged with a fine line width and space width can be formed with good accuracy by using the double exposure technique as described above. The layout of the present embodiment described above (see FIG. 2 and the like) is also suitable when the double exposure technique is applied.

  Further, in the p-type well (P-well) on both sides of the gate electrode G, an n-type low concentration impurity region EX1 is formed (FIGS. 7 and 8). This n-type low concentration impurity region EX1 can be formed by introducing an n-type impurity into the active region (AcP) by ion implantation using the gate electrode G as a mask. In the n-type well (N-well) on both sides of the gate electrode G, a p-type low concentration impurity region EX1 is formed (FIGS. 7 and 8). This p-type low-concentration impurity region EX1 can be formed by introducing a p-type impurity into the active region (AcN) by ion implantation using the gate electrode G as a mask.

  Further, sidewalls SW are formed on the sidewalls on both sides of the gate electrode G (FIGS. 7 and 8). The sidewall SW is made of, for example, a silicon nitride film. For example, after an insulating film such as a silicon nitride film is deposited on the semiconductor substrate 1 including the gate electrode G by CVD, anisotropic etching is performed so that the insulating film is used as the sidewall SW on the side wall of the gate electrode G. It can be left.

  An n-type high concentration impurity region EX2 is formed in the p-type well (P-well) on both sides of the composite of the gate electrode G and the sidewall SW (FIGS. 7 and 8). This n-type high-concentration impurity region EX2 can be formed by introducing an n-type impurity by ion implantation using the composite as a mask. In addition, p-type high concentration impurity regions EX2 are formed in the n-type wells (N-wells) on both sides of the composite (FIGS. 7 and 8). This p-type high-concentration impurity region EX2 can be formed by introducing a p-type impurity by ion implantation using the composite as a mask. The high concentration impurity region EX2 has a higher impurity concentration and is formed deeper than the low concentration impurity region EX1. The low concentration impurity region EX1 and the high concentration impurity region EX2 constitute a source / drain region having an LDD (Lightly Doped Drain) structure. The source / drain region refers to a region to be a source or a drain. Further, the source / drain region may be indicated as “one end” or “the other end” of the transistor.

  As described above, in the present embodiment, the driver transistors are divided (TND1 and TND2, TND3 and TND4) and arranged on different active regions (AcP2 and AcP1, AcP4 and AcP3). This configuration is also apparent from the cross section shown in FIG. In this embodiment, access transistors (TNA1, TNA2) are also arranged in the divided active regions (TND1 and TND2, TND3 and TND4). This configuration is also apparent from the cross section shown in FIG.

  Note that as a method of forming the transistor, a so-called gate last in which a metal gate is formed after forming a groove of a gate pattern using a dummy gate may be used.

  As shown in FIGS. 9 to 11, a plug P1 is disposed on the high concentration impurity region EX2 (source / drain region) of each transistor (TNA1, TND1, TND2, TP1, etc.). Although not shown in the sectional views of FIGS. 9 to 11, the plug P1 is also formed on the gate electrode G (see FIG. 2). The plug P1 can be formed by the following process, for example. A laminated film of a silicon nitride film and a silicon oxide film is formed as an interlayer insulating film IL1 on the semiconductor substrate 1 including on each transistor (TNA1, TND1, TND2, TP1, etc.). Next, a contact hole is formed in the interlayer insulating film IL1, and a conductive film is deposited on the interlayer insulating film IL1 including the inside of the contact hole. As the conductive film, a laminated film of a barrier film and a metal film can be used. As the barrier film, for example, a Ti (titanium) film, a TiN (titanium nitride) film, or a laminated film thereof can be used. As the metal film, for example, a W (tungsten) film can be used. By removing the conductive film other than the contact hole from the deposited conductive film using a CMP method or the like, the conductive film can be embedded in the contact hole.

  A first layer wiring M1 is disposed on the plug P1. The first layer wiring M1 can be formed by patterning a conductive film. The first layer wiring M1 may be a buried wiring (damascene wiring).

  A second layer wiring M2 (LVSS, BL, / BL, LVDD, etc.) is disposed on the first layer wiring M1 via the second plug P2. In other words, these wirings are arranged in the same layer. The second plug P2 can be formed in the interlayer insulating film IL2 in the same manner as the first plug P1. The second layer wiring M2 can be formed in the same manner as the first layer wiring M1. The second layer wiring M2 may be a buried wiring. At this time, a so-called dual damascene method may be used in which a conductive film is simultaneously buried in the contact hole and the wiring trench, and the second plug P2 and the second layer wiring M2 are simultaneously formed.

  A third layer wiring M3 (WL) is arranged on the second layer wiring M2 via a third plug P3. The third plug P3 can be formed in the interlayer insulating film IL3 in the same manner as the first plug P1. The third layer wiring M3 can be formed in the same manner as the first layer wiring M1. The third layer wiring M3 may be a buried wiring. At this time, a so-called dual damascene method may be used in which a conductive film is simultaneously buried in the contact hole and the wiring trench, and the third plug P3 and the third layer wiring M3 are formed simultaneously.

  In addition, although there is no restriction | limiting in the formation process of each pattern which comprises the said cross-sectional structure, For example, it can form in the following order. First, after forming the element isolation region STI in the semiconductor substrate 1, a well (P-well, N-well, P-well) is formed. Thereafter, the gate insulating film GO and the gate electrode G are formed, the low concentration impurity region EX1 is formed, the sidewall SW is formed, and the high concentration impurity region EX2 is formed, whereby each transistor (TNA1, TND1, TND2) is formed. , TP1, etc.) (see FIG. 7 etc.). Thereafter, the first to third layer wirings (M1 to M3) and the like are formed by repeating the steps of forming the interlayer insulating film, the plug and the wiring. Thereafter, a multilayer wiring may be formed. In addition, each pattern constituting a tap cell (power feeding cell), which will be described later, may be formed at the same time, and a peripheral circuit such as a decoder for driving the SRAM may be formed at the same time.

  Note that in the following embodiments, cross-sectional views and description of formation steps are omitted, but the cross-section of the transistor portion has a cross-sectional structure similar to that of this embodiment and can be formed in the same steps. Needless to say.

[Configuration of memory cell array]
FIG. 12 is a plan view showing the concept of the SRAM memory cell array of the present embodiment. 13 and 14 are plan views showing the configuration of the SRAM memory cell array of the present embodiment. FIG. 13 shows the layout of the pattern located from the lower layer to the second plug P2, and FIG. 14 shows the layout of the pattern above the second plug P2. 13 and FIG. 14 corresponds to a 2 × 2 cell region from the bottom to the second row in FIG. 12 and from the left to the second column.

  As shown in FIG. 12, when the memory cell region described with reference to FIGS. 2 to 4 is represented by “F”, the memory cell array extends in the X direction in the vertical direction (Y direction) in the figure. A memory cell region is repeatedly arranged symmetrically with respect to an existing line (X axis) (X axis inversion), and a line (Y axis) extending in the Y direction in the horizontal direction (X direction) in the figure The memory cell regions are repeatedly arranged in line symmetry with respect to (Y-axis inversion).

  The layout and cross-sectional structure of the memory cell region indicated by “F” (rectangular region surrounded by a one-dot chain line) will be described in detail using the plan views of FIGS. 2 to 4 and the cross-sectional views of FIGS. As explained. In the memory cell regions other than the memory cell region indicated by “F”, the shape of each pattern is provided symmetrically with respect to a line extending in the X direction or the Y direction (FIGS. 13 and 13). 14).

  Here, as described above, each well (P-well, N-well, P-well) in the memory cell region extends in the Y direction (FIG. 13). Further, since the P-well outside the memory cell region is in contact with the P-well in the adjacent memory cell region, the p-type well (P-well) and the n-type well (N− well) are alternately arranged in the X direction.

[Description of tap cell area]
As described with reference to FIG. 12, a plurality of cell regions (for example, m × n) are arranged in the memory cell array, but a tap cell region (power feeding region) is provided in the memory cell array. A predetermined potential (for example, ground potential VSS or power supply potential VDD) is supplied to each well through the tap cell region.

  FIG. 15 conceptually shows the position of the tap cell region in the SRAM memory cell array of the present embodiment. As shown in the drawing, this tap cell (feed cell) is arranged for every n memory cell regions arranged in the Y direction, and is repeatedly arranged in the X direction in line symmetry with the line extending in the Y direction. In other words, a tap cell region is arranged for every m × n array region portions, and a plurality of tap cells are arranged in the X direction in this tap cell region. Among the plurality of tap cells arranged in the X direction, one tap cell is indicated by “F ′”.

  16 and 17 are plan views showing the configuration of the SRAM tap cell (F ') of the present embodiment. FIG. 16 shows the arrangement of the active region (power feeding unit, potential applying unit) AcS, dummy gate electrode DG, first plug P1, first layer wiring M1, and second plug P2. FIG. 17 shows the arrangement of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3. Therefore, in FIG. 16 and FIG. 17, the positional relationship of display patterns in each figure becomes clear by overlapping the plan views with the second plug P2 as a reference. In addition, the rectangular area | region enclosed with the dashed-dotted line in the figure shows one tap cell area | region, for example, is set to the same magnitude | size as a memory cell area | region.

  In the memory cell region, each well (P-well, N-well, P-well) extending in the Y direction also extends in the Y direction in the tap cell shown in FIG. well), n-type well (N-well), and p-type well (P-well) are arranged in the X direction.

  An active region AcS for power supply is provided on the tap cell region, and three active regions AcS are arranged side by side in the X direction. An element isolation region (STI) is formed between these active regions (AcS).

  Specifically, each active region AcS is an exposed region of each well (P-well, N-well, P-well), and is here formed in a substantially rectangular shape having a long side in the X direction. The three active regions AcS are arranged on the same line extending in the X direction.

  A first plug P1 is disposed on the active region AcS on the left p-type well (P-well) in FIG. 16, and a first layer wiring M1 is disposed on the first plug P1. A second plug P2 is disposed on the first layer wiring M1. A second layer wiring M2 (LVSS) is disposed on the second plug P2 (FIG. 17). The second layer wiring M2 (LVSS) serves as the ground potential line described in the section “Memory cell pattern layout”. Further, in the tap cell region, the third plug P3 is disposed on the second layer wiring M2 (LVSS), and the third layer wiring M3 (CVSS) is disposed thereon. The third layer wiring M3 (CVSS) becomes a common ground potential line connected to each ground potential line of the tap cells arranged in the X direction (FIG. 17).

  A first plug P1 is disposed on the active region AcS on the n-type well (N-well), and a first layer wiring M1 is disposed on the first plug P1. A second plug P2 is disposed on the first layer wiring M1. On the second plug P2, the second layer wiring M2 (LVDD) is disposed (FIG. 17). The second layer wiring M2 (LVDD) serves as the power supply potential line described in the section “Memory cell pattern layout”. Further, in the tap cell region, the third plug P3 is disposed on the second layer wiring M2 (LVDD), and the third layer wiring M3 (CVDD) is disposed on the third plug P3. The third layer wiring M3 (CVDD) serves as a common power supply potential line connected to each ground potential line of the tap cells arranged in the X direction (FIG. 17).

  A first plug P1 is disposed on the active region AcS on the p-type well (P-well) on the right side in FIG. 16, and a first layer wiring M1 is disposed on the first plug P1. A second plug P2 is disposed on the first layer wiring M1. A second layer wiring M2 (LVSS) is disposed on the second plug P2 (FIG. 17). The second layer wiring M2 (LVSS) serves as the ground potential line described in the section “Memory cell pattern layout”. Further, in the tap cell region, the third plug P3 is disposed on the second layer wiring M2 (LVSS), and the third layer wiring M3 (CVSS) is disposed thereon. The third layer wiring M3 (CVSS) serves as the common ground potential line connected to each ground potential line of the tap cells arranged in the X direction (FIG. 17).

  Note that the bit lines (second-layer wiring M2 (BL), second-layer wiring M2 (/ BL)) described in the section of “pattern layout of memory cell” extend on the tap cell region ( FIG. 17).

  As shown in FIG. 16, in the tap cell region, a dummy gate electrode (dummy gate wiring, dummy gate) DG extending in the X direction is disposed on the element isolation region STI. The dummy gate electrode is a conductive film that is provided on the element isolation region (STI) and cannot perform a transistor operation. This conductive film is formed of the same material and the same process as the gate electrode G.

  Thus, by providing the dummy gate electrode DG, the unevenness due to the gate electrode is regularly repeated, and the regularity of the layout is improved. As a result, manufacturing variations and the like can be reduced, and device characteristics can be improved. The dummy gate electrodes DG are arranged in a line extending in the X direction, but here, a separation part Sp is provided as appropriate and arranged separately (see FIG. 16).

  FIG. 18 is a plan view showing the concept of the SRAM memory cell and tap cell formation region of the present embodiment. 19 and 20 are plan views showing the configuration of the SRAM memory cell and tap cell formation region of the present embodiment. FIG. 19 shows a layout of a pattern located from the lower layer to the second plug P2, and FIG. 20 shows a layout of a pattern above the second plug P2. The region shown in FIGS. 18 to 20 is a 2 × 3 cell region, and the tap cell region is arranged in the second row from the bottom.

  As shown in FIGS. 18 to 20, the dummy gate electrodes DG of the tap cell (F ′) are arranged at both ends in the Y direction of the tap cell so as to sandwich the active region (AcS). At this time, the dummy gate electrode DG may be arranged in a continuous line extending in the X direction, but here, the dummy gate electrode DG is appropriately cut so as to correspond to the gate electrode G of the adjacent memory cell. Has been. In other words, a separation part (Sp) is provided. By arranging the dummy gate electrode DG in this manner, the regularity of the gate electrode G and the dummy gate electrode DG can be further improved, and the device characteristics can be improved.

  Each pattern (AcS, DG, P1 to P3, M1 to M3, etc.) constituting the tap cell can be formed in the same manner as each pattern constituting the memory cell.

(Embodiment 2)
In the first embodiment, among the six active regions (AcP2, AcP1, AcN1, AcN2, AcP3, AcP4) arranged in the X direction, the divided driver transistors (TND1 and TND2) are arranged in the X direction of AcP2 and AcP1. Were equal in length (width in the X direction). Further, the lengths in the X direction (width in the X direction) of AcP4 and AcP3 in which the driver transistors (TND3 and TND4) are arranged are equal. These may be different lengths (widths). The width of the active region (Ac) in the X direction corresponds to the gate width of each transistor. Therefore, in other words, in the first embodiment, the gate width of the driver transistor (TND1) is made equal to the gate width of the driver transistor (TND2), and further the gate width of the driver transistor (TND3) and the driver transistor The gate widths of (TND4) were made equal.

  In contrast, in the present embodiment, the gate width of the driver transistor (TND1) is different from the gate width of the driver transistor (TND2), and the gate width of the driver transistor (TND3) is different from that of the driver transistor (TND4). Use different gate widths.

  21 and 22 are plan views showing the configuration of the SRAM memory cell of the present embodiment. FIG. 21 shows the arrangement of the active region Ac, the gate electrode G, and the first plug P1. FIG. 22 shows an arrangement of the first plug P1, the first layer wiring M1, and the second plug P2. Therefore, in FIG. 21 and FIG. 22, the positional relationship of display patterns in each figure becomes clear by overlapping the plan views with the first plug P1 as a reference. The configuration above the second plug P2, that is, the arrangement of the second layer wiring M2, the third plug P3, and the third layer wiring M3 is the case of the first embodiment described with reference to FIG. Is the same. In addition, a rectangular area surrounded by an alternate long and short dash line in the figure indicates a 1 (1 bit) memory cell area.

  The configuration of the memory cell is the same as that of the first embodiment except for the length in the X direction (width in the X direction) of AcP2 and AcP1 and the length in the X direction (width in the X direction) of AcP4 and AcP3. Therefore, detailed description thereof is omitted.

  As shown in FIG. 21, for example, when the widths of the active region AcP2 and the active region AcP1 are WAcP2 and WAcP1, respectively, WAcP2 <WAcP1 may be satisfied. Further, when the widths of the active region AcP3 and the active region AcP4 are WAcP3 and WAcP4, respectively, WAcP4 <WAcP3 may be satisfied.

  As described above, in the present embodiment, the ratio between the drive capability of the driver transistors (TND1 and TND2, TND3 and TND4) and the drive capability of the access transistors (TNA1, TNA2) can be easily adjusted. That is, the β ratio can be easily adjusted simply by changing the widths of the active regions (AcP2 and AcP1, AcP4 and AcP3).

  In the first embodiment, the gate width of the access transistor (TNA1, TNA2) and the gate width of the driver transistor (the sum of the gate widths of TND1 and TND2, the sum of the gate widths of TND3 and TND4) are 1: 2. This ratio is appropriately adjusted according to the characteristics of the SRAM. In other words, depending on the device, there are cases where it is desired to change the capacity ratio between the access transistor and the driver transistor in accordance with the intended use, such as making the reading characteristics better than writing. Here, the gate width of the access transistors (TNA1, TNA2) is “a”, and the gate width of the driver transistor (the sum of the gate widths of TND1 and TND2, the sum of the gate widths of TND3 and TND4) is “b”. With respect to the ratio a: b, the value of b when a is 1 (that is, b / a, sometimes referred to as “β ratio”) can be easily adjusted. As for the range of adjustment, for example, b / a is preferably adjusted within a range of 1.1 to 3. Furthermore, it is more preferable to adjust b / a in the range of 1.5 to 2.5.

  For example, if b / a = 1.1, when the gate widths of the driver transistor TND1 and the access transistor TNA1 are equal to 1, the gate width of the driver transistor TND2 is 0.1, which is a considerably narrow gate width. As a result, the pattern is not stable.

  For this reason, the gate widths of the driver transistors TND1 and TND2 are about 0.75.

  On the other hand, if b / a = 1.5, the gate width of the driver transistor TND2 becomes 0.5, and a temporary pattern can be formed, or the gate widths of the driver transistor TND1 and the access transistor TNA1 are equal. Can be close to the direction.

  For example, when b / a = 3, the gate width of the access transistor TNA1 is 1, and the gate widths of the driver transistors TND1 and TND2 are 1.5.

  In contrast, when the gate width of the access transistor TNA1 is 1, and the gate widths of the driver transistors TND1 and TND2 are 1.25, the difference between the gate widths of the access transistor TNA1 and the driver transistor TND1 is “b / a This is preferable in that it can be made smaller than the case of 3 ″.

  Although there are no restrictions on the widths of the other active regions (AcN1, AcN2), the widths of the active regions AcP2 and AcP4 are set to be the same here.

  In addition, the β ratio may be adjusted by reversing the above relationship (WAcP2> WAcP1, WAcP4> WAcP3). There are few, and it is thought that the controllability of characteristics is high.

  Further, since the arrangement of the gate electrode G and the first plug P1 is the same as that of the first embodiment (FIG. 2), the description thereof is omitted. Also, the arrangement of the first plug P1, the first layer wiring M1, and the second plug P2 shown in FIG. 22 is the same as that in the first embodiment (FIG. 3), and thus the description thereof is omitted.

  Thus, in the present embodiment, in addition to the effects described in detail in Embodiment 1, the above effects can be achieved.

(Embodiment 3)
In the tap cell described in the first embodiment, the active region AcS on the p-type well (P-well) is connected to the second layer wiring M2 (LVSS), and the active region AcS on the n-type well (N-well). Was connected to the second layer wiring M2 (LVDD). The second layer wiring M2 (LVSS) is the ground potential line described in the “Memory cell pattern layout” column, and the second layer wiring M2 (LVDD) is in the “Memory cell pattern layout” column. This is the power supply potential line described. That is, the well power supply is performed through the ground potential line and the power supply potential line connected to the memory cell, but the well power supply may be performed using a wiring (third potential wiring) other than the ground potential line and the power supply potential line. Good. In the present embodiment, the second ground potential line (LVSSB) is used as the power supply wiring for the p-type well (P-well).

[Description of tap cell area]
23 and 24 are plan views showing the configuration of the SRAM tap cell of the present embodiment. FIG. 23 shows the arrangement of the active region AcS, the dummy gate electrode DG, the first plug P1, the first layer wiring M1, and the second plug P2. FIG. 24 shows the arrangement of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3. Therefore, in FIG. 23 and FIG. 24, the positional relationship of the display pattern in each figure becomes clear by overlapping the plan views with the second plug P2 as a reference. Note that a rectangular area surrounded by an alternate long and short dash line in the figure indicates one tap cell area (for example, an area corresponding to F ′ in FIG. 18), and is set to the same size as the memory cell area, for example. .

  In the memory cell region, each well (P-well, N-well, P-well) extending in the Y direction also extends in the Y direction in the tap cell shown in FIG. well), n-type well (N-well), and p-type well (P-well) are arranged in the X direction.

  An active region AcS for power supply is provided on the tap cell region, and three active regions AcS are arranged side by side in the X direction. An element isolation region (STI) is formed between these active regions (AcS).

  Specifically, each active region AcS is an exposed region of each well (P-well, N-well, P-well), and is here formed in a substantially rectangular shape having a long side in the X direction. The three active regions AcS are arranged on the same line extending in the X direction.

  A first plug P1 is disposed on the active region AcS on the p-type well (P-well) on the right side of the drawing, and a first layer wiring M1 is disposed on the first plug P1. A second plug P2 is disposed on the first layer wiring M1 (FIG. 23). On the second plug P2, the second layer wiring M2 (LVSSB) is disposed (FIG. 24).

  The second layer wiring M2 (LVSSB) is a second ground potential line, and is different from the ground potential line (second layer wiring M2 (LVSS)) described in the section of “Memory cell pattern layout”. Become. Further, in the tap cell region, the third plug P3 is disposed on the second layer wiring M2 (LVSS), and the third layer wiring M3 is disposed on the third plug P3. This third layer wiring M3 becomes a common second ground potential line connected to each second ground potential line of the tap cells arranged in the X direction (FIG. 24).

  Similarly, a first plug P1 is disposed on the active region AcS on the p-type well (P-well) on the right side of the drawing, and a first layer wiring M1 is disposed on the first plug P1. Yes. A second plug P2 is disposed on the first layer wiring M1. A second layer wiring M2 (LVSSB) is disposed on the second plug P2.

  The second layer wiring M2 (LVSSB) is a second ground potential line, and is different from the ground potential line (second layer wiring M2 (LVSS)) described in the section of “Memory cell pattern layout”. Become. Further, in the tap cell region, the third plug P3 is disposed on the second layer wiring M2 (LVSS), and the third layer wiring M3 is disposed on the third plug P3. The third layer wiring M3 serves as the common second ground potential line connected to the second ground potential lines of the tap cells arranged in the X direction (FIG. 24).

  As in the case of the first embodiment, the first plug P1 and the first layer wiring M1 are arranged on the active region AcS on the n-type well (N-well), and via the plug P2. Second layer wiring M2 (LVDD) is arranged. The second layer wiring M2 (LVDD) serves as the power supply potential line described in the section “Memory cell pattern layout”. Further, in the tap cell region, the third plug P3 is disposed on the second layer wiring M2 (LVDD), and the third layer wiring M3 (CVDD) is disposed on the third plug P3. The third layer wiring M3 (CVDD) serves as a common power supply potential line connected to each ground potential line of tap cells arranged in the X direction (see FIGS. 24 and 17).

  In the tap cell region, a common ground potential line (third layer wiring M3 (CVSS)) is connected to a ground potential line (second layer wiring M2 (LVSS)) extending from the memory cell region via a third plug P3. ) Are arranged (FIGS. 24 and 17).

  As described above, in this embodiment, since power is supplied to the p-type well (P-well) through a separate wiring from the ground potential line connected to the memory cell, the fixed potential of the p-type well (P-well). (The back gate potential of the transistor) and the potential of the ground potential line connected to the memory cell can be individually set.

  For example, the potential of the ground potential line connected to the memory cell can be set to about 0.1 V, and the fixed potential of the p-type well (P-well) (back gate potential of the transistor) can be set to 0 V. As described above, by lowering the fixed potential of the p-type well relative to the potential of the ground potential line connected to the memory cell, a back bias effect is generated, and leakage current can be reduced. As described above, by making the ground potential line connected to the memory cell and the power supply wiring of the p-type well (P-well) separate, transistor characteristics can be finely adjusted and device characteristics can be improved. Can do.

  FIG. 25 is a circuit diagram showing the SRAM memory cell of the present embodiment. The configuration and circuit operation of the memory cell are the same as those of the first embodiment. For example, the connection relationship of the transistors is the same as that of the circuit diagram shown in FIGS. The back gate potentials (here, VSSB) of (TND2, TNA1, TND1, TND3, TNA2, and TND4) are different.

  That is, although not explicitly shown in FIG. 5, the back gate potentials of the n-type transistors (TND2, TNA1, TND1, TND3, TNA2, TND4) of the eight transistors are the ground potential (VSS). The back gate potential of the p-type transistors (TP1, TP2) is the power supply potential (VDD). On the other hand, in FIG. 25, the back gate potential of the n-type transistors (TND2, TNA1, TND1, TND3, TNA2, and TND4) is the second ground potential (VSSB). Note that the back gate potential of the p-type transistors (TP1, TP2) is the power supply potential (VDD).

  Although the ground potential line is a separate wiring in this embodiment, the power supply potential line may be a separate wiring.

  For example, the first plug P1 is arranged on the active region AcS on the n-type well (N-well) shown in FIG. 16 in the same manner as in the first embodiment, and the first plug P1 is placed on the first plug P1. Layer wiring M1 is arranged. A second plug P2 is provided on the first layer wiring M1, and the second layer wiring is disposed. The second layer wiring is arranged to be located on the right side of the power supply potential line (LVDD) shown in FIG. 16, and becomes the second power supply potential line (LVDDB). That is, of the two second layer wirings, the left side is a power supply potential line (LVDD) and the right side is a second power supply potential line (LVDDB). Thereafter, the power supply potential line (LVDD) and the second power supply potential line (LVDDB) are respectively connected to individual third layer wirings (a common power supply potential line and a common second power supply potential line) via the third plug P3. The

  According to the above configuration, the back gate potential of the p-type transistors (TP1, TP2) can be set to the second power supply potential (VDDB). For example, by providing a p-type transistor having a relatively high conduction resistance value between the second power supply potential line (LVDDB) and the power supply potential line (power supply potential line (LVDD)) connected to the memory cell, Occurrence of the latch-up phenomenon can be suppressed.

  As described above, the ground potential (VSS) side may have a separate wiring configuration, and the power supply potential (VDD) side may have a separate wiring configuration. Of course, a separate wiring configuration may be applied to both the ground potential (VSS) side and the power supply potential (VDD) side.

(Embodiment 4)
In the memory cell described in the first embodiment, six active regions are arranged in the X direction in the order of AcP2, AcP1, AcN1, AcN2, AcP3, and AcP4 (FIG. 2). The positions of AcP2 and AcP1 Further, the positions of AcP3 and AcP4 may be interchanged (see FIG. 26).

[Configuration of memory cell]
[Memory cell pattern layout]
26 to 28 are plan views showing the configuration of the SRAM memory cell according to the present embodiment. FIG. 26 shows the arrangement of the active region Ac, the gate electrode G, and the first plug P1. FIG. 27 shows the arrangement of the first plug P1, the first layer wiring M1, and the second plug P2. FIG. 28 shows the arrangement of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3. Therefore, in FIG. 26 and FIG. 27, the positional relationship of display patterns in each figure becomes clear by overlapping the plan views with the first plug P1 as a reference. In FIGS. 27 and 28, the plan view is overlapped with the second plug P2 as a reference, so that the positional relationship of display patterns in each figure becomes clear. Note that a rectangular area surrounded by an alternate long and short dash line in the figure indicates a 1 (1 bit) memory cell area.

  As shown in FIG. 26, a p-type well (P-well), an n-type well (N-well), and a p-type well (P-well) are arranged in the X direction on the semiconductor substrate. In FIG. 26, only the memory cell region of 1 (1 bit) is shown, but as described above, the memory cells are repeatedly arranged in the X direction and the Y direction (see FIGS. 12 to 14). The wells (P-well, N-well, P-well) extend in the Y direction. Note that the exposed region of these wells becomes an active region (active region, Ac).

  In addition, six active regions are arranged in the X direction on the semiconductor substrate. Unlike the case of Embodiment 1, in this Embodiment, it arrange | positions in order of AcP1, AcP2, AcN1, AcN2, AcP4, and AcP3.

  Other configurations (G, P1, etc.) are the same as those in the first embodiment, and thus detailed description thereof is omitted. The arrangement of the first plug P1, the first layer wiring M1, the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3 shown in FIGS. 27 and 28 is also shown in FIGS. Since this is almost the same as that of the first embodiment described with reference to FIG.

  As described above, in the present embodiment, in the memory cell region, AcP1 having longer long sides is arranged in the n-type well (N−) with respect to the arrangement of the substantially rectangular active regions AcP1 and AcP2 having long sides in the Y direction. well). In addition, in the memory cell region, with respect to the arrangement of the substantially rectangular active regions AcP4 and AcP3 having long sides in the Y direction, AcP3 having longer long sides is arranged away from the n-type well (N-well). With such an arrangement, the well proximity effect can be reduced.

  The well proximity effect is obtained when, for example, a photoresist film is formed in a region other than the n-type impurity introduction region, and the n-type well is formed by blocking the introduction of the n-type impurity. N-type impurities implanted in the element isolation region STI) diffuse into the gate electrode and source / drain regions of the n-type transistor formed in the p-type well, thereby degrading the characteristics of the n-type transistor. To tell. Similarly, a p-type transistor can be affected by p-type impurities when forming a p-type well. As described above, at the boundary between the n-type well and the p-type well, the transistor characteristics are likely to change due to the well proximity effect, and this problem becomes remarkable due to the miniaturization of the memory cell.

  However, in this embodiment, an active region having a longer long side, in other words, an active region (AcP1 and AcP3) in which more transistors are arranged is divided into an n-type well (N-well) and a p-type well ( By disposing it away from the boundary with P-well), the well proximity effect can be reduced and the transistor characteristics can be improved.

  For reference, eight transistors (TND2, TNA1, TND1, TP1, TP2, TND3, TNA2, TND4) are arranged in correspondence with the above “memory cell pattern layout”, and their connection states are clearly shown. A circuit diagram is shown in FIG.

  As is clear from FIG. 29, the transistors TNA1 and TNA2 are disposed away from the boundary between the n-type well (N-well) and the p-type well (P-well) (see arrows in the figure).

  In this manner, the well proximity effect can be reduced, and transistor characteristics (for example, characteristics of TNA1 and TNA2) can be improved.

  In the present embodiment, in addition to the effects described in detail in the first embodiment, the above effects can be achieved.

(Embodiment 5)
In the memory cell described in the first embodiment, the first plug P1 is provided on the source / drain region and the gate electrode G of each transistor, and the wiring is connected using the wiring above this, but the shared plug (shared contact) is used. ) You may connect using SP1.

  30 to 32 are plan views showing the configuration of the SRAM memory cell according to the present embodiment. FIG. 30 shows an arrangement of the active region Ac, the gate electrode G, the first plug P1, and the shared first plug SP1. FIG. 31 shows the arrangement of the first plug P1, the shared first plug SP1, the first layer wiring M1, and the second plug P2. FIG. 32 shows the arrangement of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3. Therefore, in FIG. 30 and FIG. 31, the positional relationship between the patterns displayed in each figure becomes clear by overlapping the plan views with reference to the first plug P1 and the shared first plug SP1. Further, in FIGS. 31 and 32, the positional relationship of the display pattern in each figure becomes clear by overlapping the plan views with the second plug P2 as a reference. Note that a rectangular area surrounded by an alternate long and short dash line in the figure indicates a 1 (1 bit) memory cell area.

[Memory cell pattern layout]
Regarding the pattern layout of the memory cell of the present embodiment, the configuration other than the portion of the shared first plug SP1 is the same as that of the first embodiment, so detailed description thereof is omitted, and the vicinity of the shared first plug SP1 is omitted. The configuration will be described in detail.

  As shown in FIG. 30, in the present embodiment as well, the p-type well (P-well), the n-type well (N-well), and the p-type well (P-well) are X in the same manner as in the first embodiment. They are arranged side by side. Also, six active regions (AcP2, AcP1, AcN1, AcN2, AcP3, AcP4) are arranged side by side in the X direction. An element isolation region (STI) is formed between these active regions (Ac).

  On the six active regions (AcP2, AcP1, AcN1, AcN2, AcP3, AcP4), a gate electrode G extends across the active regions in the X direction via a gate insulating film (GO). The eight transistors described in the “Circuit Configuration” column of the first embodiment are configured.

  Specifically, a common gate electrode G1 is arranged so as to cross over the active regions AcP2, AcP1, and AcN1. As a result, TND2 is disposed on the active region AcP2, TND1 is disposed on the active region AcP1, and TP1 is disposed on the active region AcN1, and these gate electrodes (G) are connected. On the active region AcP1, another gate electrode G2 is arranged in parallel with the common gate electrode G1. Thereby, TNA1 is arranged on the active region AcP1, and the source / drain region of TNA1 and the source / drain region of TND1 are connected (shared).

  A common gate electrode G3 is arranged so as to cross over the active regions AcP4, AcP3 and AcN2. As a result, TND4 is disposed on the active region AcP4, TND3 is disposed on the active region AcP3, and TP2 is disposed on the active region AcN2, and these gate electrodes (G) are connected. On the active region AcP3, another gate electrode G4 is arranged in parallel with the common gate electrode G3. As a result, TNA2 is disposed on the active region AcP3, and the source / drain region of TNA2 and the source / drain region of TND3 are connected (shared).

  The four gate electrodes G are arranged on the same line two by two. Specifically, the common gate electrode G1 crossing over the active regions AcP2, AcP1 and AcN1 and the gate electrode G4 on the active region AcP3 are arranged on the same line extending in the X direction. The common gate electrode G3 crossing over the active regions AcP4, AcP3 and AcN2 and the gate electrode G2 on the active region AcP1 are arranged on the same line extending in the X direction.

  A first plug P1 is disposed on the source / drain regions of the eight transistors (TND2, TNA1, TND1, TP1, TP2, TND3, TNA2, and TND4). The first plug P1 is also disposed on the four gate electrodes.

  Here, on one source / drain region of TP2 and the common gate electrode G1 of TP1, TND2, and TND1, a shared first plug SP1 that is one continuous plug (integrated plug) is disposed. . A shared first plug SP1 which is one continuous plug is disposed on one source / drain region of TP1 and the common gate electrode G3 of TP2, TND3, and TND4.

  Thus, the source / drain regions to be electrically connected and the gate electrode G may be connected using the shared first plug SP1.

  Thus, by using the shared first plug SP1, the arrangement of the first plugs P1d and P1h shown in FIG. 2 becomes unnecessary, so that the distance between the active regions AcN1 and AcN2 is reduced as shown in FIG. be able to. Therefore, for example, the memory cell area can be reduced as compared with the memory cell of Embodiment 1 (see FIG. 2).

  The layout of the upper layer pattern of the first plug P1 and the shared first plug SP1, that is, the arrangement of the first layer wiring M1, the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3. 31 and 32 are substantially the same as those in the first embodiment described with reference to FIGS. 3 and 4, and thus detailed description thereof is omitted here.

  For reference, eight transistors (TND2, TNA1, TND1, TP1, TP2, TND3, TNA2, TND4) are arranged in correspondence with the above “memory cell pattern layout”, and their connection states are clearly shown. A circuit diagram is shown in FIG.

  In FIG. 33, the location of connection by the shared first plug SP1 corresponds to the location of the circle in the figure, and the source / drain region and the gate using one continuous plug (shared first plug SP1). The electrode G is connected.

  Thus, the memory cell area can be reduced by using the shared first plug SP1.

  In the present embodiment, in addition to the effects described in detail in the first embodiment, the above effects can be achieved.

(Embodiment 6)
In the first embodiment, the length (length in the vertical direction in the figure) of the side extending in the Y direction of the substantially rectangular memory cell region is the length (height) of two transistors to be described later. However, in this embodiment, the length of the side extending in the Y direction of the substantially rectangular memory cell region is the length of four transistors. The length of one transistor means the sum (a1 + b1) of a1 and b1, where the width in the Y direction of the gate electrode is a1 and the distance in the Y direction between the gate electrodes is b1. For example, in the first embodiment, the length of the side extending in the Y direction of the memory cell region is 2 (a1 + b1), which is the length of two transistors (see FIG. 2). In the present embodiment, the length of the side extending in the Y direction of the memory cell region is 4 (a1 + b1).

  In other words, the gate electrodes G are arranged in two stages (two rows) in the first embodiment, but the gate electrodes G are arranged in four stages (four rows) in the present embodiment. To do.

  The circuit configuration and circuit operation of the SRAM memory cell of the present embodiment are the same as those of the first embodiment described with reference to FIG.

[Structure of SRAM]
[Configuration of memory cell]
34 to 36 are plan views showing the structure of the SRAM memory cell according to the present embodiment. FIG. 34 shows the arrangement of the active region A, the gate electrode G, and the first plug P1. FIG. 35 shows the arrangement of the first plug P1, the first layer wiring M1, and the second plug P2. FIG. 36 shows the arrangement of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3. Therefore, in FIG. 34 and FIG. 35, the positional relationship of display patterns in each figure becomes clear by overlapping the plan views with the first plug P1 as a reference. In FIGS. 35 and 36, the positional relationship of display patterns in each figure becomes clear by overlapping the plan views with the second plug P2 as a reference. Note that a rectangular area surrounded by an alternate long and short dash line in the figure indicates a 1 (1 bit) memory cell area.

[Memory cell pattern layout]
[A, G, P1]
As shown in FIG. 34, a p-type well (P-well), an n-type well (N-well), and a p-type well (P-well) are arranged in the X direction on the semiconductor substrate. In FIG. 34, only 1 (1 bit) memory cell region is shown. However, since the memory cells are repeatedly arranged in the X direction and the Y direction (see FIG. 12), these wells (P-well, N- well, P-well) extends in the Y direction. Note that the exposed region of these wells becomes an active region (active region, A).

  In addition, three active regions (AP1, AN, AP2) are arranged in the X direction on the semiconductor substrate. Between these active regions (A) is an element isolation region (STI). In other words, the active region (A) is defined by the element isolation region (STI). The wells (P-well, N-well, P-well) are connected at the lower part of the element isolation region STI.

  Specifically, the active region AP1 is an exposed region of a p-type well (P-well) and has a substantially rectangular shape having a long side in the Y direction. In FIG. 34, only 1 (1 bit) memory cell region is shown for convenience, but the memory cells are repeatedly arranged in the X direction and the Y direction (see FIG. 12). AP1 is continuously arranged with the active region of an adjacent memory cell (here, the memory cell below the memory cell region shown in FIG. 34).

  The active region AN is an exposed region of an n-type well (N-well) and has a substantially rectangular shape having a long side in the Y direction.

  The active region AP2 is an exposed region of a p-type well (P-well) located on the right side of the n-type well in the drawing, and has a substantially rectangular shape having a long side in the Y direction. Note that since the memory cells are repeatedly arranged in the X direction and the Y direction (see FIG. 12), in the memory cell array, the active region AP2 is an adjacent memory cell (here, the memory above the memory cell region shown in FIG. 34). Cell) and the active region.

  On the three active regions (AP1, AN, AP2), a gate electrode G extends across the active regions in the X direction via a gate insulating film (GO). The eight transistors described in the “Circuit Configuration” column are configured.

  Specifically, two common gate electrodes (G1, G3) are arranged so as to cross over the active regions AP1, AN, and AP2. Thus, TND2 and TND3 are arranged in series on the active region AP2, sharing the source / drain region, TND1 and TND4 are arranged in series on the active region AP1, sharing the source / drain region, TP1 and TP2 are arranged in series on the active region AN, sharing the source / drain region. Further, the gate electrodes (G) of TND1, TP1 and TND2 are connected by one common gate electrode G1, and the gate electrodes (G) of TND3, TP2 and TND4 are connected by the other common gate electrode G3. Will be. These two common gate electrodes (G1, G3) are arranged extending in the X direction in parallel.

  Further, on the active region AP1, one gate electrode G2 is arranged in parallel with the two common gate electrodes G. Thereby, TNA1 is arranged on the active region AP1, and the source / drain region of TNA1 and the source / drain region of TND1 are connected (shared). On the active region AP2, another gate electrode G4 is arranged in parallel with the two common gate electrodes (G1, G3). Thereby, TNA2 is arranged on the active region AP2, and the source / drain region of TNA2 and the source / drain region of TND3 are connected (shared).

  Thus, in the present embodiment, the driver transistors are divided (TND1 and TND2, TND3 and TND4) and arranged on different active regions (AP1, AP2). Furthermore, by extending these active regions (AP1, AP2) in the Y direction, a simple layout is obtained and the processing accuracy is improved.

  Therefore, as in the first embodiment, the gate width of the access transistor and the gate width of the driver transistor are easily set to 1: 2 without providing a corner (bent portion) in the shape of the active region (A). Can do.

  In addition, since three transistors are arranged in each of the active regions (AP1, AP2), the number of active regions can be reduced. As a result, a simple layout can be realized, and the memory cell area can be reduced.

  Further, by extending the active region (A) in the Y direction, the gate electrode (G) can be extended in the X direction, and not only the processing accuracy of the active region (A) but also the gate electrode (G). The machining accuracy can be improved. In particular, as described in detail in the first embodiment, the multiple exposure technique can be easily adopted, and the processing accuracy can be improved. Moreover, simulation model creation becomes easy and the verification accuracy can be improved.

[P1, M1, P2]
As shown in FIG. 35, the first plug P1 is formed on the source / drain regions of the eight transistors (TND2, TNA1, TND1, TP1, TP2, TND3, TNA2, TND4) described with reference to FIG. Be placed. Further, the first plug P1 is also disposed on the four gate electrodes described with reference to FIG.

  A first layer wiring M1 is disposed on the first plug P1, and electrical connection between the first plugs P1 is achieved.

  Specifically, the first plug P1A on one source / drain region of TND2, the first plug P1B on the common source / drain region of TND1 and TNA1, and the first plug P1C on one source / drain region of TP1. , And a first plug P1D on a common gate electrode (G3) of TP2, TND3, and TND4 is connected by a first layer wiring (first node wiring) M1A. The first layer wiring M1A can be associated with the storage node A of FIG. The above “one” means the lower source / drain region in the drawing.

  A first plug P1E on one source / drain region of TND4, a first plug P1F on a common source / drain region of TND3 and TNA2, a first plug P1G on one source / drain region of TP2, and TP1; The first plug P1H on the gate electrode (G1) common to TND1 and TND2 is connected by the first layer wiring M1B. The first layer wiring (second node wiring) M1B can be associated with the storage node B of FIG. Here, “one” means the upper source / drain region in the drawing.

  A first layer wiring (pad region) M1S is disposed on the first plug P1I on the other source / drain region of TND2. Further, the first layer wiring M1S is arranged on the first plug P1J on the other source / drain region of the TND1.

  A first layer wiring (pad region) M1D is disposed on the first plug P1K on the common source / drain region of TP1 and TP2. The first layer wiring M1D can be associated with the power supply potential (VDD) in FIG. 1, and is connected to the power supply potential line (LVDD) as will be described later.

  Further, the first layer wiring M1BL is disposed on the first plug P1L on the other source / drain region of the TNA1 and the first plug P1M on the other source / drain region of the TNA2.

  Further, the first layer wiring M1W is disposed on the first plug P1N on the gate electrode (G2) of the TNA1 and the first plug P1O on the gate electrode (G4) of the TNA2.

  The connection state by the first layer wiring M1 between the plurality of first plugs P1 can be variously modified as long as the connection state of the circuit diagram shown in FIG. 1 is satisfied.

[P2, M2, P3, M3]
As shown in FIG. 36, of the first layer wiring M1 described with reference to FIG. 35, the first layer other than the first layer wiring M1 (M1A, M1B) corresponding to the storage node (A or B). A second plug P2 is disposed on the wiring M1, and a second layer wiring M2 is disposed on the second plug P2.

  Specifically, the first layer wiring M1W connected to the gate electrode (G2) of TNA1 is connected to the second layer wiring M2W via the second plug P2. The first layer wiring M1W connected to the gate electrode (G4) of TNA2 is connected to the second layer wiring M2W through the second plug P2. These two second layer wirings M2W are arranged so as to extend in the Y direction at both ends in the X direction of the memory cell region. Further, a third plug P3 is disposed on the two second layer wirings M2W, and a third layer wiring M3 (WL) is disposed in the X direction so as to connect the two third plugs P3. . The third layer wiring M3 (WL) is a word line.

  The first layer wiring (pad region) M1S connected to the common source / drain region (P1I) of TND2 and TND3 is connected to the second layer wiring M2 (LVSS) through the second plug P2. The second layer wiring M2 (LVSS) is a ground potential line. The first layer wiring (pad region) M1S connected to the common source / drain region (P1J) of TND1 and TND4 is connected to the second layer wiring M2 (LVSS) via the second plug P2. The second layer wiring M2 (LVSS) is a ground potential line. These two ground potential lines are arranged so as to extend in the Y direction inside the two second layer wirings M2 arranged at both ends of the memory cell region described above.

  Further, the first layer wiring M1BL connected to the other source / drain region of the TNA1 is connected to the second layer wiring M2 (BL) through the second plug P2. This second layer wiring M2 (BL) is one bit line of the bit line pair. The first layer wiring M1BL connected to the other source / drain region of TNA2 is connected to the second layer wiring M2 (/ BL) via the second plug P2. This second layer wiring M2 (/ BL) is another bit line. These two bit lines (BL, / BL) are arranged so as to extend in the Y direction, respectively, inside the above-described two ground potential lines (LVSS).

  The first layer wiring (pad region) M1D connected to the common source / drain region (P1K) of TP1 and TP2 is connected to the second layer wiring M2 (LVDD) via the second plug. The second layer wiring M2 (LVDD) is a power supply potential line.

  The connection state of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3 can be variously modified as long as the connection state of the circuit diagram shown in FIG. 1 is satisfied. As described above, a simple layout can be realized by extending the second layer wiring M2 mainly in the Y direction and extending the third layer wiring M3 mainly in the X direction. 34 to 36, only 1 (1 bit) memory cell region is shown for convenience. However, as will be described later, the memory cells are repeatedly arranged in the X direction and the Y direction. The ground potential lines (LVSS), bit lines (BL, / BL), and power supply potential lines (LVDD) extend in the Y direction, and the word lines (WL) extend in the X direction.

  In the present embodiment, since the ground potential line (LVSS) is arranged between the second layer wiring M2W (second layer wiring connected to the word line) and the bit lines (BL, / BL). The shielding effect of the ground potential line (LVSS) is generated, and the interaction (crosstalk noise) between the second layer wiring M2W (second layer wiring connected to the word line) and the bit lines (BL, / BL) is reduced. can do.

  Each pattern described with reference to FIGS. 34 to 36 is arranged point-symmetrically with respect to the center point of the memory cell region.

  For reference, eight transistors (TND2, TNA1, TND1, TP1, TP2, TND3, TNA2, TND4) are arranged in correspondence with the above “memory cell pattern layout”, and their connection states are clearly shown. A circuit diagram is shown in FIG.

[Configuration of memory cell array]
The SRAM memory cell array of the present embodiment is arranged in an array as in the first embodiment. That is, as described with reference to FIG. 12 in the first embodiment, the memory cell region (“F”) is repeatedly arranged in line symmetry with respect to the line extending in the X direction, and also in the Y direction. Are repeatedly arranged symmetrically with respect to the line extending to the line.

[Description of tap cell area]
In the SRAM memory cell array of the present embodiment, a tap cell region is provided as in the first embodiment. A predetermined potential (for example, ground potential VSS or power supply potential VDD) is supplied to each well through the tap cell region.

(Embodiment 7)
In the sixth embodiment, a p-type well (P-well), an n-type well (N-well) and a p-type well (P-well) are arranged in the X direction (FIG. 34). The p-type wells (P-wells) on both sides of (N-well) may be arranged together on one side (FIG. 38).

  In the present embodiment, as in the sixth embodiment, the length of the side extending in the Y direction of the substantially rectangular memory cell region is the length of four transistors. In other words, in this embodiment, the gate electrodes G are arranged in four stages (four rows).

  The circuit configuration and circuit operation of the SRAM memory cell of the present embodiment are the same as those of the first embodiment described with reference to FIG.

[Structure of SRAM]
[Configuration of memory cell]
38 to 40 are plan views showing configurations of the SRAM memory cells according to the present embodiment. FIG. 38 shows the arrangement of the active region A, the gate electrode G, and the first plug P1. FIG. 39 shows the arrangement of the first plug P1, the first layer wiring M1, and the second plug P2. FIG. 40 shows the arrangement of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3. Therefore, in FIG. 38 and FIG. 39, the positional relationship of display patterns in each figure becomes clear by overlapping the plan views with the first plug P1 as a reference. Also, in FIGS. 39 and 40, the positional relationship of the display patterns in each figure becomes clear by overlapping the plan views with the second plug P2 as a reference. Note that a rectangular area surrounded by an alternate long and short dash line in the figure indicates a 1 (1 bit) memory cell area.

[Memory cell pattern layout]
[A, G, P1]
As shown in FIG. 38, an n-type well (N-well) and a p-type well (P-well) are arranged in the X direction on the semiconductor substrate. In FIG. 38, only 1 (1 bit) memory cell region is shown. However, since the memory cells are repeatedly arranged in the X direction and the Y direction (see FIG. 12), both wells (N-well, P- well) extends in the Y direction. Note that the exposed region of these wells becomes an active region (active region, A).

  Further, three active regions (AN, AP1, AP2) are arranged side by side in the X direction on the semiconductor substrate. Between these active regions (A) is an element isolation region (STI). In other words, the active region (A) is defined by the element isolation region (STI). The wells (N-well, P-well) are connected at the lower part of the element isolation region STI.

  Specifically, the active region AN is an exposed region of an n-type well (N-well) and has a substantially rectangular shape having a long side in the Y direction.

  The active region AP1 is an exposed region of a p-type well (P-well) located on the right side of the n-type well in the drawing, and has a substantially rectangular shape having a long side in the Y direction. In FIG. 38, only 1 (1 bit) memory cell region is shown for convenience. However, since the memory cells are repeatedly arranged in the X direction and the Y direction, the active region AP1 is arranged in the Y direction in the memory cell array. It will extend in a line shape.

  The active region AP2 is an exposed region of the p-type well (P-well), is disposed next to the active region AP1, and has a substantially rectangular shape having a long side in the Y direction.

  On the three active regions (AN, Ap1, AP2), a gate electrode G extends across the active regions in the X direction via a gate insulating film (GO). The eight transistors described in the “Circuit Configuration” column are configured.

  Specifically, two common gate electrodes (G1, G3) are arranged so as to cross over the active regions AN, AP1, and AP2. Thereby, TND2 and TND4 are arranged in series on the active region AP2, sharing the source / drain region, TND1 and TND3 are arranged in series on the active region AP1, sharing the source / drain region, and TP1 and TP2 are arranged in series on the active region AN, sharing the source / drain region. In addition, the gate electrodes (G) of TP1, TND1, and TND2 are connected by one common gate electrode G1, and the gate electrodes (G) of TP2, TND3, and TND4 are connected by the other common gate electrode G3. Will be. These two common gate electrodes G are arranged extending in the X direction in parallel.

  On the active region AP1, one gate electrode G2 is arranged in parallel with the two common gate electrodes (G1, G3). Thereby, TNA1 is arranged on the active region AP1, and the source / drain region of TNA1 and the source / drain region of TND1 are connected (shared). On the active region AP1, another gate electrode G4 is arranged in parallel with the two common gate electrodes G. Thereby, TNA2 is arranged on the active region AP1, and the source / drain region of TNA2 and the source / drain region of TND3 are connected (shared).

  Thus, in the present embodiment, the driver transistors are divided (TND1 and TND2, TND3 and TND4) and arranged on different active regions (AP1, AP2). Furthermore, by extending these active regions (AP1, AP2) in the Y direction, a simple layout is obtained and the processing accuracy is improved.

  Therefore, as in the first embodiment, the gate width of the access transistor and the gate width of the driver transistor are easily set to 1: 2 without providing a corner (bent portion) in the shape of the active region (A). Can do.

  In addition, since the access transistors (TNA1, TNA2) are also arranged in the active region (AP1), the number of active regions can be reduced. Although the access transistors (TNA1, TNA2) are also arranged in the active region (AP1) here, one access transistor may be arranged in each of the two active regions AP1 and AP2. In this manner, the remaining n-type transistors may be appropriately disposed in the active region (here, AP1 and AP2) where the driver transistors are divided and disposed. Thereby, the number of active regions can be reduced. As a result, a simple layout can be realized and the memory cell area can be reduced.

  Further, by extending the active region (A) in the Y direction, the gate electrode (G) can be extended in the X direction, and not only the processing accuracy of the active region (A) but also the gate electrode (G). The machining accuracy can be improved. In particular, as described in detail in the first embodiment, the multiple exposure technique can be easily adopted, and the processing accuracy can be improved. Moreover, simulation model creation becomes easy and the verification accuracy can be improved.

[P1, M1, P2]
As shown in FIG. 39, the first plug P1 is formed on the source / drain regions of the eight transistors (TND2, TNA1, TND1, TP1, TP2, TND3, TNA2, TND4) described with reference to FIG. Be placed. Further, the first plug P1 is also disposed on the four gate electrodes described with reference to FIG.

  A first layer wiring M1 is disposed on the first plug P1, and electrical connection between the first plugs P1 is achieved.

  Specifically, the first plug P1A on one source / drain region of TND2, the first plug P1B on the common source / drain region of TND1 and TNA1, and the first plug P1C on one source / drain region of TP1. , And the first plug P1D on the common gate electrode (G3) of TP2, TND3, and TND4 is connected by the first layer wiring M1A. The first layer wiring (first node wiring) M1A can be associated with the storage node A of FIG. The above “one” means the lower source / drain region in the drawing.

  A first plug P1E on one source / drain region of TND4, a first plug P1F on a common source / drain region of TND3 and TNA2, a first plug P1G on one source / drain region of TP2, and TP1; The first plug P1H on the common gate electrode (G1) of TND1 and TND2 is connected by the first layer wiring (second node wiring) M1B. The first layer wiring M1B can be associated with the storage node B of FIG. Here, “one” means the upper source / drain region in the drawing.

  The first plug P1P on the common source / drain region of TND2 and TND4 and the first plug P1Q on the common source / drain region of TND1 and TND3 are connected by the first layer wiring M1S. The first layer wiring M1S can be associated with the ground potential (VSS) in FIG. 1, and is connected to the ground potential line (LVSS) as described later.

  The first layer wiring M1D is disposed on the first plug P1R on the common source / drain region of TP1 and TP2. The first layer wiring M1D can be associated with the power supply potential (VDD) in FIG. 1, and is connected to the power supply potential line (LVDD) as will be described later.

  Further, the first layer wiring M1BL is disposed on the first plug P1S on the other source / drain region of the TNA1 and the first plug P1T on the other source / drain region of the TNA2. The first plug P1U on the gate electrode (G2) of TNA1 and the first plug P1V on the gate electrode (G4) of TNA2 are connected by the first layer wiring M1W.

  The connection state by the first layer wiring M1 between the plurality of first plugs P1 can be variously modified as long as the connection state of the circuit diagram shown in FIG. 1 is satisfied.

[P2, M2, P3, M3]
As shown in FIG. 40, of the first layer wiring M1 described with reference to FIG. 39, the first layer other than the first layer wiring M1 (M1A, M1B) corresponding to the storage node (A or B). A second plug P2 is disposed on the wiring M1, and a second layer wiring M2 is disposed on the second plug P2.

  Specifically, the first layer wiring M1W connected to the gate electrode (G2) of TNA1 and the gate electrode (G4) of TNA2 is connected to the second layer wiring M2W via the second plug P2. The second layer wiring M2W is arranged to extend in the Y direction at the end of the memory cell region in the X direction. Further, a third plug P3 is disposed on the second layer wiring M2, and a third layer wiring M3 (WL) extending in the X direction is disposed on the third plug P3. The third layer wiring M3 (WL) is a word line.

  The first layer wiring M1BL connected to the other source / drain region (P1S) of the TNA1 is connected to the second layer wiring M2 (BL) via the second plug P2. This second layer wiring M2 (BL) is one bit line of the bit line pair.

  The first layer wiring M1BL connected to the other source / drain region (P1T) of TNA2 is connected to the second layer wiring M2 (/ BL) via the second plug P2. This second layer wiring M2 (/ BL) is another bit line. These two bit lines (BL, / BL) are arranged so as to extend in the Y direction, respectively.

  The first layer wiring M1S connected to the common source / drain region (P1P) of TND2 and TND4 and the common source / drain region (P1Q) of TND1 and TND3 is connected to the second layer via the second plug P2. It is connected to the wiring M2 (LVSS). The second layer wiring M2 (LVSS) is a ground potential line. This ground potential line is arranged between the two bit lines (BL, / BL) so as to extend in the Y direction.

  The first layer wiring M1D connected to the common source / drain region (P1R) of TP1 and TP2 is connected to the second layer wiring M2 (LVDD) through the second plug. The second layer wiring M2 (LVDD) is a power supply potential line.

  The connection state of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3 can be variously modified as long as the connection state of the circuit diagram shown in FIG. 1 is satisfied. As described above, a simple layout can be realized by extending the second layer wiring M2 mainly in the Y direction and extending the third layer wiring M3 mainly in the X direction. 34 to 36, only 1 (1 bit) memory cell region is shown for convenience. However, as will be described later, the memory cells are repeatedly arranged in the X direction and the Y direction. The ground potential lines (LVSS), bit lines (BL, / BL), and power supply potential lines (LVDD) extend in the Y direction, and the word lines (WL) extend in the X direction.

  In this embodiment, since the ground potential line (LVSS) is arranged between the bit lines (BL, / BL), the shielding effect of the ground potential line (LVSS) is generated, and the bit lines (BL, / BL) are generated. BL) can be reduced (crosstalk noise).

  Further, in the present embodiment, since the p-type well (P-well) is arranged on one side of the n-type well (N-well) in the memory cell region, it is compared with the case of the sixth embodiment (FIG. 34). In addition, the boundary region between the n-type well (N-well) and the p-type well (P-well) is reduced, and the above-described well proximity effect can be reduced.

  For reference, eight transistors (TND2, TNA1, TND1, TP1, TP2, TND3, TNA2, TND4) are arranged in correspondence with the above “memory cell pattern layout”, and their connection states are clearly shown. A circuit diagram is shown in FIG.

[Configuration of memory cell array]
The SRAM memory cell array of the present embodiment is arranged in an array as in the first embodiment. That is, as described with reference to FIG. 12 in the first embodiment, the memory cell region (“F”) is repeatedly arranged in line symmetry with respect to the line extending in the X direction, and also in the Y direction. Are repeatedly arranged symmetrically with respect to the line extending to the line.

[Description of tap cell area]
In the SRAM memory cell array of the present embodiment, a tap cell region is provided as in the first embodiment. A predetermined potential (for example, ground potential VSS or power supply potential VDD) is supplied to each well through the tap cell region.

  The SRAM memory cell array of the present embodiment has a tap cell (F ′) as in the first embodiment (FIG. 15). The tap cells (F ′) are arranged for every n memory cell regions arranged in the Y direction, and are repeatedly arranged in the X direction in line symmetry with respect to a line extending in the Y direction. In FIG. 15, one tap cell among a plurality of tap cells arranged in the X direction is indicated by “F ′”.

  42 and 43 are plan views showing the configuration of the SRAM tap cell (F ') of the present embodiment. FIG. 42 shows the arrangement of the active region AcS, the dummy gate electrode DG, the first plug P1, the first layer wiring M1, and the second plug P2. FIG. 43 shows the arrangement of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3. Therefore, in FIG. 42 and FIG. 43, the positional relationship of display patterns in each figure becomes clear by overlapping the plan views with the second plug P2 as a reference. In addition, the rectangular area | region enclosed with the dashed-dotted line in the figure shows one tap cell area | region, for example, is set to the same magnitude | size as a memory cell area | region.

  In the memory cell region, each well (N-well, P-well) extending in the Y direction also extends in the Y direction in the tap cell shown in FIG. 42, and the n-type well (N-well) and p-well Mold wells (P-wells) are arranged side by side in the X direction.

  An active region AcS for power supply is provided on the tap cell region, and two active regions AcS are arranged side by side in the X direction. An element isolation region (STI) is formed between these active regions (AcS).

  Specifically, each active region AcS is an exposed region of each well (P-well, N-well), and is here formed in a substantially rectangular shape having a long side in the X direction. The two active regions AcS are arranged on the same line extending in the X direction.

  A first plug P1 is disposed on the active region AcS on the p-type well (P-well) on the left side of the drawing, and a first layer wiring M1 is disposed on the first plug P1. A second plug P2 is disposed on the first layer wiring M1. A second layer wiring M2 (LVSS) is arranged on the second plug P2. The second layer wiring M2 (LVSS) serves as the ground potential line described in the section “Memory cell pattern layout”. Further, in the tap cell region, the third plug P3 is disposed on the second layer wiring M2 (LVSS), and the third layer wiring M3 (CVSS) is disposed thereon. The third layer wiring M3 (CVSS) serves as a common ground potential line connected to each ground potential line of the tap cells arranged in the X direction (FIG. 43).

  A first plug P1 is disposed on the active region AcS on the left n-type well (N-well) in the drawing, and a first layer wiring M1 is disposed on the first plug P1. A second plug P2 is disposed on the first layer wiring M1. A second layer wiring M2 (LVDD) is arranged on the second plug P2. The second layer wiring M2 (LVDD) serves as the power supply potential line described in the section “Memory cell pattern layout”. Further, in the tap cell region, the third plug P3 is disposed on the second layer wiring M2 (LVDD), and the third layer wiring M3 (CVDD) is disposed on the third plug P3. The third layer wiring M3 (CVDD) serves as a common power supply potential line connected to each ground potential line of the tap cells arranged in the X direction (FIG. 43).

  Note that the bit lines (second-layer wiring M2 (BL), second-layer wiring M2 (/ BL)) described in the section of “pattern layout of memory cell” extend on the tap cell region ( FIG. 43).

  Further, as shown in FIG. 42, in the tap cell region, a dummy gate electrode DG extending in the X direction is arranged on the element isolation region STI. Thus, by providing the dummy gate electrode DG, the unevenness due to the gate electrode is regularly repeated, and the regularity of the layout is improved. As a result, manufacturing variations and the like can be reduced, and device characteristics can be improved.

(Embodiment 8)
In the memory cell described in the seventh embodiment, three active regions are arranged in the X direction in the order of AN, AP1, and AP2 (FIG. 38), but the positions of AP1 and AP2 may be interchanged ( (See FIG. 44).

[Configuration of memory cell]
[Memory cell pattern layout]
44 to 46 are plan views showing the configuration of the SRAM memory cell according to the present embodiment. FIG. 44 shows the arrangement of the active region (A), the gate electrode G, and the first plug P1. FIG. 45 shows an arrangement of the first plug P1, the first layer wiring M1, and the second plug P2. FIG. 46 shows the arrangement of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3. Therefore, in FIG. 44 and FIG. 45, the positional relationship of display patterns in each figure becomes clear by overlapping the plan views with the first plug P1 as a reference. 45 and 46, the positional relationship of the display patterns in each figure becomes clear by overlapping the plan views with the second plug P2 as a reference. Note that a rectangular area surrounded by an alternate long and short dash line in the figure indicates a 1 (1 bit) memory cell area.

  As shown in FIG. 44, an n-type well (N-well) and a p-type well (P-well) are arranged in the X direction on the semiconductor substrate. In FIG. 44, only the memory cell region of 1 (1 bit) is shown. However, as described above, since the memory cells are repeatedly arranged in the X direction and the Y direction (see FIG. 12), these wells (N -Well, P-well) will extend in the Y direction. Note that the exposed region of these wells becomes an active region (active region, A).

  In addition, three active regions are arranged in the X direction on the semiconductor substrate. Unlike the case of the seventh embodiment, in this embodiment, the AN, AP2, and AP1 are arranged in this order.

  Other configurations (G, P1, etc.) are the same as those in the seventh embodiment, and thus detailed description thereof is omitted. The arrangement of the first plug P1, the first layer wiring M1, the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3 shown in FIGS. 45 and 46 is also shown in FIGS. Since this is almost the same as that of the first embodiment described with reference to FIG.

  Thus, in the present embodiment, in the memory cell region, the active region AP1 extending in a line shape in the Y direction is separated from the boundary between the n-type well (N-well) and the p-type well (P-well). It is placed away. In other words, the active region in which more transistors are disposed is disposed away from the boundary. As a result, the distance between the boundary between the n-type well (N-well) and the p-type well (P-well) and the active region AP1 is increased, and the above-described well proximity effect can be reduced. As a result, transistor characteristics can be improved.

  For reference, eight transistors (TND2, TNA1, TND1, TP1, TP2, TND3, TNA2, TND4) are arranged in correspondence with the above “memory cell pattern layout”, and their connection states are clearly shown. A circuit diagram is shown in FIG.

  As is clear from FIG. 47, the transistors TNA1 and TNA2 are arranged away from the boundary between the n-type well (N-well) and the p-type well (P-well) (see the arrow in the figure).

  In this manner, the well proximity effect can be reduced, and transistor characteristics (for example, characteristics of TNA1 and TNA2) can be improved.

  In the present embodiment, in addition to the effects described in detail in the first embodiment, the above effects can be achieved.

(Embodiment 9)
In the first embodiment, a so-called single-port SRAM (FIG. 1) has been described as an example. In the present embodiment, a so-called dual-port SRAM (FIG. 48) is used. An application example will be described.

[Circuit configuration]
FIG. 48 is an equivalent circuit diagram showing the SRAM memory cell of the present embodiment. Unlike the equivalent circuit diagram (FIG. 1) described in the first embodiment, it has two bit line pairs (BLA and / BLA, BLB and / BLB) and two word lines (WLA and WLB).

  As shown in FIG. 48, the memory cell is arranged at the intersection of the two pairs of bit lines and the two word lines WL. This memory cell includes a pair of load transistors (load MOS, load transistor, load MISFET) TP1, TP2, two pairs of access transistors (access MOS, access transistor, access MISFET, transfer transistor) TNA1, TNA3, TNA2. And TNA4, and a pair of driver transistors (driver MOS, driving MISFET) TND2, TND4.

  In this embodiment, the driver transistor TND1 connected in parallel with the driver transistor (driving MISFET) TND2 is provided. The driver transistor TND3 is connected in parallel with the driver transistor (driving MISFET) TND4.

  Among the transistors constituting the memory cell, the load transistor is a p-type (p-channel type) transistor, and the access transistor and the driver transistor are n-type (n-channel type) transistors.

  Of the eight transistors constituting the memory cell, TND2 and TP1 constitute a CMOS inverter, and TND4 and TP2 constitute another CMOS inverter. The mutual input / output terminals (storage nodes A and B) of the pair of CMOS inverters are cross-coupled to form a flip-flop circuit as an information storage unit for storing 1-bit information.

  Here, in the SRAM memory cell of the present embodiment, since TND1 is provided in parallel with TND2, and TND3 is provided in parallel with TND4, a CMOS inverter is configured by TND1, TND2, and TP1, and TND3, It can also be seen that another CMOS inverter is configured with TND4 and TP2.

  Therefore, the connection relationship of the 10 transistors constituting the SRAM memory cell of the present embodiment will be described in detail as follows.

  TP1 is connected between the power supply potential (first potential) and the storage node A, and TND1 and TND2 are connected in parallel between the storage node A and the ground potential (reference potential, second potential lower than the first potential). The gate electrodes of TP1, TND1, and TND2 are connected to storage node B.

  TP2 is connected between the power supply potential (first potential) and the storage node B, and TND3 and TND4 are connected in parallel between the storage node B and the ground potential (reference potential, second potential lower than the first potential). The gate electrodes of TP2, TND3, and TND4 are connected to storage node A.

  TNA1 is connected between bit line BLA and storage node A, TNA3 is connected between bit line / BLA and storage node B, and the gate electrodes of TNA1 and TNA3 are connected to word line WLA (word Line).

  TNA2 is connected between bit line BLB and storage node A, TNA4 is connected between bit line / BLB and storage node B, and the gate electrodes of TNA2 and TNA4 are connected to word line WLB. (It becomes a word line).

  As described above, in the SRAM memory cell of the present embodiment, the driver transistors are divided (TND1 and TND2, TND3 and TND4).

  As described above, dual-port SRAM has two signal ports for data input / output, so that even if data is read from one port, the other is simultaneously Data can be written from these ports, and data processing can be performed at high speed.

[Structure of SRAM]
[Configuration of memory cell]
49 to 51 are plan views showing the configuration of the SRAM memory cell according to the present embodiment. FIG. 49 shows the arrangement of the active region Ac, the gate electrode G, and the first plug P1. FIG. 50 shows the arrangement of the first plug P1, the first layer wiring M1, and the second plug P2. FIG. 51 shows the arrangement of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3. Therefore, in FIG. 49 and FIG. 50, the positional relationship of the display patterns in each figure becomes clear by overlapping the plan views with the first plug P1 as a reference. 50 and 51, the positional relationship of the display patterns in each figure becomes clear by overlapping the plan views with reference to the second plug P2. Note that a rectangular area surrounded by an alternate long and short dash line in the figure indicates a 1 (1 bit) memory cell area.

[Memory cell pattern layout]
[Ac, G, P1]
As shown in FIG. 49, a p-type well (P-well), an n-type well (N-well), and a p-type well (P-well) are arranged in the X direction on the semiconductor substrate. In FIG. 49, only the memory cell region of 1 (1 bit) is shown. However, since the memory cells are repeatedly arranged in the X direction and the Y direction (see FIG. 12), these wells (P -Well, N-well, P-well) will extend in the Y direction. Note that the exposed region of these wells becomes an active region (active region, Ac).

  In addition, six active regions (AcP2, AcP1, AcN1, AcN2, AcP3, AcP4) are arranged in the X direction on the semiconductor substrate. An element isolation region (STI) is formed between these active regions (Ac). In other words, the active region (Ac) is defined by the element isolation region (STI). The wells (P-well, N-well, P-well) are connected at the lower part of the element isolation region STI.

  Specifically, the active region AcP2 is an exposed region of a p-type well (P-well) and has a substantially rectangular shape having a long side in the Y direction. The active region AcP1 is disposed next to the active region AcP2, is an exposed region of a p-type well (P-well), and has a substantially rectangular shape having a long side in the Y direction. In FIG. 49, only 1 (1 bit) memory cell region is shown for convenience. However, since the memory cells are repeatedly arranged in the X direction and the Y direction, the active regions AcP1 and AcP2 are It extends in a line shape in the Y direction.

  The active region AcN1 is an exposed region of an n-type well (N-well) and has a substantially rectangular shape having a long side in the Y direction. The active region AcN2 is an exposed region of an n-type well (N-well) and has a substantially rectangular shape having a long side in the Y direction.

  The active region AcP3 is an exposed region of a p-type well (P-well) located on the right side of the n-type well in the drawing, and has a substantially rectangular shape having a long side in the Y direction. The active region AcP4 is disposed next to the active region AcP3, is an exposed region of the p-type well (P-well), and has a substantially rectangular shape having a long side in the Y direction. In the memory cell array, the active regions AcP3 and AcP4 extend in a line shape in the Y direction.

  On the six active regions (AcP2, AcP1, AcN1, AcN2, AcP3, AcP4), a gate electrode G extends across the active regions in the X direction via a gate insulating film (GO). The ten transistors described in the above “Circuit Configuration” column are configured.

  Specifically, a common gate electrode G1 is arranged so as to cross over the active regions AcP2, AcP1, and AcN1. As a result, TND2 is disposed on the active region AcP2, TND1 is disposed on the active region AcP1, and TP1 is disposed on the active region AcN1, and these gate electrodes (G) are connected. On the active region AcP1, a gate electrode G2b is arranged in parallel with the common gate electrode G1. Thereby, TNA1 is arranged on the active region AcP1, and the source / drain region of TNA1 and the source / drain region of TND1 are connected (shared). A gate electrode G2a is disposed on the active region AcP2 in parallel with the common gate electrode G1. As a result, TNA2 is arranged on active region AcP2, and the source / drain region of TNA2 and the source / drain region of TND2 are connected (shared).

  A common gate electrode G3 is arranged so as to cross over the active regions AcP4, AcP3 and AcN2. Thereby, TND3 is disposed on the active region AcP4, TND4 is disposed on the active region AcP3, and TP2 is disposed on the active region AcN2, and these gate electrodes (G) are connected. On the active region AcP3, a gate electrode G4b is arranged in parallel with the common gate electrode G3. As a result, the TNA 4 is arranged on the active region AcP3, and the source / drain region of the TNA 4 and the source / drain region of the TND 4 are connected (shared). A gate electrode G4a is disposed on the active region AcP4 in parallel with the common gate electrode G3. As a result, the TNA 3 is arranged on the active region AcP4, and the source / drain region of the TNA 3 and the source / drain region of the TND 3 are connected (shared).

  The six gate electrodes G are arranged on the same line three by three. Specifically, the common gate electrode G1 crossing over the active regions AcP2, AcP1, and AcN1, the gate electrode G4b on the active region AcP3, and the gate electrode G4a on the active region AcP4 are on the same line extending in the X direction. Is arranged. The common gate electrode G3 crossing over the active regions AcP4, AcP3 and AcN2, the gate electrode G2b on the active region AcP1, and the gate electrode G2a on the active region AcP2 are arranged on the same line extending in the X direction. .

  As described above, in this embodiment, the driver transistors are divided (TND1 and TND2, TND3 and TND4), and arranged on different active regions (AcP2 and AcP1, AcP4 and AcP3). Furthermore, by extending these active regions (AcP2 and AcP1, AcP4 and AcP3) in the Y direction, a simple layout is obtained and the processing accuracy is improved.

  Therefore, as in the first embodiment, the gate width of the access transistor and the gate width of the driver transistor are easily set to 1: 2 without providing a corner (bent portion) in the shape of the active region (Ac). Can do.

  In addition, since the access transistors (TNA1, TNA2, TNA3, TNA4) are arranged in the active regions (AcP2, AcP1, AcP4, AcP3), the number of active regions can be reduced. As a result, a simple layout can be realized, and the memory cell area can be reduced.

  Further, by extending the active region (Ac) in the Y direction, the gate electrode (G) can be extended in the X direction, and not only the processing accuracy of the active region (Ac) but also the gate electrode (G). The machining accuracy can be improved. In particular, as described in detail in the first embodiment, the multiple exposure technique can be easily adopted, and the processing accuracy can be improved. Moreover, simulation model creation becomes easy and the verification accuracy can be improved.

[P1, M1, P2]
As shown in FIG. 50, the ten transistors (TND2, TNA2, TNA1, TND1, TP1, TP2, TND4, TNA4, TND3, TNA3) described with reference to FIG. One plug P1 is arranged. The first plug P1 is also disposed on the six gate electrodes described with reference to FIG.

  A first layer wiring M1 is disposed on the first plug P1, and electrical connection between the first plugs P1 is achieved.

  Specifically, the first plug P1a on the common source / drain region of TND2 and TNA2, the first plug P1b on the common source / drain region of TND1 and TNA1, and the first plug on one of the source / drain regions of TP1. The plug P1c and the first plug P1d on the common gate electrode G3 of TP2, TND3, and TND4 are connected by the first layer wiring (first node wiring) M1A. The first layer wiring M1A can be associated with the storage node A of FIG. The above "one" indicates the upper source / drain region in the drawing.

  A first plug P1e on the common source / drain region of TND3 and TNA3, a first plug P1f on the common source / drain region of TND4 and TNA4, a first plug P1g on one of the source / drain regions of TP2, and The first plug P1h on the common gate electrode G of TP1, TND1, and TND2 is connected by the first layer wiring M1B. The first layer wiring M1B can be associated with the storage node B of FIG. The first layer wiring M1 (M1A, M1B) corresponding to the storage node (A or B) is arranged so as to extend mainly in the X direction. Here, “one” means the lower source / drain region in the figure.

  The first plug P1j on the other source / drain region of TND2 and the first plug P1i on the other source / drain region of TND1 are connected by the first layer wiring M1S. The first layer wiring M1S can be associated with the ground potential (VSS) of FIG. 48 and is connected to the ground potential line (LVSS) as will be described later.

  The first plug P1k on the other source / drain region of TND3 and the first plug P1m on the other source / drain region of TND4 are connected by the first layer wiring M1S. The first layer wiring M1S can be associated with the ground potential (VSS) of FIG. 48 and is connected to the ground potential line (LVSS) as will be described later.

  Further, on the first plug P1t on the other source / drain region of TNA2, the first plug P1n on the other source / drain region of TNA1, and the first plug P1o on the other source / drain region of TP1, First-layer wirings M1 (M1BL, M1D) are respectively arranged. Further, on the first plug P1u on the other source / drain region of TNA3, the first plug P1p on the other source / drain region of TNA4, and the first plug P1q on the other source / drain region of TP2, First-layer wirings M1 (M1BL, M1D) are respectively arranged.

  Also, the first plug P1r on the gate electrode (G2a) of TNA2, the first plug P1v on the gate electrode (G2b) of TNA1, the first plug P1w on the gate electrode (G4b) of TNA4, and the gate electrode (TNA3) A first layer wiring M1W is arranged on each first plug P1s on G4a).

  The connection state by the first layer wiring M1 between the plurality of first plugs P1 can be variously modified as long as the connection state of the circuit diagram shown in FIG. 48 is satisfied.

[P2, M2, P3, M3]
As shown in FIG. 51, of the first layer wiring M1 described with reference to FIG. 50, the first layer other than the first layer wiring M1 (M1A, M1B) corresponding to the storage node (A or B). A second plug P2 is disposed on the wiring M1 (M1S, M1D, M1W, M1BL), and a second layer wiring M2 is disposed above the second plug P2.

  Specifically, the first layer wiring M1W connected to the gate electrode (G2a) of TNA2 is connected to the second layer wiring M2W through the second plug P2. The first layer wiring M1W connected to the gate electrode (G4b) of TNA4 is connected to the second layer wiring M2W through the second plug P2. These two second layer wirings M2W are arranged so as to extend in the Y direction in the memory cell region. Further, a third plug P3 is disposed on the two second layer wirings M2W, and a third layer wiring M3 (WLB) is disposed in the X direction so as to connect the two third plugs P3. . The third layer wiring M3 (WLB) is a word line.

  The first layer wiring M1W connected to the gate electrode (G4a) of TNA3 is connected to the second layer wiring M2W through the second plug P2. The first layer wiring M1W connected to the gate electrode (G2b) of TNA1 is connected to the second layer wiring M2W via the second plug P2. These two second layer wirings M2 are arranged so as to extend in the Y direction in the memory cell region. Further, a third plug P3 is disposed on the two second layer wirings M2W, and a third layer wiring M3 (WLA) is disposed in the X direction so as to connect the two third plugs P3. . The third layer wiring M3 (WLA) is a word line.

  The first layer wiring M1S connected to the other source / drain region (P1j) of TND2 and the other source / drain region (P1i) of TND1 is connected to the second layer wiring M2 (LVSS) via the second plug P2. ). The second layer wiring M2 (LVSS) is a ground potential line. The first layer wiring M1S connected to the other source / drain region (P1m) of TND4 and the other source / drain region (P1k) of TND3 is connected to the second layer wiring M2 (LVSS) via the second plug P2. Connected. The second layer wiring M2 (LVSS) is a ground potential line.

  The first layer wiring M1BL connected to the other source / drain region (P1t) of TNA2 is connected to the second layer wiring M2 (BLB) via the second plug P2. The first layer wiring M1BL connected to the other source / drain region (P1p) of the TNA4 is connected to the second layer wiring M2 (/ BLB) via the second plug P2. These two second layer wirings M2BL (bit lines (BLB, / BLB)) form a bit line pair and are arranged so as to extend in the Y direction.

  Further, the first layer wiring M1BL connected to the other source / drain region (P1n) of the TNA1 is connected to the second layer wiring M2 (BLA) via the second plug P2. The first layer wiring M1BL connected to the other source / drain region (P1u) of TNA3 is connected to the second layer wiring M2 (/ BLA) via the second plug P2. These two second layer wirings M2 (bit lines (BLA, / BLA)) constitute a bit line pair and are arranged so as to extend in the Y direction, respectively.

  The second plug P2 on the first layer wiring M1D connected to the other source / drain region (P1o) of TP1 and the first layer wiring M1D connected to the other source / drain region (P1q) of TP2. A second layer wiring M2 (LVDD) is arranged to connect the upper second plug P2. The second layer wiring M2 (LVDD) is a power supply potential line. The power supply potential line mainly extends in the Y direction, but has a line portion extending in the Y direction and a protrusion that covers the second plug P2 from the line portion.

  The connection state of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3 can be variously modified as long as the connection state of the circuit diagram shown in FIG. 48 is satisfied. As described above, a simple layout can be realized by extending the second layer wiring M2 mainly in the Y direction and extending the third layer wiring M3 mainly in the X direction. 49 to 51, for the sake of convenience, only a 1 (1 bit) memory cell region is shown. However, as will be described later, the memory cells are repeatedly arranged in the X direction and the Y direction. The ground potential lines (LVSS), bit lines (BLA, / BLA, BLB, / BLB), power supply potential lines (LVDD) extend in the Y direction, and word lines (WLA, WLB) extend in the X direction. Arranged to do.

  In the present embodiment, since the active regions are divided and arranged (AcP2 and AcP1, AcP4 and AcP3), driver transistors (TND1, TND2, TND3) corresponding to the element isolation regions (STI) located between the active regions. And TND4) are formed in a large area. By using this area, a bit line or a ground potential line (second potential wiring M2W connected to the word line) is connected between the second layer wiring M2 (second layer wiring M2W connected to the word line). LVSS) can be arranged. In addition, since the ground potential line (LVSS) is arranged between the bit lines, the shielding effect of the ground potential line (LVSS) is generated, and the interaction (crosstalk noise) between the bit lines can be reduced.

  Each pattern described with reference to FIGS. 49 to 51 is arranged point-symmetrically with respect to the center point of the memory cell region.

  For reference, ten transistors (TND2, TNA2, TNA1, TND1, TP1, TP2, TND4, TNA4, TND3, and TNA3) are arranged corresponding to the above “memory cell pattern layout” and their connections. A circuit diagram clearly showing the state is shown in FIG.

(Embodiment 10)
In the ninth embodiment, a dual-port SRAM (FIG. 48) has been described in which the length of the side extending in the Y direction of the substantially rectangular memory cell region is the length of two transistors. However, the length of the side extending in the Y direction of the substantially rectangular memory cell region may be the length of four transistors. In the present embodiment, a dual-port SRAM (FIG. 53) in which the length of the side extending in the Y direction of the substantially rectangular memory cell region is the length of four transistors will be described. .

  The circuit configuration of the SRAM memory cell of the present embodiment is the same as that of the ninth embodiment described with reference to FIG.

[Structure of SRAM]
[Configuration of memory cell]
53 to 55 are plan views showing the configuration of the SRAM memory cell according to the present embodiment. FIG. 53 shows the arrangement of the active region A, the gate electrode G, and the first plug P1. FIG. 54 shows an arrangement of the first plug P1, the first layer wiring M1, and the second plug P2. FIG. 55 shows the arrangement of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3. Therefore, in FIG. 53 and FIG. 54, the positional relationship of the display pattern in each figure becomes clear by overlapping the plan views with the first plug P1 as a reference. In FIGS. 54 and 55, the positional relationship of display patterns in each figure becomes clear by overlapping the plan views with the second plug P2 as a reference. Note that a rectangular area surrounded by an alternate long and short dash line in the figure indicates a 1 (1 bit) memory cell area.

[Memory cell pattern layout]
[A, G, P1]
As shown in FIG. 53, a p-type well (P-well), an n-type well (N-well), and a p-type well (P-well) are arranged in the X direction on the semiconductor substrate. In FIG. 53, only 1 (1 bit) memory cell region is shown. However, since the memory cells are repeatedly arranged in the X direction and the Y direction (see FIG. 12), these wells (P-well, N− well, P-well) extends in the Y direction. Note that the exposed region of these wells becomes an active region (active region, A).

  In addition, three active regions (AP1, AN, AP2) are arranged in the X direction on the semiconductor substrate. Between these active regions (A) is an element isolation region (STI). In other words, the active region (A) is defined by the element isolation region (STI). The wells (P-well, N-well, P-well) are connected at the lower part of the element isolation region STI.

  Specifically, the active region AP1 is an exposed region of a p-type well (P-well), and the memory cell region has a substantially rectangular shape having a long side in the Y direction. In FIG. 53, only 1 (1 bit) memory cell region is shown for convenience, but the memory cells are repeatedly arranged in the X direction and the Y direction (see FIG. 12). AP1 extends in a line shape in the Y direction.

  The active region AN is an exposed region of an n-type well (N-well) and has a substantially rectangular shape having a long side in the Y direction.

  The active region AP2 is an exposed region of a p-type well (P-well) located on the right side of the n-type well in the drawing, and the memory cell region has a substantially rectangular shape having a long side in the Y direction. Since the memory cells are repeatedly arranged in the X direction and the Y direction (see FIG. 12), in the memory cell array, the active region AP1 extends in a line shape in the Y direction.

  On the three active regions (AP1, AN, AP2), a gate electrode G extends across the active regions in the X direction via a gate insulating film (GO). The ten transistors described in the “Circuit Configuration” column are configured.

  Specifically, two common gate electrodes (G1, G3) are arranged so as to cross over the active regions AP1, AN, and AP2. Thereby, TND2 and TND4 are arranged in series on the active region AP2, sharing the source / drain region, TND1 and TND3 are arranged in series on the active region AP1, sharing the source / drain region, and TP1 and TP2 are arranged in series on the active region AN, sharing the source / drain region. Further, the gate electrodes (G) of TND1, TP1, and TND2 are connected by one common gate electrode G3, and the gate electrodes (G) of TND3, TP2, and TND4 are connected by the other common gate electrode G1. Will be. These two common gate electrodes (G1, G3) are arranged extending in the X direction in parallel.

  Further, on the active region AP1, one gate electrode G4b is arranged in parallel with the two common gate electrodes (G1, G3). Thereby, TNA1 is arranged on the active region AP1, and the source / drain region of TNA1 and the source / drain region of TND1 are connected (shared). On the active region AP1, another gate electrode G2a is arranged in parallel with the two common gate electrodes (G1, G3). Thereby, TNA3 is arranged on the active region AP1, and the source / drain region of TNA3 and the source / drain region of TND3 are connected (shared).

  On the active region AP2, one gate electrode G4a is disposed in parallel with the two common gate electrodes (G1, G3). As a result, TNA2 is arranged on active region AP2, and the source / drain region of TNA2 and the source / drain region of TND2 are connected (shared). On the active region AP2, another gate electrode G2b is disposed in parallel with the two common gate electrodes (G1, G3). As a result, the TNA 4 is disposed on the active region AP2, and the source / drain region of the TNA 4 and the source / drain region of the TND 4 are connected (shared).

  Thus, in the present embodiment, the driver transistors are divided (TND1 and TND2, TND3 and TND4) and arranged on different active regions (AP1, AP2). Furthermore, by extending these active regions (AP1, AP2) in the Y direction, a simple layout is obtained and the processing accuracy is improved.

  Therefore, as in the first embodiment, the gate width of the access transistor and the gate width of the driver transistor are easily set to 1: 2 without providing a corner (bent portion) in the shape of the active region (A). Can do.

  In addition, since the access transistors (TNA1, TNA2, TNA3, TNA4) are also arranged in the active regions (AP1, AP2), the number of active regions can be reduced. As a result, a simple layout can be realized, and the memory cell area can be reduced.

  Further, by extending the active region (A) in the Y direction, the gate electrode (G) can be extended in the X direction, and not only the processing accuracy of the active region (A) but also the gate electrode (G). The machining accuracy can be improved. In particular, as described in detail in the first embodiment, the multiple exposure technique can be easily adopted, and the processing accuracy can be improved. Moreover, simulation model creation becomes easy and the verification accuracy can be improved.

[P1, M1, P2]
As shown in FIG. 54, the ten transistors (TND2, TNA2, TNA1, TND1, TP1, TP2, TND4, TNA4, TND3, TNA3) described with reference to FIG. One plug P1 is arranged. The first plug P1 is also disposed on the six gate electrodes described with reference to FIG.

  A first layer wiring M1 is disposed on the first plug P1, and electrical connection between the first plugs P1 is achieved.

  Specifically, the first plug P1F on the common source / drain region of TNA2 and TND2, the first plug P1E on the common source / drain region of TND1 and TNA1, and the first plug on one of the source / drain regions of TP1. The plug P1G and the first plug P1H on the common gate electrode (G1) of TP2, TND3, and TND4 are connected by the first layer wiring (first node wiring) M1A. The first layer wiring M1A can be associated with the storage node A of FIG. The above "one" indicates the upper source / drain region in the drawing.

  A first plug P1B on the common source / drain region of TNA3 and TND3, a first plug P1A on the common source / drain region of TND4 and TNA4, a first plug P1C on one of the source / drain regions of TP2, and The first plug P1D on the common gate electrode (G3) of TP1, TND1, and TND2 is connected by the first layer wiring (second node wiring) M1B. The first layer wiring M1B can be associated with the storage node B of FIG. Here, “one” means the lower source / drain region in the figure.

  A first layer wiring M1S is arranged on the first plug P1I on the common source / drain region of TND2 and TND4. A first layer wiring M1S is disposed on the first plug P1J on the common source / drain region of TND1 and TND3. These first layer wirings M1S can be associated with the ground potential (VSS) of FIG. 48 and are connected to the ground potential line (LVSS) as will be described later.

  A first layer wiring (pad region) M1D is disposed on the first plug P1K on the common source / drain region of TP1 and TP2. The first layer wiring M1D can be associated with the power supply potential (VDD) of FIG. 48 and is connected to the power supply potential line (LVDD) as will be described later.

  Further, the first layer wiring M1BL is disposed on the first plug P1W on the other source / drain region of TNA1 and the first plug P1M on the other source / drain region of TNA2.

  The first layer wiring M1BL is disposed on the first plug P1L on the other source / drain region of the TNA3 and the first plug P1X on the other source / drain region of the TNA4.

  The first layer wiring M1W is arranged so as to connect the first plug P1Y on the gate electrode (G4b) of TNA1 and the first plug P1N on the gate electrode (G2a) of TNA3. The first layer wiring M1W is arranged so as to connect the first plug P1O on the gate electrode (G4a) of TNA2 and the first plug P1Z on the gate electrode (G2b) of TNA4.

  The connection state by the first layer wiring M1 between the plurality of first plugs P1 can be variously modified as long as the connection state of the circuit diagram shown in FIG. 48 is satisfied.

[P2, M2, P3, M3]
As shown in FIG. 55, of the first layer wiring M1 described with reference to FIG. 54, the first layer other than the first layer wiring M1 (M1A, M1B) corresponding to the storage node (A or B). A second plug P2 is disposed on the wiring M1 (M1S, M1D, M1W, M1BL), and a second layer wiring M2 is disposed above the second plug P2.

  Specifically, the first layer wiring M1W connected to the gate electrodes (G4b, G2a) of TNA1 and TNA3 is connected to the second layer wiring M2W through the second plug P2. On the second layer wiring M2W, a third layer wiring M3 (WLA) is arranged via a third plug P3. The third layer wiring M3 (WLA) is a word line and extends in the X direction. The first layer wiring M1W connected to the gate electrodes (G4a, G2b) of TNA2 and TNA4 is connected to the second layer wiring M2W via the second plug P2. On the second layer wiring M2W, a third layer wiring M3 (WLB) is arranged via a third plug P3. The third layer wiring M3 (WLB) is a word line and extends in the X direction.

  The first layer wiring M1S connected to the common source / drain region (P1I) of TND2 and TND4 is connected to the second layer wiring M2 (LVSS) through the second plug P2. The second layer wiring M2 (LVSS) is a ground potential line. The first layer wiring M1S connected to the common source / drain region (P1J) of TND3 and TND1 is connected to the second layer wiring M2 (LVSS) via the second plug P2. The second layer wiring M2 (LVSS) is a ground potential line. These two ground potential lines are arranged so as to extend in the Y direction, respectively.

  The first layer wiring M1BL connected to the other source / drain region (P1M) of the TNA2 is connected to the second layer wiring M2 (BLB) via the second plug P2. The first layer wiring M1BL connected to the other source / drain region (P1X) of the TNA4 is connected to the second layer wiring M2 (/ BLB) via the second plug P2. These two second layer wirings M2 (bit lines (BLB, / BLB), bit line pairs) are arranged so as to extend in the Y direction.

  The first layer wiring M1BL connected to the other source / drain region (P1W) of the TNA1 is connected to the second layer wiring M2 (BLA) via the second plug P2. The first layer wiring M1BL connected to the other source / drain region (P1L) of the TNA3 is connected to the second layer wiring M2 (/ BLA) via the second plug P2. These two second layer wirings M2 (bit lines (BLA, / BLA)) constitute a bit line pair and are arranged so as to extend in the Y direction, respectively.

  Further, the second layer wiring M2 (LVDD) is disposed on the first layer wiring M1D connected to the common source / drain region (P1K) of TP1 and TP2 via the second plug P2. The second layer wiring M2 (LVDD) is a power supply potential line. This power supply potential line extends in the Y direction.

  The connection state of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3 can be variously modified as long as the connection state of the circuit diagram shown in FIG. 48 is satisfied. As described above, a simple layout can be realized by extending the second layer wiring M2 mainly in the Y direction and extending the third layer wiring M3 mainly in the X direction. 53 to 55 show only a 1 (1 bit) memory cell region for convenience, but since the memory cells are repeatedly arranged in the X direction and the Y direction as will be described later, in the memory cell array, FIG. The ground potential lines (LVSS), bit lines (BLA, / BLA, BLB, / BLB), power supply potential lines (LVDD) extend in the Y direction, and word lines (WLA, WLB) extend in the X direction. Arranged to do.

  In the present embodiment, since the ground potential line (LVSS) is disposed between the second layer wiring and the bit line, the shielding effect of the ground potential line (LVSS) occurs, and the interaction between the wirings ( Crosstalk noise) can be reduced.

  Each pattern described with reference to FIGS. 53 to 55 is arranged point-symmetrically with respect to the center point of the memory cell region.

  For reference, ten transistors (TND2, TNA2, TNA1, TND1, TP1, TP2, TND4, TNA4, TND3, and TNA3) are arranged corresponding to the above “memory cell pattern layout” and their connections. A circuit diagram clearly showing the state is shown in FIG.

(Embodiment 11)
Regarding the structure of the SRAM, a circuit in which the conductivity type of each transistor shown in the first embodiment (FIG. 1) is reversed has been proposed. In the present embodiment, an SRAM memory cell having such a circuit configuration will be described.

[Circuit configuration]
FIG. 57 is an equivalent circuit diagram showing the SRAM memory cell of the present embodiment. As shown in the figure, the memory cell has eight transistors as in the first embodiment, but instead of the n-type transistors (TNA1, TNA2, TND1, TND2, TND3, TND4) shown in FIG. Transistors (TPA1, TPA2, TPD1, TPD2, TPD3, and TPD4) are used. Further, n-type transistors (TN1, TN2) are used instead of the p-type transistors (TP1, TP2) shown in FIG.

  Thus, the conductivity type of the transistor used is reversed.

  The p-type (second conductivity type in this embodiment) transistor (TPA1, TPA2, TPD1, TPD2, TPD3, TPD4) has a power supply potential (VDD, a second power supply potential in this embodiment, a second power supply). A potential different from the potential, a potential higher than the second power supply potential).

  N-type (first conductivity type in this embodiment) transistors (TN1, TN2) are connected to a ground potential (VSS, first power supply potential in this embodiment).

  The rest of the configuration is the same as that of the circuit configuration shown in FIG.

  Thus, the SRAM memory cell of the present embodiment is also configured by dividing the driver transistor (TPD1 and TPD2, TPD3 and TPD4).

[Structure of SRAM]
[Configuration of memory cell]
58 to 60 are plan views showing the configuration of the SRAM memory cell according to the present embodiment. FIG. 58 shows the arrangement of the active region Ac, the gate electrode G, and the first plug P1. FIG. 59 shows the arrangement of the first plug P1, the first layer wiring M1, and the second plug P2. FIG. 60 shows the arrangement of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3. Therefore, in FIG. 58 and FIG. 59, the positional relationship between the display patterns in each figure becomes clear by overlapping the plan views with the first plug P1 as a reference. In FIGS. 59 and 60, the positional relationship between the display patterns in each figure becomes clear by overlapping the plan views with the second plug P2 as a reference. Note that a rectangular area surrounded by an alternate long and short dash line in the figure indicates a 1 (1 bit) memory cell area.

[Memory cell pattern layout]
As described above, the SRAM memory cell of the present embodiment is configured by reversing the conductivity type of each transistor shown in the first embodiment (FIG. 1). Therefore, as shown in FIG. 58, the conductivity type of the well is opposite to that in the first embodiment (FIG. 2). Also, six active regions (AcN2, AcN1, AcP1, AcP2, AcN3, AcN4) are arranged side by side in the X direction. An element isolation region (STI) is formed between these active regions (Ac). In other words, the active region (Ac) is defined by the element isolation region (STI).

  Of the six active regions (AcN2, AcN1, AcP1, AcP2, AcN3, AcN4), AcN2, AcN1, AcN3, and AcN4 are exposed regions of the n-type well (N-well), and AcP1 and AcP2 are p-type wells. Except for the (P-well) exposed region, the pattern arrangement is the same as in the first embodiment (FIG. 2). Of course, the impurity conductivity type of the source / drain region of the transistor introduced into the active region (Ac) is reversed. That is, the conductivity type of the source / drain region in the active region which is the exposed region of the n-type well (N-well) is p-type, and the source in the active region which is the exposed region of the p-type well (P-well). The conductivity type of the drain region is n-type.

  Further, since the arrangement of the gate electrode G and the first plug P1 is the same as that of the first embodiment (FIG. 2), the description thereof is omitted. Also, the arrangement of the first plug P1, the first layer wiring M1, and the second plug P2 shown in FIG. 59 is the same as that of the first embodiment (FIG. 3). Also, the arrangement of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3 shown in FIG. 60 is replaced with the ground potential line (LVSS) of the first embodiment (FIG. 4). The second layer wiring M2 (LVDD) is arranged, and the second layer wiring M2 (LVDD) is arranged instead of the second layer wiring M2 (LVDD), which is the same as in the first embodiment (FIG. 4). Therefore, the description thereof is omitted.

  Thus, also in the present embodiment, as in the first embodiment, the driver transistors are divided (TPD1 and TPD2, TPD3 and TPD4) and arranged on different active regions (AcN2 and AcN1, AcN4 and AcN3). ing. Further, by extending these active regions (AcN2 and AcN1, AcN4 and AcN3) in the Y direction, a simple layout is obtained and the processing accuracy is improved. Furthermore, since the access transistors (TPA1, TPA2) are also arranged in these active regions, the number of active regions can be reduced.

  Further, the drive capability of the driver transistors (TPD1, TPD3) can be made larger than the drive capability of the access transistors (TPA1, TPA2). For example, by setting the width (length in the X direction) of the active regions (AcN2 and AcN1, AcN4 and AcN3) to 1: 1, the gate width of the access transistor and the gate width of the driver transistor can be easily set to 1: 2. It can be.

  Further, by dividing the active region (TPD1 and TPD2, TPD3 and TPD4), each active region can be formed into a substantially rectangular shape. In other words, the shape without the corner (bent portion) can be obtained. Therefore, the processing accuracy is improved, and the characteristics of each transistor formed on the active region (Ac) can be improved. In addition, manufacturing variations can be reduced and the operating characteristics of the SRAM memory cell array can be improved. In addition, the manufacturing yield can be improved.

  Further, in one of the divided active regions (TPD1 and TPD2, TPD3 and TPD4) (AcN1 or AcN3 in FIG. 58), in addition to the driver transistors (TPD1, TPD3), access transistors (TPA1, TPA2) are also arranged. Therefore, the number of active regions can be reduced. As a result, a simple layout can be realized, and the memory cell area can be reduced.

  Further, by extending the active region (Ac) in the Y direction, the gate electrode (G) can be extended in the X direction, and not only the processing accuracy of the active region (Ac) but also the gate electrode (G). The machining accuracy can be improved. In particular, as described in detail in the first embodiment, the multiple exposure technique can be easily adopted, and the processing accuracy can be improved. Moreover, simulation model creation becomes easy and the verification accuracy can be improved.

  Similarly to the first embodiment, the second layer wiring M2 extends mainly in the Y direction and the third layer wiring M3 extends mainly in the X direction (FIG. 60), thereby realizing a simple layout. be able to.

  In this embodiment, since the active regions are divided and arranged (AcN2 and AcN1, AcN4 and AcN3), driver transistors (TPD1, TPD2, and TPD3) corresponding to the element isolation regions (STI) located between the active regions. And TPD4) are formed in a large area, and the power supply potential line (LVDD) can be arranged using this area.

  Each pattern described with reference to FIGS. 58 to 60 is arranged point-symmetrically with respect to the center point of the memory cell region.

  For reference, eight transistors (TPD2, TPA1, TPD1, TN1, TN2, TPD3, TPA2, and TPD4) are arranged in correspondence with the above “memory cell pattern layout”, and their connection states are clarified. A circuit diagram is shown in FIG.

(Embodiment 12)
There are no restrictions on semiconductor devices (including semiconductor components and electronic devices) in which the SRAM described in detail in the above embodiments is used. For example, there is a system including a SoC (System-on-a-chip) and a microcomputer. It can be incorporated into the formed semiconductor chip. FIG. 62 shows a layout configuration of a semiconductor chip in the present embodiment. In FIG. 62, the semiconductor chip includes a CPU (Central Processing Unit), an SRAM, and a logic circuit (LOGIC). As the SRAM, the above-described single port SRAM (SP-SRAM) or dual port SRAM (DP-SRAM) is used. In addition to the SRAM, another storage element such as an EEPROM (Electrically Erasable Programmable Read Only Memory) may be used, or an analog circuit or the like may be incorporated.

  The CPU is also called a central processing unit, and corresponds to the heart of a computer or the like. This CPU reads and decodes instructions from a storage device, and performs a wide variety of operations and controls based on the instructions. A CPU core (CPU core) is built in the CPU, and an SRAM is built in the CPU core. A high-performance SRAM is used as the SRAM in the CPU core, and the SRAM described in detail in the first to eleventh embodiments is suitable. Of course, the SRAM described in detail in the first to eleventh embodiments may be used for the single-port SRAM (SP-SRAM) section or the dual-port SRAM (DP-SRAM) section.

  As described above, by incorporating the SRAM described in the first to eleventh embodiments into the microcomputer, the characteristics of the microcomputer can be improved.

  The invention made by the present inventor has been specifically described based on the first to eleventh embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  For example, in the first embodiment and the like, the active region (AcP1, AcP2, etc.) has been described as having a substantially rectangular shape. However, on the reticle (exposure mask), even if it is rectangular, the pattern after exposure and etching ( The actual finished shape is not necessarily rectangular (rectangular). For example, as shown in FIG. 63, the corner may be rounded. In addition, the pattern width may vary depending on the location. Even in such a case, the present invention does not exclude the shape shown in FIG. 63 in order to achieve the above effect.

  Furthermore, although the gate electrode (G) in each figure (for example, FIG. 2 etc.) is shown in a rectangular shape (rectangular shape), the actual finished shape may have rounded corners. Such a shape is also included.

  In addition, a part of the configuration of the above embodiment can be combined. For example, in the pattern layout (FIG. 2) of the first embodiment, the shared first plug SP1 of the fifth embodiment (FIG. 30) may be applied. Further, the pattern of the n-type well (N-well) of the sixth embodiment (FIG. 34) may be applied to TP1 and TP2 of the first embodiment (FIG. 2). The shared first plug SP1 may be applied. In the pattern layout (FIG. 2) of the first embodiment, p-type wells (P-wells) may be arranged together on one side as in the seventh embodiment (FIG. 38). Further, the SRAM of the eleventh embodiment in which the conductivity type of each transistor is reversed can be applied to the pattern layouts of other embodiments. As described above, the present invention can be variously modified without departing from the gist thereof.

  The present invention relates to a semiconductor device, and is particularly applicable to a semiconductor device having an SRAM.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate Ac Active region AcN1 Active region AcN2 Active region AcN3 Active region AcN4 Active region AcP1 Active region AcP2 Active region AcP3 Active region AcP4 Active region AN Active region AP1, AP2 Active region A, B Storage node AcS Active region BL, / BL Bit line BLA, / BLA Bit line BLB, / BLB Bit line DG Dummy gate electrode EX1 Low concentration impurity region EX2 High concentration impurity region F Memory cell F ′ Tap cell G (G1-G4, G2a, G2b, G4a, G4b) Gate electrode GO gate insulating film IL1 interlayer insulating film IL2 interlayer insulating film IL3 interlayer insulating film M1 (M1S, M1D, M1W, M1BL) first layer wiring M2 second layer wiring M2W second layer wiring M3 third layer wiring N-well n-type Well P1 (P1a to P1o, P1A to P1 ) First plug P2 second plug P3 third plug P-well p-type well SP1 shared first plug STI element isolation region SW sidewall Sp separation unit TNA1 access transistor (transistor)
TNA2 Access transistor (transistor)
TNA3 Access transistor (transistor)
TNA4 Access transistor (transistor)
TND1 Driver transistor (transistor)
TND2 Driver transistor (transistor)
TND3 Driver transistor (transistor)
TND4 Driver transistor (transistor)
TP1 Load transistor (transistor)
TP2 load transistor (transistor)
VDD Power supply potential LVDD Power supply potential line VSS Ground potential LVSS Ground potential line LVSSB Second ground potential line WL Word line WLA Word line WLB Word line

Claims (22)

A semiconductor substrate;
A first conductivity type first well formed on the semiconductor substrate;
A first conductivity type second well formed in the semiconductor substrate;
A second conductivity type well formed on the semiconductor substrate and disposed between the first conductivity type first well and the first conductivity type second well in a first direction in plan view;
A first conductivity type first MIS transistor electrically connected between a first node to which a first potential is supplied and a second node;
A second conductivity type first MIS transistor electrically connected between a third node supplied with a second potential different from the first potential and the second node;
A second conductivity type second MIS transistor connected in parallel with the second conductivity type first MIS transistor between the second node and the third node;
A first conductivity type second MIS transistor electrically connected between the first node and the fourth node;
A second conductivity type third MIS transistor electrically connected between the third node and the fourth node;
A second conductivity type fourth MIS transistor electrically connected in parallel with the second conductivity type third MIS transistor between the third node and the fourth node;
A second conductivity type fifth MIS transistor electrically connected between the second node and the fifth node;
A second conductivity type sixth MIS transistor electrically connected between the fourth node and the sixth node;
Have,
The second conductive type first MIS transistor and the second conductive type fifth MIS transistor are disposed in a first active region,
The second conductivity type second MIS transistor is disposed in a second active region separated from the first active region and disposed adjacent to the first active region;
The second conductivity type third MIS transistor is disposed in a third active region,
The second conductivity type fourth MIS transistor and the second conductivity type sixth MIS transistor are separated from the third active region and disposed in a fourth active region disposed adjacent to the third active region,
The first active region, the second active region, the third active region, and the fourth active region are arranged apart from each other so as to be sequentially arranged in the first direction,
The first active region and the second active region are disposed in the first conductivity type first well in plan view,
The third active region and the fourth active region are disposed in the first conductivity type second well in plan view,
A gate electrode of the second conductivity type fifth MIS transistor is formed by a part of the first gate wiring;
The first gate line extends in the first direction and is disposed on the first active region;
Each gate electrode of the second conductivity type first MIS transistor and the second conductivity type second MIS transistor is formed by a part of a second gate wiring,
The second gate line extends in the first direction and is disposed on the first active region and the second active region;
Each gate electrode of the second conductivity type third MIS transistor and the second conductivity type fourth MIS transistor is formed by a part of a third gate wiring,
The third gate line extends in the first direction and is disposed on the third active region and the fourth active region;
A gate electrode of the second conductivity type sixth MIS transistor is formed by a part of a fourth gate wiring;
The fourth gate line extends in the first direction and is disposed on the fourth active region;
The length of the first active region in the second direction intersecting the first direction is longer than the length of the second active region in the second direction,
The length of the fourth active region in the second direction is longer than the length of the third active region in the second direction. The second node includes a first wiring extending in the first direction and disposed on the first active region and the second active region,
The semiconductor device according to claim 1, wherein the fourth node includes a second wiring that extends in the first direction and is disposed on the third active region and the fourth active region. The first gate wiring and the fourth gate wiring are disposed in a first wiring layer,
The first gate wiring and the fourth gate wiring are disposed in a second wiring layer different from the first wiring layer and electrically connected to a word line extending in the first direction;
The fifth node is electrically connected to a first bit line arranged in a third wiring layer different from any of the first wiring layer and the second wiring layer,
The sixth node is electrically connected to a second bit line disposed in the third wiring layer,
2. The semiconductor device according to claim 1, wherein the first bit line and the second bit line extend in the second direction in a plan view and are disposed on the semiconductor substrate.   The first conductivity type first MIS transistor, the first conductivity type second MIS transistor, the second conductivity type first MIS transistor, the second conductivity type second MIS transistor, the second conductivity type third MIS transistor, the second conductivity type. The semiconductor device according to claim 1, wherein the fourth MIS transistor, the second conductivity type fifth MIS transistor, and the second conductivity type sixth MIS transistor are transistors constituting a static random access memory. The second conductivity type fifth MIS transistor and the second conductivity type sixth MIS transistor are access transistors of the static random access memory,
The second conductivity type first MIS transistor, the second conductivity type second MIS transistor, the second conductivity type third MIS transistor, and the second conductivity type fourth MIS transistor are drive transistors of the static random access memory, Item 5. The semiconductor device according to Item 4. The second active region is separated from the first active region by a first element isolation region formed in a semiconductor substrate,
The semiconductor device according to claim 1, wherein the fourth active region is separated from the third active region by a second element isolation region formed in the semiconductor substrate. The second active region is an active region disposed closest to the second conductivity type well in the first direction among the active regions disposed in the first conductivity type first well,
The third active region is an active region disposed closest to the second conductivity type well in the first direction among the active regions disposed in the first conductivity type second well. The semiconductor device described. A fifth active region in which the first conductivity type first MIS transistor is disposed;
A sixth active region isolated from the fifth active region and disposed with the first conductivity type second MIS transistor;
Further comprising
A gate electrode of the first conductivity type first MIS transistor is formed by a part of the second gate wiring;
A gate electrode of the first conductivity type second MIS transistor is formed by a part of the third gate wiring;
The fifth active region is disposed between the second active region and the sixth active region;
The semiconductor device according to claim 1, wherein the sixth active region is disposed between the fifth active region and the third active region. Wherein the first active region has a first width in the first direction, and extend in a first width in the second direction,
The second active region has a second width in the first direction, and extends in the second width in the second direction,
The third active region has a third width in the first direction, and extend in the third width in the second direction,
It said fourth active region, wherein the first direction and a fourth width, and extending in a fourth width in the second direction, the semiconductor device according to claim 1, wherein.   The semiconductor device according to claim 9, wherein the first width and the second width are equal.   The semiconductor device according to claim 10, wherein the third width is equal to the fourth width. A semiconductor substrate;
A first conductivity type first well formed on the semiconductor substrate;
A first conductivity type second well formed in the semiconductor substrate;
A second conductivity type well formed on the semiconductor substrate and disposed between the first conductivity type first well and the first conductivity type second well in a first direction in plan view;
A first conductivity type first MIS transistor electrically connected between a first node to which a first potential is supplied and a second node;
A second conductivity type first MIS transistor electrically connected between a third node supplied with a second potential different from the first potential and the second node;
A second conductivity type second MIS transistor connected in parallel with the second conductivity type first MIS transistor between the second node and the third node;
A first conductivity type second MIS transistor electrically connected between the first node and the fourth node;
A second conductivity type third MIS transistor electrically connected between the third node and the fourth node;
A second conductivity type fourth MIS transistor electrically connected in parallel with the second conductivity type third MIS transistor between the third node and the fourth node;
A second conductivity type fifth MIS transistor electrically connected between the second node and the fifth node;
A second conductivity type sixth MIS transistor electrically connected between the fourth node and the sixth node;
Have,
The second conductive type first MIS transistor and the second conductive type fifth MIS transistor are disposed in a first active region,
The second conductivity type second MIS transistor is disposed in a second active region separated from the first active region and disposed adjacent to the first active region;
The second conductivity type third MIS transistor is disposed in a third active region,
The second conductivity type fourth MIS transistor and the second conductivity type sixth MIS transistor are separated from the third active region and disposed in a fourth active region disposed adjacent to the third active region,
The first active region, the second active region, the third active region, and the fourth active region are arranged apart from each other so as to be sequentially arranged in the first direction,
The first active region and the second active region are disposed in the first conductivity type first well in plan view,
The third active region and the fourth active region are disposed in the first conductivity type second well in plan view,
A gate electrode of the second conductivity type fifth MIS transistor is formed by a part of the first gate wiring;
The first gate line extends in the first direction and is disposed on the first active region;
Each gate electrode of the second conductivity type first MIS transistor and the second conductivity type second MIS transistor is formed by a part of a second gate wiring,
The second gate line extends in the first direction and is disposed on the first active region and the second active region;
Each gate electrode of the second conductivity type third MIS transistor and the second conductivity type fourth MIS transistor is formed by a part of a third gate wiring,
The third gate line extends in the first direction and is disposed on the third active region and the fourth active region;
A gate electrode of the second conductivity type sixth MIS transistor is formed by a part of a fourth gate wiring;
The fourth gate line extends in the first direction and is disposed on the fourth active region;
The area of the first active region is wider than the area of the second active region,
The area of the fourth active region is a semiconductor device wider than the area of the third active region. The second node includes a first wiring extending in the first direction and disposed on the first active region and the second active region,
The semiconductor device according to claim 12, wherein the fourth node includes a second wiring that extends in the first direction and is disposed on the third active region and the fourth active region. The first gate wiring and the fourth gate wiring are disposed in a first wiring layer,
The first gate wiring and the fourth gate wiring are disposed in a second wiring layer different from the first wiring layer and electrically connected to a word line extending in the first direction;
The fifth node is electrically connected to a first bit line arranged in a third wiring layer different from any of the first wiring layer and the second wiring layer,
The sixth node is electrically connected to a second bit line disposed in the third wiring layer,
13. The semiconductor device according to claim 12, wherein the first bit line and the second bit line extend in a second direction intersecting the first direction in a plan view and are disposed on the semiconductor substrate.   The first conductivity type first MIS transistor, the first conductivity type second MIS transistor, the second conductivity type first MIS transistor, the second conductivity type second MIS transistor, the second conductivity type third MIS transistor, the second conductivity type. 13. The semiconductor device according to claim 12, wherein the fourth MIS transistor, the second conductivity type fifth MIS transistor, and the second conductivity type sixth MIS transistor are transistors constituting a static random access memory. The second conductivity type fifth MIS transistor and the second conductivity type sixth MIS transistor are access transistors of the static random access memory,
The second conductivity type first MIS transistor, the second conductivity type second MIS transistor, the second conductivity type third MIS transistor, and the second conductivity type fourth MIS transistor are drive transistors of the static random access memory, Item 15. A semiconductor device according to Item 15. The second active region is separated from the first active region by a first element isolation region formed in a semiconductor substrate,
The semiconductor device according to claim 12, wherein the fourth active region is separated from the third active region by a second element isolation region formed in the semiconductor substrate. The second active region is an active region disposed closest to the second conductivity type well in the first direction among the active regions disposed in the first conductivity type first well,
The third active region is an active region disposed closest to the second conductivity type well in the first direction among the active regions disposed in the first conductivity type second well. The semiconductor device described. A fifth active region in which the first conductivity type first MIS transistor is disposed;
A sixth active region isolated from the fifth active region and disposed with the first conductivity type second MIS transistor;
Further comprising
A gate electrode of the first conductivity type first MIS transistor is formed by a part of the second gate wiring;
A gate electrode of the first conductivity type second MIS transistor is formed by a part of the third gate wiring;
The fifth active region is disposed between the second active region and the sixth active region;
The semiconductor device according to claim 12, wherein the sixth active region is disposed between the fifth active region and the third active region. Wherein the first active region has a first width in the first direction, and extend in a first width in a second direction crossing the first direction,
The second active region has a second width in the first direction, and extends in the second width in the second direction,
The third active region has a third width in the first direction, and extend in the third width in the second direction,
It said fourth active region, wherein the first direction and a fourth width, and extending in a fourth width in the second direction, the semiconductor device according to claim 12.   21. The semiconductor device according to claim 20, wherein the first width and the second width are equal.   The semiconductor device according to claim 21, wherein the third width and the fourth width are equal.

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