CN1836323A - 混合晶向衬底上的高性能cmos soi器件 - Google Patents
混合晶向衬底上的高性能cmos soi器件 Download PDFInfo
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Abstract
提供了一种集成的半导体结构,它包含至少一个形成在对器件最佳的第一晶面上的器件,而另一器件被形成在对此另一器件最佳的不同的第二晶面上。形成此集成结构的方法包括提供键合衬底,此键合衬底至少包括第一晶向的第一半导体层和不同的第二晶向的第二半导体层。部分键合衬底被保护以确定第一器件区,而键合衬底的其它部分不被保护。键合衬底的未被保护部分然后被腐蚀,以便暴露第二半导体层的表面,并在暴露的表面上再生长半导体材料。在整平之后,第一半导体器件被形成在第一器件区中,而第二半导体器件被形成在再生长材料中。
Description
技术领域
本发明涉及到半导体器件,更确切地说是涉及到形成在混合晶向衬底上的诸如绝缘体上硅(SOI)/互补金属氧化物半导体(CMOS)器件之类的集成半导体器件。确切地说,本发明提供了一种将诸如NFET和PFET之类的至少二种半导体器件集成到具有不同晶向的键合衬底上的方法。各个器件在键合衬底上的位置依赖于器件在特定晶向上的性能。例如,本发明在(100)表面上制作NFET,而在(110)表面上制作PFET。(100)晶面提供具有高性能的NFET,而(110)晶面提供具有高性能的PFET。
背景技术
在当今的半导体技术中,诸如NFET或PFET之类的CMOS器件典型地被制作在诸如硅的具有单晶取向的半导体晶片上。确切地说,大多数现今的半导体器件被建造在具有(100)晶向的硅上。
已知对于(100)硅表面取向,电子具有高的迁移率,但空穴对于(110)表面取向具有高迁移率。亦即,(100)硅上的空穴迁移率数值大致比此晶向上的相应电子迁移率低2-4倍。为了补偿这一差异,PFET典型地被设计成具有较大的宽度,以便平衡正偏电流与NFET的反偏电流并得到均匀的电路转换。宽度较大的NFET是不可取的,因为它们占据很大的芯片面积。
另一方面,(110)硅上的空穴迁移率比(100)硅上的空穴迁移率高2倍;因此,形成在(110)表面上的PFET将比形成在(100)表面上的PFET显示出明显更高的驱动电流。不幸的是,与(100)硅表面相比,(110)硅表面上的电子迁移率被明显地降低。(110)硅表面上的电子迁移率降低被示于例如图1中。在图1中,实线表示电子迁移率,而虚线表示空穴迁移率。
如从上述讨论和图1能够推断的那样,(110)硅表面由于优异的空穴迁移率而对PFET最佳,而这一晶向完全不适合于NFET器件。另一方面,(100)硅表面由于其晶向有利于电子迁移率而对NFET最佳。
考虑到上述情况,对于提供形成在具有为特定器件提供最佳性能的不同晶向的衬底上的半导体器件,存在着需求。亦即,对于产生一种衬底,此衬底使诸如PFET的一种器件能够被制作在某个晶面例如(110)表面上而诸如NFET的另一种器件能够被制作在另一个晶面例如(100)表面上,存在着强烈的需求。
发明内容
本发明的一个目的是提供一种半导体器件的集成方法,使不同类型的器件被制作在键合衬底的提高器件性能的特定晶向上。
本发明的另一目的是提供一种半导体器件的集成方法,使PFET位于键合衬底的(110)晶面上,而NFET位于(100)晶面上。
本发明的另一目的是提供一种用简单而容易的工艺步骤来集成绝缘体上硅(SOI)技术与互补金属氧化物半导体(CMOS)技术的方法。
本发明的另一目的是提供一种方法,其中,一个CMOS器件是类SOI的,而另一个CMOS器件是类体的。
本发明的另一目的是提供一种方法,其中,被集成的二个CMOS器件都是类SOI的。
本发明的另一目的是提供一种方法,来集成(100)晶面上的应变硅NFET与(110)晶面上的硅或应变硅PFET。
本发明的另一目的是提供一种方法,用来将不同的CMOS器件集成到具有不同晶向表平面的键合衬底上,其中,在不同类型的CMOS器件之间形成了隔离区。
利用包括晶片键合、掩蔽、腐蚀、以及半导体层再生长各个步骤的方法,达到了这些和其它的目的和优点。具体地说,本发明的方法包含下列步骤:
提供键合衬底,它至少包含被绝缘层分隔开的第一晶向的第一半导体层和第二晶向的第二半导体层,所述第一晶向不同于所述第二晶向,且所述第一半导体层位于所述第二半导体层上方;
保护部分键合衬底,以便确定第一器件区,同时使键合衬底的另一部分不被保护,键合衬底的所述不被保护的部分确定了第二器件区;
对键合衬底的所述未被保护的部分进行腐蚀,以便暴露第二半导体层的表面;
在第二半导体层的所述暴露表面上再生长半导体材料,所述半导体材料的晶向与第二晶向相同;
对包含此半导体材料的键合衬底进行整平,使第一半导体层的上表面与此半导体材料的上表面基本上齐平;以及
在所述第一器件区中至少形成一个第一半导体器件,同时在所述第二器件区中的所述半导体材料上至少形成一个第二半导体器件。
根据本发明,第一半导体器件可以是PFET,且第一晶向可以是(110)或(111),而第二半导体器件可以是NFET,且第二晶向可以是(100)或(111)。在本发明中也有可能第一半导体器件是NFET,而第二半导体器件是PFET。在本发明的一个实施方案中,此方法还包含在第一器件区与第二器件区之间形成隔离区。在本发明的另一实施方案中,此半导体材料包含应变硅的上层和弛豫SiGe合金或SiC合金的下层。
本发明的另一情况涉及到一种集成的半导体结构,它至少包含二种器件,其中,至少一个器件被形成在对此器件最佳的第一晶面上,而另一器件被形成在对此另一器件最佳的不同于第一晶面的第二晶面上。具体地说,本发明的结构包含:
键合衬底,它包含具有第一晶向的第一器件区和具有第二晶向的第二器件区,所述第一晶向不同于所述第二晶向;
隔离区,它将所述第一器件区分隔于所述第二器件区;以及
位于所述第一器件区的至少一个第一半导体器件和位于所述第二器件区的至少一个第二半导体器件。
根据本发明,第一半导体器件可以是PFET,且第一晶向可以是(110)或(111),而第二半导体器件可以是NFET,且第二晶向可以是(100)或(111)。在本发明中也有可能第一半导体器件是NFET,而第二半导体器件是PFET。这些半导体器件的构造将依赖于键合衬底的晶向。
附图说明
图1是Vgs=1V下的μeff对硅衬底晶向的关系曲线。
图2A-2F是剖面图,示出了用于本发明在键合衬底的不同晶面上形成集成CMOS器件的基本工艺步骤。
图3A-3D示出了可以被键合到一起并用于图2A-2E所示方法中的各种晶片。
图4A-4J是剖面图,示出了用来形成高性能半导体器件的基本工艺步骤,此高性能半导体器件包含二个形成在(100)晶面上的NFET以及形成在(110)晶面上的位于二个NFET之间的一个PFET。
图5A-5G是剖面图,示出了用来形成高性能半导体器件的变通基本工艺步骤,此高性能半导体器件包含二个形成在(100)晶面上的NFET以及形成在(110)晶面上的位于二个NFET之间的一个PFET。
具体实施方式
现在参照下列讨论以及本申请的附图来更详细地描述本发明,本发明提供了一种将诸如NFET和PFET之类的不同半导体器件形成到具有不同晶面的键合衬底上的方法。在这些附图中,相似的组成元件用相似的参考号来表示。
图2A示出了可以用于本发明的键合衬底10亦即混合衬底。如所示,键合衬底10包括表面介质层18、第一半导体层16、绝缘层14、以及第二半导体层12。键合衬底10还可以包括位于第二半导体层12下方的可选的第三半导体层(未示出)。在此可选的键合衬底中,另一绝缘层将第二半导体层12分隔于此可选的第三半导体层。
键合衬底10的表面介质层18是氧化物、氮化物、氮氧化物、或键合之前存在于初始晶片之一中的或者晶片键合之后由热工艺(例如氧化、氮化、或氮氧化)或由淀积形成在第一半导体层16顶部上的其它绝缘层。不管表面介质层18的起源如何,表面介质层18的厚度约为3-500nm,以约为5-20nm的厚度更为优选。
第一半导体层16由任何半导体材料组成,例如包括Si、SiC、SiGe、SiGeC、Ge合金、GaAs、InAs、InP、以及其它III/V或II/VI化合物半导体。第一半导体层16还可以包含预先形成的SOI衬底的SOI层或诸如Si/SiGe之类的层状半导体。第一半导体层16的特征还具有优选是为(110)的第一晶向。虽然(110)晶向是优选的,但第一半导体层16也可以具有(111)或(100)晶向。
第一半导体层16的厚度可以依赖于用来形成键合衬底10的初始晶片而变化。但典型地说,第一半导体层16的厚度约为5-500nm,以约为5-100nm的厚度更为优选。
依赖于用来产生键合衬底10的初始晶片,位于第一半导体层16与第二半导体层12之间的绝缘层14具有可变的厚度。但典型地说,绝缘层14的厚度约为1-5nm,以约为5-100nm更为优选。绝缘层14是键合之前形成在一个晶片或二个晶片上的氧化物或其它相似的绝缘材料。
第二半导体层12由任何半导体材料组成,可以与第一半导体层16相同或不同。于是,第二半导体层12可以包括例如Si、SiC、SiGe、SiGeC、Ge合金、GaAs、InAs、InP、以及其它III/V或II/VI化合物半导体。第二半导体层12还可以包含预先形成的SOI衬底的SOI层或诸如Si/SiGe之类的层状半导体。第二半导体层12的特征还具有不同于第一晶向的第二晶向。由于第一半导体层16优选是(110)表面,故第二半导体层12的晶向优选是(100)。虽然(100)晶向是优选的,但第二半导体层12也可以具有(111)或(110)晶体结构。
第二半导体层12的厚度可以依赖于用来形成键合衬底10的初始晶片而变化。但典型地说,第二半导体层12的厚度约为5-200μm,以约为5-100nm的厚度更为优选。
当存在可选的第三半导体层时,此可选的第三半导体层可以包含与第二半导体层相同的或不同的半导体材料。可选的第三半导体层的晶向典型地但不总是与第二半导体层相同。此可选的第三半导体层通常比第二半导体层12更厚。当存在可选的第三层时,绝缘层将可选的第三半导体层分隔于第二半导体层。
图2A所示的键合衬底10由键合在一起的二个半导体晶片组成。用来制作键合衬底10的二个晶片可以包括:二个SOI晶片(见图3A),其中,标注为1的晶片之一包括第一半导体层16,而标注为2的另一晶片包括第二半导体层12;一个SOI晶片(标注为2)和一个体半导体晶片(标注为1;见图3B);其上都包含绝缘层14的二个体半导体晶片(分别标注为1和2,见图3C);或者一个SOI晶片(标注为2)和一个体晶片(标注为1),此体晶片包括能够在键合过程中被用来分裂至少部分晶片之一的诸如H2注入区之类的离子注入区11(见图3D)。
借助于首先使二个晶片彼此紧密接触;可选地将外力施加到接触的晶片;然后在能够将二个晶片键合到一起的条件下对接触的晶片加热,来达到键合。可以在存在或不存在外力的情况下来执行此加热步骤。典型地在惰性气氛中,于大约200-1050℃的温度下,执行大约2-20小时的加热步骤。更优选的是在大约200-400℃的温度下,执行大约2-20小时的键合。在本发明中,术语“惰性气氛”被用来表示其中使用诸如He、Ar、N2、Xe、Kr之类的惰性气体或它们的混合物的气氛。键合工艺中使用的优选气氛是N2。
在采用二个SOI晶片的实施方案中,可以在键合之后,利用诸如化学机械抛光(CMP)或研磨和腐蚀之类的整平工艺,来清除至少SOI晶片之一的一些材料层。当达及表面介质层18时,此整平工艺就停止。
在晶片之一包括离子注入区的实施方案中,此离子注入区在键合过程中形成一个多孔区,使离子注入区上方的晶片部分剥离,留下如图1A所示的键合晶片。此离子注入区典型地由用本技术领域熟练人员众所周知的离子注入条件注入到晶片表面中的H2离子组成。
在待要键合的晶片中不包括介质层的实施方案中,可以用诸如氧化之类的热工艺,或用诸如化学气相淀积(CVD)、等离子体CVD、原子层淀积、化学溶液淀积之类的常规淀积工艺以及其它相似的淀积工艺,将表面介质层18形成在键合晶片的顶部上。
然后,在图2A的键合衬底10的预定部分上形成掩模20,以便保护部分键合衬底10,同时留下键合衬底10的其它部分不被保护。被保护的键合衬底10部分确定了结构的第一器件区22,而未被保护的键合衬底10部分确定了第二器件区24。在一个实施方案中,借助于将光抗蚀剂掩模涂敷到键合衬底10的整个表面,掩模20被形成在表面介质层18的预定部分上。在涂敷光抗蚀剂掩模之后,用光刻方法对掩模进行图形化,此光刻方法包括将光抗蚀剂暴露于辐射图形以及用抗蚀剂显影剂显影图形的步骤。得到的包括形成在键合衬底10的预定部分上的掩模20的结构,被示于例如图2B中。
在另一实施方案中,掩模20是用光刻和腐蚀方法形成和图形化的氮化物或氮氧化物层。在确定第二半导体器件区之后,可以清除氮化物或氮氧化物掩模20。
在对键合衬底10提供掩模20之后,对结构进行一个或多个腐蚀步骤,以便暴露第二半导体层12的表面。具体地说,本发明此时所用的一个或多个腐蚀步骤清除了表面介质层18的未被保护部分以及下方的部分第一半导体层16和将第一半导体层16分隔于第二半导体层12的部分绝缘层14。可以用单个腐蚀工艺来执行此腐蚀,或可以采用多个腐蚀步骤。本发明此时所用的腐蚀,可以包括诸如反应离子刻蚀、离子束腐蚀、等离子体腐蚀、或激光腐蚀之类的干法腐蚀工艺,其中采用化学腐蚀剂的湿法腐蚀工艺,或它们的任何组合。在本发明的优选实施方案中,反应离子刻蚀(RIE)被用来选择性地清除第二半导体器件区24中的表面介质层18、第一半导体层16、以及绝缘层14的未被保护的部分。在已经执行此腐蚀工艺之后得到的结构,被示于例如图2C中。注意,被保护的第一器件区22的侧壁,亦即表面介质层18、第一半导体层16、绝缘层14、以及第二半导体层12的侧壁在此腐蚀之后被暴露。如所示,层18、16、以及14的暴露侧壁与掩模20的最外边沿对准。
然后,利用常规的抗蚀剂剥离工艺,从图2C所示的结构清除掩模20,然后在暴露的侧壁上形成衬里即隔垫25。用淀积和腐蚀方法来形成此衬里即隔垫25。衬里即隔垫25由诸如氧化物之类的绝缘材料组成。
在形成衬里即隔垫25之后,半导体材料26被形成在暴露的第二半导体层12上。根据本发明,半导体材料26具有相同于第二半导体层12的晶向。得到的结构被示于例如图2D中。
半导体材料26可以包含能够用选择性外延生长方法形成的任何含硅的半导体,例如硅、应变硅、SiGe、SiC、SiGeC、或它们的组合。在某些优选实施方案中,半导体材料26由硅组成。在其它优选实施方案中,此半导体材料是位于弛豫的SiGe合金层顶部上的应变硅层。在本发明中,半导体材料26可以被称为再生长的半导体材料。
接着,对图2D所示的结构进行诸如化学机械抛光(CMP)或研磨之类的整平工艺,使半导体材料26的上表面与第一半导体层16的上表面基本上齐平。注意,在此整平工艺中,先前被保护的表面介质层18被清除了。
在提供基本上平坦的表面之后,诸如浅沟槽隔离区之类的隔离区27被典型地形成,以便将第一半导体器件区22隔离于第二半导体器件区24。利用包括例如沟槽确定和腐蚀;用扩散势垒可选地对沟槽进行衬里;以及用诸如氧化物之类的沟槽介质填充沟槽的本技术领域熟练人员众所周知的工艺步骤,来形成隔离区27。在沟槽填充之后,可以整平此结构,并可以执行可选的致密化工艺步骤,以便使沟槽介质致密。
得到的包含隔离区27的基本上平坦的结构被示于例如图2E中。如所示,图2E的结构包括第一晶向的暴露的第一半导体层16和晶向与第二半导体层12相同的未被暴露的再生长半导体材料26。图2F示出了在部分第一半导体层16上形成第一半导体器件30和在再生长半导体材料26上形成第二半导体器件32之后所形成的集成结构。尽管示出了在各个器件区中仅仅存在一个半导体器件,但本发明尝试了在特定器件区中形成多个各类型的器件。根据本发明,第一半导体器件可以是PFET或NFET,而第二半导体器件可以是NFET或PFET,但第一半导体器件必须不同于第二半导体器件,且特定的器件被制作在提供高性能器件的晶向上。利用本技术领域熟练人员众所周知的标准CMOS工艺步骤来制作这些PFET和NFET。各个FET包括栅介质、栅导体、位于栅导体顶部上的可选的硬掩模、位于至少栅导体侧壁上的隔垫、以及源/漏扩散区。在图2F中,扩散区被标注为34。注意,PFET被形成在具有(110)或(111)取向的半导体材料上,而NFET被形成在具有(100)或(111)取向的半导体表面上。
上面的描述以及图2A-2F示出了本发明的基本概念,它包括提供具有二个不同晶向的键合衬底,掩蔽,腐蚀,再生长,整平,以及器件制作。参照图4A-4J的下列描述示出了用来制作包含形成在(100)晶面上的二个NFET以及形成在(110)晶面上的位于二个NFET之间的一个PFET的高性能半导体器件的工艺步骤。
图4A示出了可以被用于本发明这一实施方案的键合衬底10。键合衬底10包括表面介质层18、第一半导体层16、绝缘层14、以及第二半导体层12。第三可选半导体层可以被置于第二半导体层12下方。在这样的实施方案中,绝缘层将第二半导体层分隔于可选的第三半导体层。
图4B示出了已经在表面介质层18上形成氮化物掩模20之后的结构。利用诸如CVD的常规淀积工艺来形成氮化物掩模20。
在形成氮化物掩模20之后,利用图形化的光抗蚀剂掩模和腐蚀,对掩模进行图形化,然后,经由另一腐蚀工艺,此图形从氮化物掩模20被转移到停止于第二半导体层12上表面顶部上的结构中。用于此第二腐蚀的腐蚀,清除了部分表面介质层18、第一半导体层16、以及绝缘层14。在将图形转移到键合衬底10中的过程中,执行了单个或多个腐蚀工艺。图4C示出了图形转移之后得到的结构。
接着,如图4D所示,隔垫25被形成在暴露的侧壁上。隔垫25由例如包括氧化物的绝缘材料组成。用淀积和腐蚀方法来形成位于被保护的第一器件区的侧壁上的隔垫25。
在形成隔垫25之后,半导体材料26被形成在第二半导体层12的暴露表面上,从而提供了例如图4E所示的结构。然后对图4E所示的结构进行整平,以便提供图4F所示的基本上平坦的结构。注意,整平步骤清除了先前未被腐蚀的氮化物掩模20和表面介质层18,以便提供其中第一半导体层16被暴露且再生长的半导体材料26被暴露的结构。暴露的第一半导体层16是其中要制作诸如NFET之类的第一半导体器件的区域,而半导体材料26的暴露表面是其中要制作诸如PFET之类的第二半导体器件的区域。
接着,如图4G所示,包含衬垫氧化物51和衬垫氮化物52的材料叠层50,被形成在图4F所示的基本上平坦的结构的顶部上。用热氧化工艺或用淀积方法,来形成材料叠层50的衬垫氧化物51,而用热氮化工艺或淀积方法来形成衬垫氮化物52。衬垫氮化物52典型地比衬垫下方的衬垫氧化物51更厚。
材料叠层50被用来确定隔离区27的沟槽窗口。图4H示出了已经将沟槽窗口29形成到图4G所示的结构中之后所形成的结构。用光刻和腐蚀的方法来形成这些沟槽窗口29。
在确定沟槽窗口29之后,用诸如氧化物之类的沟槽介质来填充沟槽窗口29,并将其整平到第一半导体层16和再生长半导体材料26。图4I示出了沟槽填充和整平之后所形成的结构。图4I所示的结构包括3个器件区;其中二个被称为第一器件区22,其中要形成第一半导体器件30,第三个是第二器件区24,其中要形成第二半导体器件32。
图4J示出了在部分第一半导体层16上形成第一半导体器件30以及在再生长的半导体材料26上形成第二半导体器件32之后所形成的集成结构。尽管示出了各个器件区中仅仅存在一个半导体器件,但本发明还尝试了在特定的器件区中形成多个各类型的器件。根据本发明,第一半导体器件可以是PFET(或NFET),而第二半导体器件可以是NFET(或PFET)。利用本技术领域熟练人员众所周知的标准CMOS工艺步骤,来制作这些PFET和NFET。各个FET包括栅介质、栅导体、位于栅导体顶部上的可选的硬掩模、位于至少栅导体侧壁上的隔垫、以及源/漏扩散区。注意,PFET被形成在具有(110)或(111)取向的表面上,而NFET被形成在具有(100)或(111)取向的表面上。在图4J所示的结构中,NFET是类SOI器件,而PFET是类体半导体器件。若第三半导体层存在于第二半导体层12下方,则所有3个器件都可以是类SOI器件。
图5A-5G示出了用来制作包含形成在(100)晶面上的二个NFET以及形成在(110)晶面上的位于二个NFET之间的一个PFET的高性能半导体器件的变通工艺步骤。此变通方法开始于形成图5A所示的键合衬底。此键合衬底10至少包括表面介质层18、第一半导体层16、绝缘层14、以及第二半导体层12。第三可选的半导体层可以被置于第二半导体层的下方。
接着,氮化物掩模20被形成在键合衬底10上,以便提供于5B所示的结构。在键合衬底10上形成氮化物掩模20之后,利用氮化物掩模20和表面介质18作为组合腐蚀掩模来形成隔离区27。借助于将光抗蚀剂涂敷到氮化物掩模20的表面、对光抗蚀剂进行图形化、以及将图形从光抗蚀剂转移到氮化物掩模20中然后到表面介质层18中,以暴露第一半导体层16,来形成隔离区27。暴露的第一半导体层16然后被腐蚀,停止于绝缘层14的上表面上。然后用沟槽介质填充此腐蚀步骤所形成的沟槽,并整平到氮化物掩模20的上表面。图5C示出了沟槽填充和整平之后的结构。确切地说,隔离区27被示于图5C中。
然后,各个隔离区之间的材料被清除,从而提供了图5D所示的结构。具体地说,借助于形成阻挡掩模以保护其中要形成第一半导体器件的结构部分,然后对氮化物掩模20、表面介质层18、以及第一半导体层16的未被保护的部分进行腐蚀,停止于绝缘层14上,来清除各个隔离区之间的材料。
然后,利用选择性地清除诸如氧化物的绝缘材料的腐蚀工艺,来清除绝缘层14的暴露部分,从而提供了例如图5E所示的结构。注意,此腐蚀步骤还降低了隔离区27的高度。此腐蚀步骤停止于第二半导体层12的上表面的顶部上。然后从此结构剥离其余的氮化物掩模20,并在第二半导体材料12的暴露表面上再生长半导体材料26,从而提供了例如图5F所示的结构。在此特定的实施方案中,再生长的半导体材料26包括应变硅的上层31。
然后从图5F所示的结构剥离氧化物,且应变硅31被形成在第一半导体层16的暴露部分上。在形成应变硅层之后,CMOS器件30和32被制作在提供高性能器件的各个晶向上。得到的包含形成在应变硅层顶部上的NFET和PFET的结构,被示于例如图5G中。
虽然对于其优选实施方案已经描述了本发明,但本技术领域的熟练人员可以理解的是,可以作出形式和细节方面的上述和其它的改变而不偏离本发明的构思与范围。因此认为本发明不局限于所述的正确形式和细节,而是在所附权利要求的范围内。
Claims (26)
1.一种在混合晶向衬底上制作CMOS器件的方法,它包括下列步骤:
提供键合衬底,它至少包括被绝缘层分隔开的第一晶向的第一半导体层和第二晶向的第二半导体层,所述第一晶向不同于所述第二晶向,且所述第一半导体层位于所述第二半导体层上方;
保护部分键合衬底,以便确定第一器件区,同时使键合衬底的另一部分不被保护,键合衬底的所述不被保护的部分确定了第二器件区;
对键合衬底的所述未被保护的部分进行腐蚀,以便暴露第二半导体层的表面;
在第二半导体层的所述暴露表面上再生长半导体材料,所述半导体材料的晶向与第二晶向相同;
对包含此半导体材料的键合衬底进行整平,使第一半导体层的上表面与此半导体材料的上表面基本上齐平;以及
在所述第一器件区中形成至少一个第一半导体器件,同时在所述第二器件区中的所述半导体材料上形成至少一个第二半导体器件。
2.权利要求1的方法,其中,所述键合衬底还包括位于所述第一半导体材料上的表面介质层。
3.权利要求1的方法,其中,所述键合衬底由二个绝缘体上硅(SOI)晶片、一个SOI晶片和一个体半导体晶片、二个体半导体晶片、或一个SOI晶片和一个包含在加热之后形成空洞的离子注入区的体半导体晶片构成。
4.权利要求1的方法,其中,通过使二个晶片彼此紧密接触,并在惰性气氛中对接触的晶片进行加热,形成所述键合衬底。
5.权利要求4的方法,其中,在大约200-1050℃的温度下执行所述加热大约2-20小时。
6.权利要求1的方法,其中,所述保护包括使用图形化的掩模。
7.权利要求6的方法,其中,所述图形化的掩模是图形化的光抗蚀剂、图形化的氮化物、或图形化的氮氧化物。
8.权利要求1的方法,其中,利用选择性外延生长方法来形成所述半导体材料。
9.权利要求1的方法,其中,所述半导体材料是选自硅、应变Si、SiGe、SiC、SiGeC、以及它们的组合的含硅半导体。
10.权利要求1的方法,其中,所述整平包括化学机械抛光或研磨。
11.权利要求1的方法,其中,在所述腐蚀与再生长步骤之间,衬里或隔垫被形成在暴露的侧壁上。
12.权利要求1的方法,还包括在腐蚀之后但在形成所述至少一个半导体器件之前形成隔离区。
13.权利要求1的方法,其中,所述半导体器件是NFET或PFET。
14.权利要求1的方法,其中,所述第一半导体层具有(110)晶向,而所述第二半导体层和半导体材料都具有(100)晶向。
15.权利要求14的方法,其中,第一半导体器件是PFET,而第二半导体器件是NFET。
16.权利要求1的方法,其中,所述半导体器件被制作在应变Si层上。
17.权利要求1的方法,其中,所述半导体材料包括位于弛豫SiGe合金层顶部上的应变Si层。
18.一种集成半导体结构,它包括:
键合衬底,它包括具有第一晶向的第一器件区和具有第二晶向的第二器件区,所述第一晶向不同于所述第二晶向;
隔离区,它将所述第一器件区分隔于所述第二器件区;以及
位于所述第一器件区的至少一个第一半导体器件和位于所述第二器件区的至少一个第二半导体器件。
19.权利要求18的集成半导体结构,其中,第一晶向是(110),而第二晶向是(100)。
20.权利要求19的集成半导体结构,其中,所述至少一个第一半导体器件是PFET,而所述至少一个第二半导体器件是NFET。
21.权利要求18的集成半导体结构,其中,第二器件区包括再生长的半导体材料。
22.权利要求21的集成半导体结构,其中,所述再生长的半导体材料是选自Si、应变Si、SiGe、SiC、SiGeC、以及它们的组合的含硅半导体。
23.权利要求18的集成半导体结构,其中,所述第一和第二半导体器件区都包括应变Si。
24.权利要求22的集成半导体结构,其中,所述再生长的半导体材料包括位于弛豫SiGe合金或SiC合金顶部上的应变Si层。
25.权利要求18的集成半导体结构,其中,所述隔离区位于侧壁隔垫上。
26.一种集成半导体结构,它包括至少二种器件,其中,至少器件之一位于对此器件最佳的第一晶面上,而另一器件位于对所述另一器件最佳的不同于第一晶面的第二晶面上。
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WO2012155833A1 (zh) * | 2011-05-16 | 2012-11-22 | 中国科学院上海微系统与信息技术研究所 | 一种全隔离混合晶向soi的制备方法 |
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CN102226989A (zh) * | 2011-06-16 | 2011-10-26 | 中国电子科技集团公司第二十四研究所 | 混合晶向硅衬底的制造方法 |
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CN106104758A (zh) * | 2014-03-17 | 2016-11-09 | 硅存储技术公司 | 体/soi混合衬底上的嵌入式存储器器件及制造其的方法 |
CN107507806A (zh) * | 2016-06-14 | 2017-12-22 | 西安电子科技大学 | 基于沟道晶向选择的压应变Si CMOS器件及其制备方法 |
CN107507806B (zh) * | 2016-06-14 | 2020-06-05 | 西安电子科技大学 | 基于沟道晶向选择的压应变Si CMOS器件及其制备方法 |
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US20040256700A1 (en) | 2004-12-23 |
JP4931211B2 (ja) | 2012-05-16 |
WO2004114400A1 (en) | 2004-12-29 |
KR20060021314A (ko) | 2006-03-07 |
TWI318785B (en) | 2009-12-21 |
JP2006527915A (ja) | 2006-12-07 |
US7713807B2 (en) | 2010-05-11 |
TW200503176A (en) | 2005-01-16 |
US20080096330A1 (en) | 2008-04-24 |
EP1639637A1 (en) | 2006-03-29 |
IL172517A0 (en) | 2006-04-10 |
KR100843489B1 (ko) | 2008-07-04 |
US7329923B2 (en) | 2008-02-12 |
CN100407408C (zh) | 2008-07-30 |
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