CN1667828A - 集成电路结构及其制作方法 - Google Patents
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Abstract
本发明公开了一种具有至少两种晶体取向的衬底的集成电路结构。第一种晶体管在具有第一种晶体取向的衬底第一部分上，并且第二种晶体管在具有第二种晶体取向的衬底第二部分上。应变层在所述第一种晶体管和所述第二种晶体管上方。此外，应变层在第一种晶体管上方变形并在第二种晶体管上方驰豫。
Description
技术领域
本发明涉及半导体器件，并且更具体地说涉及在混合晶体取向衬底上形成的集成半导体器件，例如绝缘体上硅(SOI)/互补金属氧化物半导体(CMOS)器件。更具体地说，本发明提供了一种在具有不同晶体学取向的键合衬底(bonded substrate)上集成至少两种半导体器件，例如NFETs和PFETs的方法。键合衬底上每种器件的位置取决于特定晶体取向上器件的性能。举例来说，本发明在(100)表面上形成NFETs，而在(110)表面上形成PFETs。(100)晶面为NFETs提供高的性能，而(110)晶面为PFETs提供高的性能。
背景技术
在当前半导体技术中，典型地在具有单晶取向的半导体，例如Si的晶片上制造CMOS器件，例如NFETs或PFETs。具体地说，当今大多数半导体器件都是在具有(100)晶体取向的Si上制造的。
公知电子对于(100)Si表面取向具有高的迁移率，但是空穴对于(110)表面取向具有高的迁移率。也就是说，空穴在(100)Si上的迁移率值比该晶体取向上相应的电子空穴迁移率低大约2-4倍。为了补偿这种差异，典型地设计具有较大宽度的PFETs，从而对NFET上拉电流(pull-down currents)和下拉电流(pull-up currents)并且实现均匀的电路开关。因为占据大量的芯片面积，所以具有较大宽度的NFETs是不可取的。
另一方面，空穴在(110)Si的迁移率比(100)Si上高两倍；因此，在(110)表面上形成的PFETs将表现出显著高于在(100)表面上形成的PFETs的驱动电流。不幸地是与(100)Si表面相比，电子在(110)Si表面上的迁移率显著降低。举例来说，图1中表示了电子在(110)Si表面上的迁移率降低。在图1中，实线表示电子迁移率，虚线表示空穴迁移率。
从上面的讨论和图1中可以推断出(110)Si表面因其优异的空穴迁移率对于PFET器件是最优的，但是这种晶体取向完全不适合于NFET器件。相反，因为晶体取向有利于电子迁移率，(100)Si表面对于NFET器件是最优的。
从上面来看，需要提供在具有不同晶体取向的衬底上形成并且对于具体器件提供最优性能的集成半导体器件。也就是说，迫切需要制造一种衬底，允许在其某个晶体学表面，例如(110)表面上形成一种器件，举例来说如PFET，而在另一种晶体学表面，例如(100)表面上形成另一种器件，举例来说如NFET。
发明内容
本发明公开了一种通过在第二衬底结构上键合第一衬底结构而形成叠层结构来开始形成集成电路结构的方法。因此，叠层结构在第二种晶体取向的第二衬底上具有第一种晶体取向的第一衬底。本发明在叠层结构上向着第二衬底刻蚀第一开口。然后，从第二衬底上生长附加材料来填充第一开口。这样在叠层结构上面制造出衬底，其第一部分具有第一种类型的晶体取向，并且第二部分具有第二种类型的晶体取向。此外，衬底的第一部分可以包含非浮置(non-floating)衬底部分，并且衬底的第二部分包含浮置(floating)衬底部分。
在衬底的第一部分上面形成第一种晶体管(例如N或P型)，并且在衬底的第二部分上面形成第二种晶体管。第一种晶体管与第二种晶体管互补。第一种晶体管和第二种晶体管包含互补金属氧化物半导体(CMOS)晶体管和鳍式场效应晶体管(FinFETs)之一。本发明在第一种晶体管和第二种晶体管上形成应变层。
这样就制造出衬底具有两种晶体取向的集成电路结构。第一种晶体管在具有第一种晶体取向的衬底第一部分上，并且第二种晶体管在具有第二种晶体取向的衬底第二部分上。应变层在第一种晶体管和第二种晶体管上方。此外，应变层可以在第一种晶体管上变形并在第二种晶体管上驰豫。
第一种晶体管和第二种晶体管包括硅化区，并且应变层在硅化区上方。第一种晶体管和第二种晶体管包括在衬底内部形成的源极区和漏极区，以及在源极区和漏极区之间的衬底上方形成的栅极导体，并且在栅极导体和源极及漏极区上方形成硅化区。
因此，本发明提供了一种对于N型晶体管下面的衬底部分使用有利于N型晶体管的晶体取向类型，以及对于P型晶体管下面的衬底部分使用有利于P型晶体管的不同晶体取向类型的结构。这就允许在具有有利于每种晶体管的晶体取向的不同类型衬底上形成每种晶体管。此外，本发明可以选择性地在任一类型或者两种类型的晶体管上包括应变产生层，从而允许每种不同类型的晶体管接受最有利于每种晶体管的应变类型。
本发明的这些和其它方面和目的在考虑结合下面的说明书和附图时将更好领会和理解。但是，应当理解下面表示本发明优选的实施方案及其大量具体细节的说明书只是出于举例说明而非限制性地给出。可以在本发明的范围内做出许多变化和修改，而不会背离其精神，并且本发明包括所有这种修改。
附图说明
参考附图，从下面详细的说明中，将更容易理解本发明。附图中：
图1是Vgs＝1V时μeff对Si衬底晶体取向的图。
图2A-2H是举例说明本发明中使用的在键合衬底不同晶体取向平面上形成集成CMOS器件的基本加工步骤的图示(剖视图)。
图3A-3D是可以键合在一起并且在图2A-2E所述的方法中使用的各种晶片的图示。
图4A-4J是举例说明在形成高性能半导体器件中使用的基本加工步骤的图示(剖视图)，所述半导体器件包括两个在(100)晶面上形成的NFETs和位于所述NFETs之间并在(110)晶面上形成的PFET。
图5A-5F是举例说明在形成高性能半导体器件中使用的可选加工步骤的图示(剖视图)，所述半导体器件包括两个在(100)晶面上形成的NFETs和位于所述NFETs之间并在(110)晶面上形成的PFET。
具体实施方式
参照在附图中举例说明并且在下面的说明书中详述的非限制性实施方案，本发明及其各个特征与有利的细节将被更完全地解释。应当指出在附图中举例说明的特征不一定是按比例绘制的。省略了公知部件和加工技术的说明，以至于不会不必要地使本发明变得模糊。本文使用的实例仅打算便于理解本发明被实践的方式，并且能够使本领域技术人员实践本发明。因此，这些实例不会限制本发明的范围。
现在参照下面的讨论以及本发明的附图更详细地描述本发明，本发明提供了一种在具有不同晶体取向的键合衬底上形成不同半导体器件，例如NFETs和PFETs的方法。在附图中，相同和相应的元件由相同的参考数字表示。
图2A举例说明了可以在本发明中使用的键合衬底10，即混合衬底。如图所示，键合衬底10包括表面介质层18、第一半导体层16、绝缘层14和第二半导体层12。键合衬底10还可以在第二半导体层12的下方包括可选的第三半导体层(未显示)。在可选的键合衬底中，另一个绝缘层隔离第二半导体层12与可选的第三半导体层。
键合衬底10的表面介质层18是氧化物、氮化物、氧氮化物，或者其它绝缘层，所述绝缘层或者是键合前的初始晶片之一，或者在通过热过程(即氧化、氮化或者氧氮化)或沉积在键合晶片后形成在第一半导体层16的上面。不管表面介质层18的来源，表面介质层18的厚度从约3至约500纳米，并且从约5至20纳米的厚度是更加优选的。
第一半导体层16由任何半导体材料组成，举例来说包括Si、SiC、SiGe、SiGeC、Ge合金、GaAs、InAs、InP，以及其它III/V或II/VI化合物半导体。第一半导体层16还可以包含预先形成的SOI衬底的SOI层，或者层状半导体，例如Si/SiGe。第一半导体层16还具有优选为(110)的第一晶体取向的特征。尽管(110)晶体取向是优选的，但是第一半导体层16可以具有(111)或者(100)的晶体取向。
第一半导体层16的厚度可以根据用于形成键合衬底10的起始晶片而变化。但是，典型地第一半导体层16的厚度为从约3至约500纳米，并且从约5至100纳米的厚度是更加优选的。
位于第一半导体层16和第二半导体层12之间的绝缘层14根据用于产生键合衬底10的初始晶片而具有可变的厚度。但是，典型地绝缘层14的厚度为从约1至约5纳米，并且从约5至100纳米的厚度是更加优选的。绝缘层14是在键合前于一个或两个晶片上形成的氧化物或其它类似的绝缘体。
第二半导体层12由任何与第一半导体层16相同或不同的半导体材料组成。因此，第二半导体层12举例来说包括Si、SiC、SiGe、SiGeC、Ge合金、GaAs、InAs、InP，以及其它III/V或II/VI化合物半导体。第二半导体层12还可以包含预先形成的SOI衬底的SOI层，或者层状半导体，例如Si/SiGe。第二半导体层12还具有与第一晶体取向不同的的第二晶体取向的特征。因为第一半导体层16优选为(110)衬底，所以第二半导体层12的晶体取向优选为(100)。尽管(100)晶体取向是优选的，但是第二半导体层12可以具有(111)或者(110)的晶体取向。
第二半导体层12的厚度可以根据用于形成键合衬底10的起始晶片而变化。但是，典型地第二半导体层12的厚度为从约5纳米至约200微米，并且从约5至100纳米的厚度是更加优选的。
当存在可选的第三半导体层时，可选的第三半导体层可以包含与第二半导体层12相同或不同的半导体材料。可选的第三半导体层的晶体取向典型地，但并不总是与第二半导体层相同。可选的第三半导体层通常比第二半导体层12更厚。当存在可选的第三半导体层时，绝缘层将可选的第三半导体层与第二半导体层隔开。
图2A举例说明的键合衬底10由键合在一起的两片半导体晶片组成。在制造键合衬底10中使用的两片晶片包括两片SOI晶片(参阅图3)，其中标识为1的一个晶片包括第一半导体层16，并且标识为2的另一个晶片包括第二半导体层12；SOI晶片(标识为2)和本体半导体晶片(标识为1，参阅图3B)；两个上面都含有绝缘层14的本体半导体晶片(分别标识为1和2，参阅图3C)；或者SOI晶片(标识为2)和包括离子注入区11，例如H2注入区的本体晶片(标识为1)，所述区域可以用来在键合时分开至少一个晶片的一部分(参阅图3D)。
通过如下方法实现键合：首先将两个晶片彼此紧密接触；可选地对接触的晶片施加外力；然后在能够将两个晶片键合在一起的条件下加热两个接触的晶片。加热步骤可以在存在外力或者不存在外力的情况下实施。加热步骤典型地惰性环境中于从约200℃至约1050℃下实施从约2至约20小时的时间。更优选地，在从约200℃至约400℃下实施键合从约2至约20小时的时间。本发明中使用术语“惰性环境”表示其中使用惰性气体，例如He、Ar、N2、Xe、Kr或者它们的混合物的气氛。键合过程期间使用的优选环境是N2。
在使用两个SOI晶片的实施方案中，在键合后可以使用平面化工艺，例如化学机械抛光(CMP)或者研磨和刻蚀方法除去至少一个SOI晶片的一些材料层。
在其中晶片之一包括离子注入区的实施方案中，离子注入区在键合时形成多孔区，引起离子注入区上面的晶片部分脱落，留下键合晶片，举例来说如图1A所示。离子注入区典型地包括使用本领域技术人员公知的离子注入条件而注入晶片表面的H2离子。
在待键合的晶片中不包括电介质层的实施方案中，通过热过程，例如氧化，或者通过常规沉积过程，例如化学气相沉积(CVD)、等离子体增强CVD、原子层沉积、化学溶液沉积，以及其它类似的沉积过程在键合的晶片上面形成表面介质层18。
然后，在图2A的键合衬底10的预定部分上形成掩模20，从而保护部分键合衬底10，而不保护另一部分键合衬底10。键合衬底10的保护部分定义了所述结构的第一器件区22，而键合衬底10的未保护部分定义了第二器件区24。在一个实施方案中，通过向键合衬底10的整个表面上施用光刻胶掩模而在表面介质层18的预定部分上形成掩模20。在施用了光刻胶掩模后，通过光刻图案化掩模，其包括使光刻胶曝光成辐射图案和使用抗蚀剂显影剂显影图案的步骤。所得的包括在键合衬底10预定部分上形成的掩模20的结构举例来说如图2B所示。
在另一个实施方案中，掩模20是使用光刻和刻蚀形成并图案化的氮化物或氧氮化物。在定义了第二半导体器件的区域后，可以除去氮化物或氧氮化物掩模20。
在给键合衬底10提供了掩模20后，所述结构接受一次或多次刻蚀步骤，从而暴露出第二半导体层12的表面。具体地说，在本发明此处使用的一次或多次刻蚀步骤除去了表面介质层18的未保护部分，以及第一半导体层16的下面部分和隔离第一半导体层16与第二半导体层12的一部分绝缘层14。使用一步刻蚀过程来实施刻蚀，或者可以使用多个刻蚀步骤。本发明此处使用的刻蚀包括干法刻蚀，例如反应离子蚀刻、离子束刻蚀、等离子体刻蚀或者激光刻蚀，以及其中使用化学试剂的湿法刻蚀，或者它们的任何组合。在本发明优选的实施方案中，使用反应离子刻蚀(RIE)来选择性除去第二半导体器件区24中表面介质层18、第一半导体器件层16和绝缘层14的未保护部分。已经实施了刻蚀过程后的所得结构举例来说如图2C所示。注意在该刻蚀步骤后暴露出保护的第一器件区22，即表面介质层18、第一半导体层16、绝缘层14和第二半导体器件层12的侧壁。如图所示，层18、16和14暴露的侧壁与掩模20的最外边对准。
然后，使用传统的抗蚀剂剥离过程从图2C中所示的结构中除去掩模20，并且在暴露的侧壁上形成衬里或间隔25。通过沉积和刻蚀来形成衬里或间隔25。衬里或间隔25由绝缘材料组成，举例来说如氧化物。
在形成衬里或间隔25后，在暴露的第二半导体层12上形成半导体材料26。根据本发明，半导体材料26具有与第二半导体层12的晶体取向相同的的晶体取向。所得的结构举例来说如图2D所示。
半导体材料26可以包含任何含Si的半导体，例如Si、应变Si、SiGe、SiC、SiGeC或者其组合，所述材料可以使用选择性外延生长方法来形成。在一些优选的实施方案中，半导体材料26由Si组成。在其它优选的实施方案中，半导体材料是位于驰豫SiGe合金层上方的应变Si层。在本发明中，半导体材料26可以称作再生长的半导体材料。
接下来，图2D中所示的结构接受平面化过程，例如化学机械抛光(CMP)或者研磨，以至于半导体材料26的上表面基本上与第一半导体层16的上表面成平面。注意在所述平面化过程后，除去前面表面介质层18的保护部分。
在提供基本上平的平面后，典型地形成隔离区27，例如浅沟槽隔离区，从而隔离第一半导体器件区22与第二半导体器件区24。使用本领域技术人员公知的加工步骤来形成隔离区27，例如包括沟槽定义和刻蚀；可选地用扩散阻挡层作沟槽的衬里；及用沟槽电介质，例如氧化物填充沟槽。在沟槽填充后，所述结构被平面化，并且实施可选的致密化过程步骤来致密化沟槽电介质。
所得包含隔离区27的基本上平面的结构举例来说如图2E所示。如图所示，图2E的结构包括暴露的第一晶体取向的第一半导体层16和与第二半导体层12具有相同晶体取向的未暴露的再生长的半导体材料26。
另外，图2E举例说明了在不同类型的衬底16、26上方形成的应变层21。根据所用的具体衬底，在这一阶段加工中可以使用能够产生应变的任何类型层。应变层21可以产生增强电子迁移率并降低空穴迁移率的拉伸型应变，或者具有相反作用的压缩型应变。举例来说，公知Si3N4能够在硅衬底中根据用来在晶片上沉积薄膜所使用的详细工艺而产生张力或压缩型应力。
尽管附图示例说明在两种衬底16、26上方形成的应变产生层21，本发明也可在形成产生应变层时遮掩一种衬底，从而仅使一种类型的衬底变形。另外，本发明通过大量的技术来驰豫应变层21。举例来说，形成掩模来保护应该保持应变的衬底，并且暴露出应该使应变驰豫的衬底部分。然后，实施离子注入，使应变产生层21暴露部分中的应变驰豫。
图2F表示在部分第一半导体层16上形成第一半导体器件30，并且在再生长的半导体材料26上形成第二半导体器件区32后所形成的集成结构。尽管表示出在每个器件区仅存在一个半导体器件，但是本发明打算在特定的器件区形成多个每种类型的器件。根据本发明，在第一半导体器件与第二半导体器件不同并且在提供高性能器件的晶体取向上制造特定器件的条件下，第一半导体器件可以是PFET或NFET，而第二半导体器件可以是NFET或PFET。使用本领域技术人员公知的标准CMOS加工步骤来形成PFETs和NFETs。每个FET包括栅极电介质、栅极导体、位于栅极导体上方的可选硬质掩模、位于至少栅极导体侧壁上的间隔，以及源极/漏极扩散区。扩散区在图2F中标记为34。注意在具有(110)或者(111)取向的半导体材料上形成PFET，而在具有(100)或者(111)取向的半导体表面上形成NFET。
图2G举例说明了本发明的另一个实施方案，其中代替形成如图2E和2F中所示的应变层21，在形成了晶体管的源极/漏极和栅极后形成应变层23。在本实施方案中，在硅化源极/漏极区34和栅极导体32后形成应变层23。本实施方案对图2H的鳍式场效应晶体管(FinFETs)尤其有用。更具体地说，对于FinFETs，鳍从不同的硅衬底16、26形成，并且在硅化鳍后形成应变层23。
上述描述和图2A-2H举例说明了本发明的基本概念，其包括提供具有两个不同晶体取向的键合衬底、遮掩、刻蚀、再生长、平面化和器件形成。下面参照图4A-4J的说明举例说明在形成高性能半导体器件时使用的加工步骤，所述器件包含在(100)晶面上形成的两个NFETs，以及位于NFETs之间并在(110)晶面上形成的一个PFET。
图4A举例说明了可以在本发明本实施方案中使用的键合衬底10。键合衬底10包括表面介质层18、第一半导体层16、绝缘层14和第二半导体层12。可选的第三半导体层位于第二半导体层12的下方。在该实施方案中，绝缘层14隔离第二半导体层和可选的第三半导体层。
图4B举例说明了在表面介质层18上已经形成了氮化物掩模20的结构。使用传统的沉积过程，例如CVD来形成氮化物掩模20。
在氮化物掩模20的形成后，使用图案化的光刻胶掩模并且刻蚀来图案化掩模，然后借助另一个刻蚀过程将图案从氮化物掩模20转移成位于第二半导体层12的上表面层上的结构。在第二次刻蚀中使用的刻蚀除去了部分表面介质层18、第一半导体层16和绝缘层14。实施一步或多步刻蚀过程将图案转移成键合衬底10。图4C表示了图案转移后所得的结构。
接下来，如图4D所示，在暴露的侧壁上形成间隔25。间隔25由举例来说包括氧化物的绝缘材料组成。通过沉积和刻蚀来形成位于保护的第一器件区侧壁上的间隔25。
在形成间隔25后，在第二半导体层12暴露的表面上形成半导体材料26，提供例如图4E中所示的结构。同上述的应变层21一样，本实施方案还可以使用应变层41。两个应变层的性质是相似的。然后，平面化如图4E所示的结构，提供如图4F所示的基本上为平面的结构。注意平面化步骤除去了先前未被刻蚀的氮化物掩模20和表面介质层18，从而提供暴露出第一半导体层16并且暴露出再生长的半导体材料26的结构。暴露的第一半导体层16是其中将要形成诸如NFET的第一半导体器件的区域，而半导体材料26暴露的表面是将要形成诸如PFET的第二半导体器件的区域。
接下来，如图4G所示，在图4F所示的基本上为平面的结构上面形成包含衬垫氧化物(pad oxide)51和衬垫氮化物(pad nitride)52的材料叠层50。材料叠层50的衬里氧化物51通过热氧化过程或者沉积来形成，而衬里氮化物52通过热氮化过程或沉积来形成。衬垫氮化物52典型比底下的衬垫氧化物51更厚。在定义用于隔离区27的沟槽开口时使用材料叠层50。图4H举例说明了在沟槽开口29已经被形成图4G所示的结构中之后形成的结构。通过光刻和蚀刻形成沟槽开口29。
在定义了沟槽开口29后，用例如氧化物的沟槽电介质填充沟槽开口29，并且平面化至第一半导体层16和再生长的半导体材料26。图4I在沟槽填充并平面化后形成的结构。图4I中所示的结构包括三个器件区；其中两个称作其中将要形成第一半导体器件30的第一器件区22，并且第三个是其中将要形成第二半导体器件32的第三器件区24。
图4J表示在第一半导体层16的一部分上形成了第一半导体器件区30，并且在再生长的半导体材料26上形成了第二半导体器件32之后形成的集成结构。尽管表示在每个器件区只存在一个半导体器件，但是本发明打算在特定的器件区形成多个每种类型的器件。根据本发明，第一半导体器件可以是PFET(或NFET)，而第二半导体器件可以是NFET(或PFET)。使用本领域技术人员公知的标准CMOS加工步骤来形成PFETs和NFETs。每个FET包括栅极电介质、栅极导体、位于栅极导体上方的可选硬质掩模、位于至少栅极导体侧壁上的间隔，以及源极/漏极扩散区。注意在具有(110)或者(111)取向的半导体材料上形成PFET，而在具有(100)或者(111)取向的半导体表面上形成NFET。在图4J所示的结构中，NFETs是SOI类器件，而PFET是块类(bulk-like)半导体器件。如果在第二半导体层12下方存在第三半导体层，那么所有三个器件将是SOI类。
图5A-5F举例说明了在形成高性能半导体器件中使用的加工步骤，所述器件包含在(100)晶面上形成的两个NFETs，以及一个位于NFETs之间并在(110)晶面上形成的PFET。可选的方法首先形成如图5A所示的键合衬底。键合衬底10包括表面介质层18、第一半导体层16、绝缘层14和第二半导体层12。可选的第三半导体层位于第二半导体层的下方。
接下来，在所述键合衬底10上形成氮化物掩模20，提供如图5B所示的结构。在于键合衬底10上形成了氮化物掩模20后，使用氮化物掩模20和表面介质18作为组合刻蚀掩模，形成隔离区27。隔离区27如下形成：向氮化物掩模20的表面上施用光刻胶，图案化光刻胶并且将光刻胶的图案转移到氮化物掩模20上，然后转移至表面介质层18内，从而暴露出第一半导体层16。然后，刻蚀暴露出的第一半导体层16，在绝缘层14的上表面上停止。然后，用沟槽电介质填充由刻蚀步骤形成的沟槽，并且平面化至氮化物掩模20的上表面。图5C表示了沟槽填充和平面化后的结构。具体地说，隔离区27如图5C所示。
然后，除去隔离区之间的材料，提供如图5D所示的结构。具体地说，通过形成阻挡掩模，保护该结构将要形成第一半导体器件的部分，然后刻蚀氮化物掩模20、表面介质层18和保持在绝缘层14上的第一半导体层16的未保护部分，从而除去隔离区之间的材料。
然后，使用选择性除去绝缘体材料，例如氧化物的刻蚀过程来除去绝缘层14的暴露部分，提供举例来说如图5E所示的结构。注意该刻蚀步骤还降低了隔离区27的高度。该刻蚀步骤在第二半导体层12的上表面上停止。然后，从所述结构上剥离残留的氮化物掩模20，然后在第二半导体材料12的暴露表面上再生长半导体材料26，提供举例来说如图5F所示的结构。在这个具体的实施方案中，再生长的半导体材料26包括应变Si 31的上层。
然后，从图5F所示的结构中剥离氧化物，并且在第一半导体层16的暴露部分上形成应变Si 31。在形成应变的Si层后，在提供高性能器件的各自晶体取向上形成CMOS器件30和32。
因此，如上所述，本发明提供了一种通过在第二衬底结构上键合第一衬底结构而形成叠层结构来开始形成集成电路结构的方法。本发明在叠层结构中刻蚀第一开口至第二衬底。然后，从第二衬底上生长附加材料来填充第一开口。这样在叠层结构上面制造出衬底，其第一部分具有第一种类型的晶体取向，并且第二部分具有第二种类型的晶体取向。在衬底的第一部分上面形成第一种晶体管(例如N或P型)，并且在衬底的第二部分上面形成第二种晶体管。本发明在第一种晶体管和第二种晶体管上面形成应变层。
这样就制造出衬底具有两种晶体取向的集成电路结构。第一种晶体管在具有第一种晶体取向的衬底第一部分上，并且第二种晶体管在具有第二种晶体取向的衬底第二部分上。应变层在第一种晶体管和第二种晶体管上方。此外，应变层可以在第一种晶体管上变形并在第二种晶体管上驰豫。
第一种晶体管和第二种晶体管包括硅化区，并且应变层在硅化区上面。第一种晶体管和第二种晶体管包括在衬底内部形成的源极和漏极区，以及在源极和漏极区之间的衬底上方形成的栅极导体，并且在栅极导体和源极及漏极区上方形成硅化区。
因此，本发明提供了一种对于N型晶体管下面的衬底部分使用有利于N型晶体管的晶体取向类型，并且对于P型晶体管下面的衬底部分使用有利于P型晶体管的不同晶体取向类型的结构。这就允许在具有有利于每种晶体管的晶体取向的不同类型衬底上形成每种晶体管。此外，本发明可以选择性地在任一类型或者两种类型的晶体管上包括应变产生层，从而允许每种不同类型的晶体管接受最有利于每种晶体管的应变类型。
本发明在nFETs和pFETs中提供了更高的迁移率载流子，从而导致CMOS电路增加的开关速率和/或更低功率的操作。这些FETs增加的线性还为使用这种器件的类似电路提供了利益。
尽管已经以优选实施方案的方式说明了本发明，本领域技术人员将认识到可以在附加权利要求的精神和范围内的修改下实践本发明。
Claims (20)
1、一种集成电路结构，其包含：
具有至少两种晶体取向的衬底；
在具有第一种晶体取向的所述衬底第一部分上形成的第一种晶体管；
在具有第二种晶体取向的所述衬底第二部分上形成的第二种晶体管；及
在所述第一种晶体管和所述第二种晶体管上方的应变层。
2、权利要求1的结构，其中所述第一种晶体管和所述第二种晶体管包括硅化区，并且所述应变层在所述硅化区上方。
3、权利要求1的结构，其中所述第一种晶体管和所述第二种晶体管包括在所述衬底内部形成的源极区和漏极区，以及在所述源极区和漏极区之间的所述衬底上方形成的栅极导体，并且
其中在所述栅极导体和所述源极区和漏极区上方形成所述硅化区。
4、权利要求1的结构，其中所述第一种晶体管与所述第二种晶体管互补。
5、权利要求1的结构，其中所述衬底的所述第一部分包含非浮置衬底部分，并且所述衬底的所述第二部分包含浮置衬底部分。
6、权利要求1的结构，其中所述应变层在所述第一种晶体管上方变形并在所述第二种晶体管上方驰豫。
7、权利要求1的结构，其中所述第一种晶体管和所述第二种晶体管包含平面互补金属氧化物半导体晶体管和鳍式场效应晶体管之一。
8、一种集成电路结构，其包含：
具有至少两种晶体取向的衬底；
在具有第一种晶体取向的所述衬底第一部分上形成的N型场效应晶体管；
在具有第二种晶体取向的所述衬底第二部分上形成的P型场效应晶体管；及
在所述N型场效应晶体管和所述P型场效应晶体管上方的应变层。
9、权利要求8的结构，其中所述N型场效应晶体管和所述P型场效应晶体管包括硅化区，并且所述应变层在所述硅化区上方。
10、权利要求9的结构，其中所述N型场效应晶体管和所述P型场效应晶体管包括在所述衬底内部形成的源极区和漏极区，以及在所述源极区和漏极区之间的所述衬底上方形成的栅极导体，并且
其中在所述栅极导体和所述源极区和漏极区上方形成所述硅化区。
11、权利要求8的结构，其中所述N型场效应晶体管与所述P型场效应晶体管互补。
12、权利要求8的结构，其中所述衬底的所述第一部分包含非浮置衬底部分，并且所述衬底的所述第二部分包含浮置衬底部分。
13、权利要求8的结构，其中所述应变层在所述N型场效应晶体管上方变形并在所述P型场效应晶体管上方驰豫。
14、权利要求8的结构，其中所述N型场效应晶体管和所述P型场效应晶体管包含平面互补金属氧化物半导体晶体管和鳍式场效应晶体管之一。
15、一种形成集成电路结构的方法，所述方法包含：
在第二衬底结构上键合第一衬底结构，从而形成在第二晶体取向的第二衬底上方具有第一晶体取向的第一衬底的叠层结构；
在所述叠层结构中向下刻蚀第一开口至所述第二衬底；
在所述第二衬底上生长附加材料来填充第一开口，从而在所述叠层结构上面制造衬底，其第一部分具有所述第一种类型的晶体取向，并且第二部分具有所述第二种类型的晶体取向；
在所述衬底的所述第一部分上方形成第一种晶体管；
在所述衬底的所述第二部分上方形成第二种晶体管；及
在所述第一种晶体管和所述第二种晶体管上方形成应变层。
16、权利要求15的方法，其进一步包含在所述第一种晶体管和所述第二种晶体管上形成硅化区，其中所述应变层形成在所述硅化区上方。
17、权利要求16的方法，其中所述形成第一种晶体管和所述形成第二种晶体管的所述形成步骤包括在所述衬底内部形成源极区和漏极区，以及在所述源极区和漏极区之间的所述衬底上方形成栅极导体，其中在所述栅极导体和所述源极区和漏极区上方形成所述硅化区。
18、权利要求15的方法，其中所述第一种晶体管与所述第二种晶体管互补。
19、权利要求15的方法，其进一步包含在位于所述第二种晶体管上方的所述应变层部分中驰豫应变。
20、权利要求15的方法，其中所述第一种晶体管和所述第二种晶体管包含平面互补金属氧化物半导体晶体管和鳍式场效应晶体管之一。
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| CN102549747B (zh) * | 2009-10-16 | 2019-03-22 | 国家半导体公司 | 使用结合选择性外延生长的混合定向技术(hot)提高迁移率的方法及相关设备 |
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|---|---|
| TW200601561A (en) | 2006-01-01 |
| US20050199984A1 (en) | 2005-09-15 |
| TWI343649B (en) | 2011-06-11 |
| JP2005260240A (ja) | 2005-09-22 |
| US20060065954A1 (en) | 2006-03-30 |
| US7498216B2 (en) | 2009-03-03 |
| CN100367503C (zh) | 2008-02-06 |
| US6995456B2 (en) | 2006-02-07 |
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