JP2005260240A - ハイブリッド結晶方位基板上の集積回路構造及び形成方法(高性能cmossoiデバイス) - Google Patents
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
【解決手段】少なくとも2タイプの結晶方位を有する基板を備える集積回路構造を開示する。第1のタイプのトランジスタは、第1のタイプの結晶方位を有する基板の第1の部分の上に位置し、第2のタイプのトランジスタは、第2のタイプの結晶方位を有する基板の第2の部分の上に位置する。第1のタイプのトランジスタおよび第2のタイプのトランジスタの上には、歪み発生層がある。さらに、歪み発生層は、第1のタイプのトランジスタの上では歪み、第2のタイプのトランジスタの上では緩和することができる。
【選択図】図8
Description
12 第2の半導体層
14 絶縁層
16 第1の半導体層
18 表面誘電体層
20 マスク
21 歪み発生層
22 第1のデバイス領域
24 第2のデバイス領域
25 スペーサ(ライナ)
26 半導体材料
27 分離領域
29 トレンチ開口
30 第1の半導体デバイス
31 歪Si層
32 第2の半導体デバイス
34 ソース/ドレイン拡散領域
Claims (20)
- 少なくとも2タイプの結晶方位を有する基板と、
第1のタイプの結晶方位を有する前記基板の第1の部分の上に形成された第1のタイプのトランジスタと、
第2のタイプの結晶方位を有する前記基板の第2の部分の上に形成された第2のタイプのトランジスタと、
前記第1のタイプのトランジスタおよび前記第2のタイプのトランジスタの上に位置する歪み発生層とを含む、集積回路構造。 - 前記第1のタイプのトランジスタおよび前記第2のタイプのトランジスタがシリサイド領域を含み、前記歪み発生層が前記シリサイド領域の上に位置する、請求項1に記載の構造。
- 前記第1のタイプのトランジスタおよび前記第2のタイプのトランジスタが、前記基板内に形成されたソース領域およびドレイン領域と、前記基板の上の、前記ソース領域と前記ドレイン領域の間に形成されたゲート導体とを含み、
前記シリサイド領域が、前記ゲート導体ならびに前記ソース領域および前記ドレイン領域の上に形成される、請求項2に記載の構造。 - 前記第1のタイプのトランジスタが、前記第2のタイプのトランジスタと相補的である、請求項1に記載の構造。
- 前記基板の前記第1の部分が非浮遊基板部分を含み、前記基板の前記第2の部分が浮遊基板部分を含む、請求項1に記載の構造。
- 前記歪み発生層が、前記第1のタイプのトランジスタの上では歪み、前記第2のタイプのトランジスタの上では緩和される、請求項1に記載の構造。
- 前記第1のタイプのトランジスタおよび前記第2のタイプのトランジスタが、平面相補型金属酸化膜半導体(CMOS)トランジスタおよびフィン型電界効果トランジスタ(FinFET)のうち一方を含む、請求項1に記載の構造。
- 少なくとも2タイプの結晶方位を有する基板と、
第1のタイプの結晶方位を有する前記基板の第1の部分の上に形成されたN型電界効果トランジスタ(NFET)と、
第2のタイプの結晶方位を有する前記基板の第2の部分の上に形成されたP型電界効果トランジスタ(PFET)と、
前記NFETおよび前記PFETの上に位置する歪み発生層とを含む、集積回路構造。 - 前記NFETおよび前記PFETがシリサイド領域を含み、前記歪み発生層が前記シリサイド領域の上に位置する、請求項8に記載の構造。
- 前記NFETおよび前記PFETが、前記基板内に形成されたソース領域およびドレイン領域と、前記基板の上の、前記ソース領域と前記ドレイン領域の間に形成されたゲート導体とを含み、
前記シリサイド領域が、前記ゲート導体ならびに前記ソース領域および前記ドレイン領域の上に形成される、請求項9に記載の構造。 - 前記NFETが、前記PFETと相補的である、請求項8に記載の構造。
- 前記基板の前記第1の部分が非浮遊基板部分を含み、前記基板の前記第2の部分が浮遊基板部分を含む、請求項8に記載の構造。
- 前記歪み発生層が、前記NFET(N型)の上では歪み、前記PFETの上では緩和される、請求項8に記載の構造。
- 前記NFETおよび前記PFETが、平面相補型金属酸化膜半導体(CMOS)トランジスタおよびフィン型電界効果トランジスタ(FinFET)のうち一方を含む、請求項8に記載の構造。
- 集積回路構造を形成する方法であって、
第2の基板構造上に第1の基板構造を接合して、第1の結晶方位を有する第1の基板を第2の結晶方位を有する第2の基板の上に備える積層構造を形成するステップと、
前記積層構造に、前記第2の基板まで延びる第1の開口をエッチングにより形成するステップと、
前記第2の基板上にさらに別の材料を成長させて前記第1の開口を充填して、前記積層構造の上部に、前記第1のタイプの結晶方位を有する第1の部分および前記第2のタイプの結晶方位を有する第2の部分を有する基板を形成するステップと、
前記基板の前記第1の部分の上に第1のタイプのトランジスタを形成するステップと、
前記基板の前記第2の部分の上に第2のタイプのトランジスタを形成するステップと、
前記第1のタイプのトランジスタおよび前記第2のタイプのトランジスタの上に歪み発生層を形成するステップとを含む方法。 - 前記第1のタイプのトランジスタおよび前記第2のタイプのトランジスタの上にシリサイド領域を形成するステップをさらに含み、前記歪み発生層が前記シリサイド領域の上に形成される、請求項15に記載の方法。
- 前記第1のタイプのトランジスタを形成する前記ステップおよび前記第2のタイプのトランジスタを形成する前記ステップが、前記基板内にソース領域およびドレイン領域を形成し、前記基板上の、前記ソース領域と前記ドレイン領域の間にゲート導体を形成することを含み、前記シリサイド領域が、前記ゲート導体ならびに前記ソース領域および前記ドレイン領域の上に形成される、請求項16に記載の方法。
- 前記第1のタイプのトランジスタが、前記第2のタイプのトランジスタと相補的である、請求項15に記載の方法。
- 前記歪み発生層の、前記第2のタイプのトランジスタの上に位置する部分において歪みを緩和するステップをさらに含む、請求項15に記載の方法。
- 前記第1のタイプのトランジスタおよび前記第2のタイプのトランジスタが、平面相補型金属酸化膜半導体(CMOS)トランジスタおよびフィン型電界効果トランジスタ(FinFET)のうち一方を含む、請求項15に記載の方法。
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Also Published As
Publication number | Publication date |
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US20050199984A1 (en) | 2005-09-15 |
US20060065954A1 (en) | 2006-03-30 |
CN100367503C (zh) | 2008-02-06 |
CN1667828A (zh) | 2005-09-14 |
US7498216B2 (en) | 2009-03-03 |
US6995456B2 (en) | 2006-02-07 |
TWI343649B (en) | 2011-06-11 |
TW200601561A (en) | 2006-01-01 |
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