CN102790004A - 一种全隔离混合晶向soi的制备方法 - Google Patents
一种全隔离混合晶向soi的制备方法 Download PDFInfo
- Publication number
- CN102790004A CN102790004A CN2011101255589A CN201110125558A CN102790004A CN 102790004 A CN102790004 A CN 102790004A CN 2011101255589 A CN2011101255589 A CN 2011101255589A CN 201110125558 A CN201110125558 A CN 201110125558A CN 102790004 A CN102790004 A CN 102790004A
- Authority
- CN
- China
- Prior art keywords
- crystal orientation
- silicon
- top layer
- soi substrate
- orientation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000013078 crystal Substances 0.000 title claims abstract description 144
- 238000002955 isolation Methods 0.000 title claims abstract description 56
- 238000002360 preparation method Methods 0.000 title claims abstract description 24
- 239000012212 insulator Substances 0.000 title abstract description 3
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 101
- 239000010703 silicon Substances 0.000 claims abstract description 101
- 239000000463 material Substances 0.000 claims abstract description 22
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 14
- 229920005591 polysilicon Polymers 0.000 claims abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 73
- 238000005516 engineering process Methods 0.000 claims description 19
- 238000005260 corrosion Methods 0.000 claims description 9
- 230000007797 corrosion Effects 0.000 claims description 9
- 239000011810 insulating material Substances 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 69
- 239000004065 semiconductor Substances 0.000 abstract description 10
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 5
- 150000004706 metal oxides Chemical class 0.000 abstract description 5
- 230000000295 complement effect Effects 0.000 abstract description 3
- 238000013508 migration Methods 0.000 abstract 1
- 230000005012 migration Effects 0.000 abstract 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-NJFSPNSNSA-N silicon-30 atom Chemical compound [30Si] XUIMIQQOPSSXEZ-NJFSPNSNSA-N 0.000 description 4
- 239000002210 silicon-based material Substances 0.000 description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- KAATUXNTWXVJKI-UHFFFAOYSA-N cypermethrin Chemical compound CC1(C)C(C=C(Cl)Cl)C1C(=O)OC(C#N)C1=CC=CC(OC=2C=CC=CC=2)=C1 KAATUXNTWXVJKI-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 125000000896 monocarboxylic acid group Chemical group 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
- Thin Film Transistor (AREA)
Abstract
本发明公开了一种全隔离混合晶向SOI衬底的制备方法,以及基于该方法的CMOS集成电路制备方法。本发明提出的全隔离混合晶向SOI衬底制备方法,采用SiGe层作为第一晶向外延的虚拟衬底层,从而可以形成第一晶向的顶层应变硅;采用多晶硅支撑材料作为连接第一晶向的顶层应变硅与第二晶向的顶层硅的支撑,从而可去除第一晶向顶层应变硅下方的SiGe层,填充绝缘材料形成绝缘埋层。该方法形成的顶层硅和绝缘埋层厚度均匀、可控,窗口内形成的应变硅与窗口外的顶层硅具有不同晶向,可分别为NMOS及PMOS提供更高的迁移率,从而提升了CMOS集成电路的性能。
Description
技术领域
本发明涉及一种半导体器件衬底的制备方法,尤其涉及一种全隔离混合晶向SOI衬底的制备方法,属于半导体器件制造领域。
背景技术
互补金属氧化物半导体(CMOS,Complementary Metal Oxide Semiconductor)器件是将N沟道金属氧化物半导体晶体管(NMOS)与P沟道金属氧化物半导体晶体管(PMOS)集成在同一块衬底上的半导体器件。随着CMOS技术的不断发展,如何控制器件稳定性、提高器件性能已成为器件尺寸不断缩小所面临的日益严重的挑战。SOI(Silicon On Insulator)是指绝缘体上硅技术,由于SOI技术减小了源漏的寄生电容,SOI电路的速度相对传统体硅电路的速度有显著的提高,同时SOI还具有短沟道效应小,很好的抗闭锁性,工艺简单等一系列优点,因此SOI技术已逐渐成为制造高速、低功耗、高集成度和高可靠超大规模硅集成电路的主流技术。SOI通常由以下三层构成:薄的单晶硅顶层,在其上形成集成电路;相当薄的埋层氧化层(BOX,buried oxide),即绝缘二氧化硅中间层;非常厚的体型衬底硅衬底层,其主要作用是为上面的两层提供机械支撑。由于SOI结构中氧化层把其上的硅膜层与体型衬底硅衬底层分隔开来,因此大面积的p-n结将被介电隔离(dielectric isolation)取代。源极(sourceregion)和漏极(drain region)向下延伸至埋层氧化层,有效减少了漏电流和结电容。
此外,在Si材料中,空穴迁移率在(110)晶面Si衬底中与传统的(100)晶面Si衬底相比增加一倍以上;而电子迁移率在(100)晶面Si衬底中是最高的。当前CMOS集成电路的NMOS和PMOS都制作在(100)晶面的硅衬底上,由于(100)晶面Si衬底具有最高的电子迁移率,比其空穴迁移率约高2-4倍,这就需要设计较大栅宽的PMOS以平衡NMOS,难以得到更高性能的CMOS器件与电路。为了充分利用载流子迁移率依赖于Si表面晶向的优势,IBM公司的Yang等人开发出一种采用混合晶体取向Si衬底制造CMOS电路的新技术。Yang M,leongM,Shi L等人于2003年在《Digest of Technical Paper of International Flectron DevicesMeeting》杂志上发表的文章《High performance CMOS fabricated on hybrid substrate withdifferent crystal orientations》中介绍了他们的技术。其通过键合和选择性外延技术,NMOS器件制作在具有埋层氧化层的(100)晶面Si表面上,而PMOS器件制作在(110)晶面Si上,使PMOS器件性能取得极大提高。当Ioff=100nA/μm,(110)衬底上的PMOS器件驱动电流提高了45%。其缺点是制作在外延层上的PMOS器件没有埋层氧化层将其与衬底隔离,因而器件性能还是受到影响。美国专利号为US2007/0281446A1的专利文献公开了一种混合晶向SOI衬底的制作方法,通过刻蚀沟槽暴露底层硅,采用横向外延选择性工艺从底层硅外延出与原(100)顶层硅不同晶向的(110)硅材料,从而得到具有混合晶向的SOI衬底,该方法制作工艺复杂,其(110)硅材料是通过底层硅直接外延得到。然而,随着器件的特征尺寸进一步缩小,普通硅材料较低的空穴迁移率将成为提高器件性能的瓶颈之一。
为了进一步提升CMOS集成电路的性能,本发明将提出一种新的全隔离的混合晶向SOI衬底技术,在实现混合晶向SOI衬底的同时提供应变硅材料,可分别为NMOS及PMOS提供更高迁移率的衬底。
发明内容
本发明要解决的技术问题在于提供一种全隔离混合晶向SOI衬底的制备方法,以及基于该方法的CMOS集成电路制备方法。
为了解决上述技术问题,本发明采用如下技术方案:
一种全隔离混合晶向SOI衬底的制备方法,包括以下步骤:
步骤一、提供一片SOI衬底,所述SOI衬底包括第一晶向的底层硅、位于所述底层硅之上的绝缘埋层以及位于所述绝缘埋层之上的第二晶向的顶层硅;
步骤二、在所述SOI衬底上刻蚀出窗口,所述窗口使部分底层硅暴露,然后在所述窗口的四周侧壁形成侧墙隔离结构;
步骤三、在形成有侧墙隔离结构的窗口内外延第一晶向的SiGe层,然后在所述SiGe层上继续外延第一晶向的顶层硅;
步骤四、刻蚀掉所述窗口其中相对两侧的部分侧墙隔离结构,露出部分底层硅,然后在部分侧墙隔离结构被刻蚀掉的位置沉积支撑材料,作为连接第一晶向的顶层硅与第二晶向的顶层硅的支撑;
步骤五、刻蚀掉剩余的侧墙隔离结构,然后采用选择性腐蚀工艺去除所述SiGe层,使第一晶向的顶层硅下方悬空;
步骤六、填充绝缘材料在第一晶向的顶层硅下方形成第二绝缘埋层;
步骤七、去除在所述第一晶向的顶层硅四周的绝缘材料和支撑材料,并在所述第一晶向的顶层硅四周制作浅沟槽隔离结构,最终得到全隔离混合晶向SOI衬底。
作为本发明的优选方案,步骤二在所述SOI衬底上形成第一硬掩膜,再刻蚀出窗口。步骤七先去除所述第一硬掩膜,再制作第二硬掩膜覆盖SOI衬底表面,然后通过刻蚀去除在所述第一晶向的顶层硅四周的绝缘材料和支撑材料,在所述第一晶向的顶层硅四周制作浅沟槽隔离结构,并通过热磷酸腐蚀去除第二硬掩膜,最终得到全隔离混合晶向SOI衬底。
作为本发明的优选方案,所述第一晶向是指(110)晶向,所述第二晶向是指(100)晶向;或者所述第一晶向是指(100)晶向,所述第二晶向是指(110)晶向。
作为本发明的优选方案,所述支撑材料为多晶硅。
作为本发明的优选方案,步骤六通过化学气相沉积的方法在第一晶向的顶层硅下方填充绝缘材料形成第二绝缘埋层。
作为本发明的优选方案,所述第一晶向顶层硅可以是具有第一晶向的应变硅或非应变硅,取决于外延生长的厚度。
一种基于全隔离混合晶向SOI衬底的CMOS集成电路的制备方法,包括以下步骤:
步骤一、提供一片SOI衬底,所述SOI衬底包括第一晶向的底层硅、位于所述底层硅之上的绝缘埋层以及位于所述绝缘埋层之上的第二晶向的顶层硅;
步骤二、在所述SOI衬底上刻蚀出窗口,所述窗口使部分底层硅暴露,然后在所述窗口的四周侧壁形成侧墙隔离结构;
步骤三、在形成有侧墙隔离结构的窗口内外延第一晶向的SiGe层,然后在所述SiGe层上继续外延第一晶向的顶层硅;
步骤四、刻蚀掉所述窗口其中相对两侧的部分侧墙隔离结构,露出部分底层硅,然后在部分侧墙隔离结构被刻蚀掉的位置沉积支撑材料,作为连接第一晶向的顶层硅与第二晶向的顶层硅的支撑;
步骤五、刻蚀掉剩余的侧墙隔离结构,然后采用选择性腐蚀工艺去除所述SiGe层,使第一晶向的顶层硅下方悬空;
步骤六、填充绝缘材料在第一晶向的顶层硅下方形成第二绝缘埋层;
步骤七、去除在所述第一晶向的顶层硅四周的绝缘材料和支撑材料,并在所述第一晶向的顶层硅四周制作浅沟槽隔离结构,最终得到全隔离混合晶向SOI衬底;
步骤八、在所得全隔离混合晶向SOI衬底的第一晶向的顶层硅上制作第一导电型MOS器件;在所得全隔离混合晶向SOI衬底的第二晶向的顶层硅上制作第二导电型MOS器件。
作为本发明的优选方案,所述第一晶向为(110)晶向则所述第一导电型MOS器件为PMOS器件;所述第二晶向为(100)晶向则所述第二导电型MOS器件为NMOS器件。
作为本发明的优选方案,所述第一晶向为(100)晶向则所述第一导电型MOS器件为NMOS器件,所述第二晶向为(110)晶向则所述第二导电型MOS器件为PMOS器件。
本发明的有益效果在于:
本发明提出的全隔离混合晶向SOI衬底制备方法,采用SiGe层作为第一晶向外延的虚拟衬底层,从而可以形成第一晶向的应变硅;采用多晶硅支撑材料作为连接第一晶向的顶层硅与第二晶向的顶层硅的支撑,从而可去除第一晶向应变硅下方的SiGe层,填充绝缘材料形成绝缘埋层。该方法形成的顶层硅和绝缘埋层厚度均匀、可控,窗口内形成的应变硅与窗口外的顶层硅具有不同晶向,可分别为NMOS及PMOS提供更高的迁移率,从而提升了CMOS集成电路的性能。
附图说明
图1-12为本发明实施例一中全隔离混合晶向SOI衬底制备方法的流程示意图;
其中,图5b是沿图5a中A-A’方向的剖视图;图6b是沿图6a中A-A’方向的剖视图,图6c是沿图6b中B-B’方向的剖视图;图7b是沿图7a中A-A’方向的剖视图,图7c是沿图7b中B-B’方向的剖视图;图8b是沿图8a中A-A’方向的剖视图,图8c是沿图8b中B-B’方向的剖视图;图9b是沿图9a中A-A’方向的剖视图,图9c是沿图9b中B-B’方向的剖视图;图10b是沿图10a中A-A’方向的剖视图,图10c是沿图10b中B-B’方向的剖视图;
图13为本发明实施例二中CMOS集成电路制备的示意图。
具体实施方式
下面结合附图进一步说明本发明的具体实施步骤,为了示出的方便附图并未按照比例绘制。
实施例一
参阅图1-12,本发明提出的全隔离混合晶向SOI衬底的制备方法,具体实施步骤如下:
步骤一、如图1所示,提供一片SOI衬底,所述SOI衬底包括第一晶向的底层硅10、位于所述底层硅10之上的绝缘埋层20以及位于所述绝缘埋层20之上的第二晶向的顶层硅30;所述SOI衬底即混合晶向的SOI衬底,其中所述第一晶向和第二晶向可以分别为(110)晶向和(100)晶向,或者(100)晶向和(110)晶向,在本实施例中,第一晶向优选为(110)晶向;第二晶向优选为(100)晶向。
步骤二、如图2-3所示,在所述SOI衬底上形成第一硬掩膜40,硬掩膜40优先选用氮化硅,然后刻蚀出窗口,所述窗口使部分底层硅10暴露,然后在所述窗口的四周侧墙形成侧墙隔离结构50,其材料优选二氧化硅或氮化硅。
步骤三、如图4所示,在形成有侧墙隔离结构50的窗口内外延第一晶向的SiGe层60,然后在所述SiGe层60上继续外延第一晶向的顶层硅70,并经化学机械抛光处理。
步骤四、如图5a和图5b所示,刻蚀掉所述窗口其中相对两侧的部分侧墙隔离结构50,露出部分底层硅10;然后如图6a、图6b和图6c所示,在部分侧墙隔离结构50被刻蚀掉的位置沉积支撑材料80,连接第一晶向的顶层硅70与第二晶向的顶层硅30。所述支撑材料80优选为多晶硅。
步骤五、如图7a、图7b和图7c所示,刻蚀掉剩余的侧墙隔离结构50,然后如图8a、图8b和图8c所示,采用选择性腐蚀工艺去除所述SiGe层60,使第一晶向的顶层硅70下方悬空,而第一晶向的顶层硅70的两侧通过支撑材料80多晶硅与顶层硅30连接用以支撑,所述SiGe选择性腐蚀用通过HF:H2O2,HF:H2O2:CH3COOH,H2O2:NH4OH,HF:HNO3:CH3COOH等湿法腐蚀,或其他干法腐蚀实现。
步骤六、如图9a、图9b和图9c所示,通过化学气相沉积等方法填充绝缘材料,在第一晶向的顶层硅70下方形成第二绝缘埋层90。
步骤七、如图10a、图10b和图10c所示,用热磷酸腐蚀先去除所述第一硬掩膜40,再制作第二硬掩膜100覆盖SOI衬底表面,然后如图11和图12所示,通过刻蚀去除在所述第一晶向的顶层硅70四周的绝缘材料和支撑材料,形成浅沟槽STI,并通过高密度等离子沉积的方法在所述浅沟槽内沉积绝缘材料110’,最后通过化学机械抛光去除第二硬掩膜100之上的110’,并通过热磷酸腐蚀去除第二硬掩膜110,在第一晶向的顶层硅70四周得到浅沟槽隔离结构110,最终得到全隔离混合晶向SOI衬底。
实施例二
在实施例一的基础上,制备基于上述全隔离混合晶向SOI衬底的CMOS集成电路,包括以下步骤:
如图13所示,在所得全隔离混合晶向SOI衬底的第一晶向的顶层硅70上制作第一导电型MOS器件;在所得全隔离混合晶向SOI衬底的第二晶向的顶层硅30上制作第二导电型MOS器件。其中,所述第一晶向优选为(110)晶向则所述第一导电型MOS器件为PMOS器件;所述第二晶向优选为(100)晶向则所述第二导电型MOS器件为NMOS器件。而当第一晶向为(100)晶向时则所述第一导电型MOS器件应为NMOS器件,当第二晶向为(110)晶向时则所述第二导电型MOS器件应为PMOS器件,这样能分别为NMOS及PMOS提供更高的迁移率,从而提升CMOS集成电路的性能。
上述实施例仅列示性说明本发明的原理及功效,而非用于限制本发明。任何熟悉此项技术的人员均可在不违背本发明的精神及范围下,对上述实施例进行修改。因此,本发明的权利保护范围,应如权利要求书所列。
Claims (10)
1.一种全隔离混合晶向SOI衬底的制备方法,其特征在于,包括以下步骤:
步骤一、提供一片SOI衬底,所述SOI衬底包括第一晶向的底层硅、位于所述底层硅之上的绝缘埋层以及位于所述绝缘埋层之上的第二晶向的顶层硅;
步骤二、在所述SOI衬底上刻蚀出窗口,所述窗口使部分底层硅暴露,然后在所述窗口的四周侧壁形成侧墙隔离结构;
步骤三、在形成有侧墙隔离结构的窗口内外延第一晶向的SiGe层,然后在所述SiGe层上继续外延生长第一晶向的顶层硅;
步骤四、刻蚀掉所述窗口其中相对两侧的部分侧墙隔离结构,露出部分底层硅,然后在部分侧墙隔离结构被刻蚀掉的位置沉积支撑材料,作为连接第一晶向的顶层硅与第二晶向的顶层硅的支撑;
步骤五、刻蚀掉剩余的侧墙隔离结构,然后采用选择性腐蚀工艺去除所述SiGe层,使第一晶向的顶层硅下方悬空;
步骤六、填充绝缘材料在第一晶向的顶层硅下方形成第二绝缘埋层;
步骤七、去除在所述第一晶向的顶层硅四周的绝缘材料和支撑材料,并在所述第一晶向的顶层硅四周制作浅沟槽隔离结构,最终得到全隔离混合晶向SOI衬底。
2.根据权利要求1所述的全隔离混合晶向SOI衬底的制备方法,其特征在于:步骤二在所述SOI衬底上形成第一硬掩膜,再刻蚀出窗口。
3.根据权利要求2所述的全隔离混合晶向SOI衬底的制备方法,其特征在于:步骤七先去除所述第一硬掩膜,再制作第二硬掩膜覆盖SOI衬底表面,然后通过刻蚀去除在所述第一晶向的顶层硅四周的绝缘材料和支撑材料,在所述第一晶向的顶层硅四周制作浅沟槽隔离结构,并去除第二硬掩膜,最终得到全隔离混合晶向SOI衬底。
4.根据权利要求1所述的全隔离混合晶向SOI衬底的制备方法,其特征在于:所述第一晶向是指(110)晶向,所述第二晶向是指(100)晶向;或所述第一晶向是指(100)晶向,所述第二晶向是指(110)晶向。
5.根据权利要求1所述的全隔离混合晶向SOI衬底的制备方法,其特征在于:所述支撑材料为多晶硅。
6.根据权利要求1所述的全隔离混合晶向SOI衬底的制备方法,其特征在于:步骤六通过化学气相沉积的方法在第一晶向的顶层硅下方填充绝缘材料形成第二绝缘埋层。
7.根据权利要求1所述的全隔离混合晶向SOI衬底的制备方法,其特征在于:所述第一晶向顶层硅是具有第一晶向的应变硅或非应变硅。
8.一种基于全隔离混合晶向SOI衬底的CMOS集成电路的制备方法,其特征在于,包括以下步骤:
步骤一、提供一片SOI衬底,所述SOI衬底包括第一晶向的底层硅、位于所述底层硅之上的绝缘埋层以及位于所述绝缘埋层之上的第二晶向的顶层硅;
步骤二、在所述SOI衬底上刻蚀出窗口,所述窗口使部分底层硅暴露,然后在所述窗口的四周侧壁形成侧墙隔离结构;
步骤三、在形成有侧墙隔离结构的窗口内外延第一晶向的SiGe层,然后在所述SiGe层上继续外延第一晶向的顶层硅;
步骤四、刻蚀掉所述窗口其中相对两侧的部分侧墙隔离结构,露出部分底层硅,然后在部分侧墙隔离结构被刻蚀掉的位置沉积支撑材料,作为连接第一晶向的顶层硅与第二晶向的顶层硅的支撑;
步骤五、刻蚀掉剩余的侧墙隔离结构,然后采用选择性腐蚀工艺去除所述SiGe层,使第一晶向的顶层硅下方悬空;
步骤六、填充绝缘材料在第一晶向的顶层硅下方形成第二绝缘埋层;
步骤七、去除在所述第一晶向的顶层硅四周的绝缘材料和支撑材料,并在所述第一晶向的顶层硅四周制作浅沟槽隔离结构,最终得到全隔离混合晶向SOI衬底;
步骤八、在所得全隔离混合晶向SOI衬底的第一晶向的顶层硅上制作第一导电型MOS器件;在所得全隔离混合晶向SOI衬底的第二晶向的顶层硅上制作第二导电型MOS器件。
9.根据权利要求8所述的基于全隔离混合晶向SOI衬底的CMOS集成电路的制备方法,其特征在于:所述第一晶向为(110)晶向则所述第一导电型MOS器件为PMOS器件,所述第二晶向为(100)晶向则所述第二导电型MOS器件为NMOS器件。
10.根据权利要求8所述的基于全隔离混合晶向SOI衬底的CMOS集成电路的制备方法,其特征在于:所述第一晶向为(100)晶向则所述第一导电型MOS器件为NMOS器件,所述第二晶向为(110)晶向则所述第二导电型MOS器件为PMOS器件。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110125558.9A CN102790004B (zh) | 2011-05-16 | 2011-05-16 | 一种全隔离混合晶向soi的制备方法 |
US13/636,126 US8501577B2 (en) | 2011-05-16 | 2012-05-16 | Preparation method for full-isolated SOI with hybrid crystal orientations |
PCT/CN2012/075554 WO2012155833A1 (zh) | 2011-05-16 | 2012-05-16 | 一种全隔离混合晶向soi的制备方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110125558.9A CN102790004B (zh) | 2011-05-16 | 2011-05-16 | 一种全隔离混合晶向soi的制备方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102790004A true CN102790004A (zh) | 2012-11-21 |
CN102790004B CN102790004B (zh) | 2014-06-11 |
Family
ID=47155374
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201110125558.9A Expired - Fee Related CN102790004B (zh) | 2011-05-16 | 2011-05-16 | 一种全隔离混合晶向soi的制备方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8501577B2 (zh) |
CN (1) | CN102790004B (zh) |
WO (1) | WO2012155833A1 (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103745952A (zh) * | 2013-12-25 | 2014-04-23 | 上海新傲科技股份有限公司 | 带有绝缘埋层的混晶衬底的制备方法 |
WO2016113640A1 (en) * | 2015-01-13 | 2016-07-21 | International Business Machines Corporation | Strain release in pfet regions |
CN107039459A (zh) * | 2016-02-03 | 2017-08-11 | 上海硅通半导体技术有限公司 | Soi和体硅混合晶圆结构及其制备方法 |
CN114267628A (zh) * | 2021-03-24 | 2022-04-01 | 青岛昇瑞光电科技有限公司 | 超薄绝缘体上硅(soi)衬底基片及其制备方法 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9396948B2 (en) * | 2013-05-03 | 2016-07-19 | Texas Instruments Incorporated | Layer transfer of silicon onto III-nitride material for heterogenous integration |
US9525053B2 (en) | 2013-11-01 | 2016-12-20 | Samsung Electronics Co., Ltd. | Integrated circuit devices including strained channel regions and methods of forming the same |
US9490161B2 (en) | 2014-04-29 | 2016-11-08 | International Business Machines Corporation | Channel SiGe devices with multiple threshold voltages on hybrid oriented substrates, and methods of manufacturing same |
US9728640B2 (en) * | 2015-08-11 | 2017-08-08 | International Business Machines Corporation | Hybrid substrate engineering in CMOS finFET integration for mobility improvement |
CN111370399B (zh) * | 2018-12-25 | 2023-12-29 | 广东美的白色家电技术创新中心有限公司 | 智能功率模块、制备方法及装置 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4888300A (en) * | 1985-11-07 | 1989-12-19 | Fairchild Camera And Instrument Corporation | Submerged wall isolation of silicon islands |
CN1722363A (zh) * | 2004-04-22 | 2006-01-18 | 国际商业机器公司 | 制造应变含硅混合衬底的方法以及含硅混合衬底 |
CN1836323A (zh) * | 2003-06-17 | 2006-09-20 | 国际商业机器公司 | 混合晶向衬底上的高性能cmos soi器件 |
CN101044621A (zh) * | 2004-11-01 | 2007-09-26 | 先进微装置公司 | 具有不同晶向硅层的绝缘体上硅半导体装置以及形成该绝缘体上硅半导体装置的方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0957515A1 (en) * | 1998-05-15 | 1999-11-17 | STMicroelectronics S.r.l. | Method for manufacturing an SOI wafer |
US7029964B2 (en) * | 2003-11-13 | 2006-04-18 | International Business Machines Corporation | Method of manufacturing a strained silicon on a SiGe on SOI substrate |
JP2006041422A (ja) * | 2004-07-30 | 2006-02-09 | Seiko Epson Corp | 半導体基板、半導体装置、半導体基板の製造方法および半導体装置の製造方法 |
JP2008541421A (ja) * | 2005-05-03 | 2008-11-20 | エヌエックスピー ビー ヴィ | 半導体デバイスの製造方法および該製造方法により得られた半導体デバイス |
US7432149B2 (en) * | 2005-06-23 | 2008-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS on SOI substrates with hybrid crystal orientations |
US7803670B2 (en) * | 2006-07-20 | 2010-09-28 | Freescale Semiconductor, Inc. | Twisted dual-substrate orientation (DSO) substrates |
JP4285536B2 (ja) * | 2006-12-19 | 2009-06-24 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
-
2011
- 2011-05-16 CN CN201110125558.9A patent/CN102790004B/zh not_active Expired - Fee Related
-
2012
- 2012-05-16 WO PCT/CN2012/075554 patent/WO2012155833A1/zh active Application Filing
- 2012-05-16 US US13/636,126 patent/US8501577B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4888300A (en) * | 1985-11-07 | 1989-12-19 | Fairchild Camera And Instrument Corporation | Submerged wall isolation of silicon islands |
CN1836323A (zh) * | 2003-06-17 | 2006-09-20 | 国际商业机器公司 | 混合晶向衬底上的高性能cmos soi器件 |
CN1722363A (zh) * | 2004-04-22 | 2006-01-18 | 国际商业机器公司 | 制造应变含硅混合衬底的方法以及含硅混合衬底 |
CN101044621A (zh) * | 2004-11-01 | 2007-09-26 | 先进微装置公司 | 具有不同晶向硅层的绝缘体上硅半导体装置以及形成该绝缘体上硅半导体装置的方法 |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103745952A (zh) * | 2013-12-25 | 2014-04-23 | 上海新傲科技股份有限公司 | 带有绝缘埋层的混晶衬底的制备方法 |
CN103745952B (zh) * | 2013-12-25 | 2016-04-06 | 上海新傲科技股份有限公司 | 带有绝缘埋层的混晶衬底的制备方法 |
WO2016113640A1 (en) * | 2015-01-13 | 2016-07-21 | International Business Machines Corporation | Strain release in pfet regions |
US9543323B2 (en) | 2015-01-13 | 2017-01-10 | International Business Machines Corporation | Strain release in PFET regions |
US9761610B2 (en) | 2015-01-13 | 2017-09-12 | International Business Machines Corporation | Strain release in PFET regions |
GB2550740A (en) * | 2015-01-13 | 2017-11-29 | Ibm | Strain release in PFET regions |
US9966387B2 (en) | 2015-01-13 | 2018-05-08 | International Business Machines Corporation | Strain release in pFET regions |
GB2550740B (en) * | 2015-01-13 | 2020-05-20 | Ibm | Strain release in PFET regions |
CN107039459A (zh) * | 2016-02-03 | 2017-08-11 | 上海硅通半导体技术有限公司 | Soi和体硅混合晶圆结构及其制备方法 |
CN114267628A (zh) * | 2021-03-24 | 2022-04-01 | 青岛昇瑞光电科技有限公司 | 超薄绝缘体上硅(soi)衬底基片及其制备方法 |
Also Published As
Publication number | Publication date |
---|---|
US8501577B2 (en) | 2013-08-06 |
US20130071993A1 (en) | 2013-03-21 |
WO2012155833A1 (zh) | 2012-11-22 |
CN102790004B (zh) | 2014-06-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102790004B (zh) | 一种全隔离混合晶向soi的制备方法 | |
US6680240B1 (en) | Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide | |
US8703565B2 (en) | Bottom-notched SiGe FinFET formation using condensation | |
US6787423B1 (en) | Strained-silicon semiconductor device | |
US7023055B2 (en) | CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding | |
US8748983B2 (en) | Embedded source/drain MOS transistor | |
CN203553173U (zh) | 电子器件 | |
CN101866885A (zh) | Finfet元件的制造方法 | |
KR20080075411A (ko) | 반도체 소자 및 그 제조방법 | |
US9543302B2 (en) | Forming IV fins and III-V fins on insulator | |
CN102790005B (zh) | 一种选择性刻蚀制备全隔离混合晶向soi的方法 | |
US6642536B1 (en) | Hybrid silicon on insulator/bulk strained silicon technology | |
CN103280459B (zh) | 具有深槽结构的图形化应变nmos器件及其制作方法 | |
US7541258B2 (en) | Method of manufacturing semiconductor substrate and method of manufacturing semiconductor device | |
US10438858B2 (en) | Low-cost SOI FinFET technology | |
CN103258742A (zh) | 晶体管的形成方法 | |
CN103066007B (zh) | 一种全隔离结构的制作方法 | |
CN107910264B (zh) | 一种全耗尽soi结构的制作方法 | |
CN103165509B (zh) | 准绝缘体上硅场效应晶体管的制备方法 | |
CN106856191A (zh) | 半导体结构及其形成方法 | |
US9660023B2 (en) | Semiconductor film with adhesion layer and method for forming the same | |
CN104425276B (zh) | 鳍式场效应晶体管的形成方法 | |
US9391198B2 (en) | Strained semiconductor trampoline | |
Saarnilehto et al. | Local buried oxide technology for HV transistors integrated in CMOS | |
CN102956536A (zh) | 准soi结构的制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140611 Termination date: 20150516 |
|
EXPY | Termination of patent right or utility model |