CN1159656A - 半导体集成电路 - Google Patents
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Abstract
一种半导体集成电路包含一电源电位反应电路以及一电容器(212c);该电路包含一连接成二极管的放电的MOS晶体管,以便在从连接节点至电源电位节点间配置成正向偏压的方向,该晶体管的背栅极和栅极本身相连接;以及,该电路包含一保持电路(216),藉此以保持其输出的电源启动复位信号。
Description
本发明系有关于一种半导体积体电路,特别是有关于一种利用二按二极管连接(diode-connected)的金属氧化物半导体(MOS)晶体管的阈值电压以设计电源复位电路的半导体集成电路。
近来,由于便携式装备如笔记型个人计算机、蜂巢式电话和个人手提电话等广泛快速的传播,低功率损耗型集成电路的需求亦随之剧增。而达成低功率损耗最普遍的方法即是让半导体集成电路在低电压的电源下工作,然而以低电压来驱动半导体集成电路会造成MOS晶体管的阈值电压降对电源电位的比例增大,而使得利用MOS晶体管阈值电压降来调整电位变得困难,这将严重地影响电路设计。
图8显示常规的产生一电源启动复位信号(下文中以POR信号表示)的电启动复位电路(下文中以POR电路表示),在电源启动时用来控制和初始化内部电路,详细例子如美国专利编号5,073,874所描述。在图8中,数字1a表示一电源电位节点在,其上电位为Vcc;数字1b表示一地电位节点,电位为Vss;数字2a和2b表示二个P沟道MOS晶体管而其各别的栅极均和本身的漏极相连接,也就是二极管连接,而二个P沟道MOS晶体管串连后再连接于电源电位节点1a和连接节点2之间。数字2c表示一电容器连接在连接节点2和地电位节点1b之间;数字3是一倒相器由P沟道MOS晶体管2a和N沟道MOS晶体管3b所构成,其输入端接收连接节点2的电位而从输出端输出POR信号。
其次,上述常规POR电路工作方式将在下文中描述。图9是一时序图,表示常规POR电路(如图8所示)在电源启动和断路时的动作。在图9中,数字(a)表示在电源电位节点1a上电位Vcc的变动,数字(b)表示在连接节点2上电位NN2的变动,数字(c)表示图8所示POR电路的输出POR信号电位(POR)的变动情形。此外|Vth|表示MOS晶体管阈值电压的绝对值,而VT表示倒相器的阈值电压。首先,当外部电源启动时,电源电位节点1a的电位Vcc从时间t0开始上升(时间t0)。当电源电位节点1a的电位Vcc达到P沟道MOS晶体管3a阈值电压(|Vth|)时,P沟道MOS晶体管开始要导通而POR信号的电位POR从时间t1开始上升(时间t1)。再来,当电源电位节点1a的电位Vcc再上升达到二个P沟道MOS晶体管2a和2b阈值电压之和2|Vth|时,按二极管连接的P沟道MOS晶体管2a和2b开始导通,藉著电容器2c的充电开始,在时间t2时连接节点2的电位NN2开始以较电源电位节点1a电位平缓的速度上升(时间t2)。当连接节点2的电位NN2已超出倒相器3的阈值电压时,倒相器3被倒相而POR信号的电位POR开始下降(时间t3)。如前述的动作结果,产生一POR信号在电源电压启动时用以控制和初始化内部电路。
其次,当电源关闭时,也就是当改变电源节点1a的电位Vcc使成为地电位节点Vss时,累积在电容器2c的电荷将经由布线电容(WiringCapacitance)而逐渐放电,因此连接节点2的电位NN2开始降低(时间t4)。然而在图8中所示的POR电路中由于在连接节点2上并未配置任何放电路径而仅能由布线电容放电,故而在时间t5电源完全关闭后,要使连接节点2的电位NN2降低至地电位Vss需要很长的时间。当累积在电容器2c和节点2的布线电容的电荷未充分放电之前即连接节点2的电位NN2尚未充分下降(时间t6时)前即再次启动电源,则只有当电源电位节点1a的电位Vcc上升至高于Vα+|Vth|时倒相器3的P沟道MOS晶体管3a开始导通,而POR信号的电位POR开始上升(时间t7)。在这一状况下,Vα表示连接节点2在时间t6时的电位。接著,当电源电位节点1a的电位上升至2个P沟道MOS晶体管2a和2b阈值电压之和|Vth|,且高于Vα时,2个按二极管连接的P沟道MOS晶体管开始对电容器2c充电而连接节点2的电位NN2也开始上升(时间t8)。当连接节点2的电位NN2超出倒相器3的临界电压VT时,被相器3倒相而POR信号电位开始降低(时间t9)。但是,在上述动作过程中,因为电源再一次启动前在连接节点2上仍残留Vα的电位,所以用来决定POR信号脉冲持续时间(t7至t9时段),相对比较于将累积在电容器2c和连接节点2布线电容上的电荷充分放电使连接节点2的电位NN2成为地电位Vss的条件下所决定之POR信号脉冲持续时间(t1到t3时间)而言是极度地缩短了。
以上所描述的常POR电路中,在电源关闭一次后再启动时因为累积在电容器2c和连接节点2的布线电容上的电荷放电速度慢且不完全,致使当电源启动时用以控制和初始化内部电路的任何POR信号将无法产生,即或可产生POR信号也不是正常的脉冲在此将引起误动作。
又当工作在低电压电源时,因为电源关闭时在连接节点2上电容器2c和布线电容所累积的电荷放电不完全,连接节点2上所产生的电位Vα和MOS晶体管的阈值电压|Vth|将占去电压电源Vcc的绝大比例,因此产生另外一个问题就是在电源关闭后很难利用传统的MOS晶体管使连接节点2的电位NN2和地电位Vss相等。
有鉴于此,本发明之目的是要解决上述的问题,亦提供一半导体集成电路能够在电源关闭后再迅速启动时将内部电路的充电电荷放电并将其电位拉低至接近地电位。
本发明的另一个目的是提供一包含POR电路的半导体集成电路,即使在电源关闭后到电源重新启动的时间周期缩短的情形下,在电源启动时仍然能产生正常的POR信号以控制和初始化内部电路。
根据本发明的第一特征,一半导体集成电路包含一放电元件由连接成二极管的MOS晶体管在电源电位节点和连接节点之间的,从连接节点至电源电位节点的方向配置成顺向偏压方向,这一MOS晶体管的背栅极和本身的栅极相连。
根据本发明的第二特征,一半导体集成电路包含一电源电压反应电路,该反应电路包含一提升电路在电源电位节点和连接节点间连接以及一电容器连接到连接节点和地电位节点;一放电MOS晶体管,按二极管连接并在电源电位节点和连接节点之间,从连接节点至电源电位节点的方向配置成前向偏压方向,这一MOS晶体管的背栅极和本身的栅极相连;一保持电路,其接收前述连接节点的电位以及输出一电源启动复位信号,使电平从电源电位开始上升经一预定时间后从第一电平改变为第二电平,而与超出预设电平的连接节点的电位相对应,从而保持该电源启动复位信号的第二电平。
图1为应用本发明的DRAM方框图;
图2为根据本发明一实施例的POR产生电路;
图3为根据本发明的POR产生电路的动作时序图;
图4为根据本发明的MOS晶体管阈值电压对背栅极和源极间电压的特性图;
图5为根据本发明另一实施例的POR产生电路;
图6为根据本发明又一实施例的POR产生电路图;
图7为根据本发明再一实施例的POR产生电路图;
图8为根据先有技术的POR产生电路图;以及
图9为根据先有技术POR产生电路的电路动作时序图;
在所有的图示中,相同的单元均约予相同的数字。
图1表示应用本发明DRAM(动态随机存取存储器)100的方框图包含一个内部电位产生电路群组200,一POR电路210和一存储单元阵列101由多个以行列方式排列的存储单元所组成。一
RAS(行地址选通)缓冲器110接收一由外部施加的信号
RAS和输出
RAS信号至地址缓冲器130;以及
CAS(列地址选通)缓冲器120接收一由外部施加的信号CAS和输出一CAS信号至地址缓冲器130。地址缓冲器130接收一外部地址信号ext Ai(i=0,1,2……)和该
RAS信号,锁存该外部地址信号extAi,输出行地址信号RAi和
RAi给内部电路,以及接收外部地址信号ext Ai(i=0,1,2……)和该
CAS信号,锁存外部地址信号extAi和输出列位址信号CAi和
CAi给内部电路。
一行译码器140接收从地址缓冲器130来的信号RAi和
RAi后选择一相对应的字元线;一列译码器150接收从地址缓冲器130来的信号CAi和
CAi后选择一相对应的读出放大器以及I/O(输入/输出)电路170,该放大器用以放大存储单元101在位元线上被读出的电位而I/O电路则用以传送存储单元101在位元线上被读出的数据。数字160表示一字元驱动器用以提高行译码器140所选择的字元线的电位;180表示一读出和写入的控制电路,从外部接收一写入允许信号ext/WE和一输出允许信号ext/OE,且输出一WO信号来控制内部电路的读出和写入;以及190表示一I/O缓冲器接收从读出和写入控制电路180输出的信号WO,在写入的情形下经一数据线传送外部施加的数据extDin至I/O引线I/O读出放大器170,在读出的情形下输出存储单元中的读出数据由读出放大器170放大后经I/O电路数据线传送至I/O引线成为数据ext Dout信号。
在图1中,POR电路210用以当电源启动时产生POR信号来控制和初始化内部电路如内部电位产生电路群组200和
RAS缓冲器110以及其它部分电路。
图2是表示根据本发明一个最佳实施例的POR电路210一图,而图3系一动作时序图。在图2中,211a表示一电源电位节点其电位为Vcc;数字211b表示一地电位节点其电位为Vss;以及数字212a和212b表示2个N沟道MOS晶体管其个别的栅极和漏极均相连在一起,也就是按二极管连接,在电源电位节点和连接节点间连接以便从电源电位节点211a至连接节点212的方向配置成前向偏压方向,从而形成一提升电路212f。数字212c表示一电容器连接在连接节点212和地电位节点211b之间,且和提升电路共同形成一电源电位反应电路212g。数字214表示一倒相器由一P沟道MOS晶体管214a和N沟道MOS晶体管214b构成,其输入端接收连接节点212的电位而输出端输出POR信号POR;数字215也是一倒相器由一P沟道MOS晶体管215a和一N沟道MOS晶体管215b构成,其输入端接收POR信号POR而输出端则连接至连接节点212;数字216表示一保持电路由两个倒相器214和215构成;数字213表示一N沟道MOS晶体管连接在电源电位节点211a和连接节点212之间,且从连接节点212至电源电位节点211a的方向配置成前向偏压方向,其背栅极213bg亦连接到栅极213g。因此,该MOS晶体管213的作用为一放电晶体管,也就是说在电源电位节点211a的电位Vcc降至比连接节点212的电位低于一个N沟道MOS晶体管213的阈值电压时,MOS晶体管213导通并将累积在电容器212c和连接节点212的布线电容上的电荷放电。
本身栅极和背栅极相连接的MOS晶体管的阈值电压将在下文中参照图4来描述。
图3显示MOS晶体管的阈值电压Vth相对于MOS晶体管其背栅极电压和源极间电位差VBS的变动图示,而其电位差如下列运算式(1)所表示:
Vth=V0+K[(2F+VBS)1/2-(2F)1/2] (1)其中:VBS表示背栅极电压(以源极电压为基准),K表示基片体效应常数,F表示基片表面电位,以及V0表示当VBS=0V时的阈值电压。
在图4中,d表示MOS晶体管背栅极与源极间的电位差VBS和MOS晶体管的阈值电压Vth在此相等之点。从图4很明显地看出,因为VBS=Vth的结果使得将传统上VBS=-1.5V时MOS晶体管的阈值电压为0.7V降低至0.25V成为可能,且尚比VBS=0V时的阈值电压V0(0.35V)小0.1V。将MOS晶体管的背栅极连接在一起即可使VBS=Vth。在下文的描述中,为区别起见|Vtho|将表示当MOS晶体管背栅极和栅极连接时阈值电压的绝对值,而|Vth|则表示当VBS=-1.5V时传统MOS晶体管的阈值电压。
接著,上文提及的POR电路210动作方式将在下文中描述。在图3中,(a)表示电源电位节点211a电位Vcc的变动,(b)表示在连接节点212上电位N212变动,以及(c)表示POR电路210的输出信号POR的电位变动。
首先,当由外部电源启动时,电源电位节点211a的电位Vcc在T0时开始上升,如图3(a)所示。当电源电位节点211a在电位Vcc在T1时(参照3(a))达到P沟道MOS晶体管214a的阈值电压值|Vth|时,P沟道MOS晶体管214a开始导通,而POR信号的电位POR也开始如图3(c)所示上升。当电源电位节点211a的电位Vcc在T2时(参照图3(a))再上升到达2个N沟道MOS晶体管212a和212b的阈值电压的相加值2|Vth|时,2个N沟道MOS晶体管212a和212b开始导通而电容器212c也开始充电,借此电容器的充电连接节点212的电位N212开始以较电源电位节点212a电位上升斜度平缓的速度上升如图3(b)所示。当连接节点212的电位N212在如图3(b)所示T3处超出倒相器214的阈值电压VT时,倒相器214被倒相,也就是说MOS晶体管214a成开路截止状态,结果POR信号的电位POR开始下降如图3(c)所示。藉由上述的动作,在电源启动时用以控制和初始化内部电路的POR信号于是产生。在这动作期间,按二极管连接的放电N沟道MOS晶体管213一直处在反偏的状态且没有任何电流流通。倒相器215的功能为提高连接节点212的电位,并和倒相器214一起形成锁存电路来保留POR信号。
当电源是断时,电源电位节点211a的电位在T4处开始下降如图3(a)所示,随著电位继续下降,累积在电容器212c和连接节点212布线电容上的电荷也经由沟道MOS晶体管215a以及正向偏压的按二极管连接的放电N沟道MOS晶体管213逐渐地放电,而连接节点212的电位N212也就如图3(b)所示下降。当电源电位节点电位Vcc降至与地电位节点电位Vss相等时,连接节点212的电位N212将更进一步在T5处下降至放电NMOS晶体管213阈值电压|Vtho|的电平如图3(b)所示。但是,如果放电N沟道MOS晶体管的背栅极没有与其栅极相连接,也就是说当背栅极是连接到基片电位VBB或地电位Vss时,连接节点212的电位N212仅能下降至比|Vtho|高的电位|Vth|。
随后,当在T6处重新启动电源时,电源电位节点211a的电位Vcc将如图3(b)所示T7处超出|Vtho|+|Vth|,在此同时P沟道MOS晶体管214a开始导通而使POR信号的电位POR开始上升如图3(c)所示。当电源电位节点211a的电位Vcc再上升达到|Vtho|+2|Vth|比|Vtho|高出2个N沟道MOS晶体管212a和212b的阈值电压和2|Vth|时(时间T8),2个按二极管连接的N沟道MOS晶体管212a和212b都导通,开始对电容器212c充电,因此连接节点212的电位N212开始上升,如图3(b)所示。此外,当连接节点212的电位N212已达到倒相器的阈值电压VT时(如图3(b)时间T9),倒相器214的输出倒相而POR信号的电位POR开始下降,如图3(c)所示。另一方面,如果连接节点212的电位N212只能降至|Vth|的电平而不能再降时,则POR信号的电位POR不是一正常脉冲信号,如图3(c)虚线所示。
如上所述,在POR电路中累积在电器212c和连接节点212布线电容上的电荷在电源中断后都很快速地降至充分的电平,如此即使缩短电源中断后到电源重新开启的时间所产生的POR信号依然是一正常的脉冲信号,最终使保护半导体集成电路免于受在电源启动时的影响而导至误动作成为可能。
虽然在上述实施例中以二个倒相器214和215来构成保持电路216,但是在倒相器214输出端连接多级倒相器218和219(如图5所示)做为驱动器亦是另一较佳实施例。
此外,虽然N沟道MOS晶体各213是做为放电晶体管,其亦可以P沟道MOS晶体管217来取代(如图6)。再者,如图7所示利用P沟道MOS晶体管212d和212e来取代N沟道MOS晶体管212a和212b也是另一较佳实施例。
前述的实施例有一个优点,即一半导体集成电路包含一放电单元能在电源中断时将电位快速地放电至近乎地电位的电平。
此外,根据本发明之另一优点是,一半导体集成电路包含一POR产生电路用以产生一正常脉冲信号即使当电源中断后立即再启动电源也能够控制以及初始化内部电路。
虽然本发明已以一些较佳实施例说明如上,然其并非用以限定本发明,本领域的一般技术人员,在不脱离本发明的精神和范围内,当可作各种更动与附加,因此本发明的保护范围仅由后附的申请专利范围所界定。
Claims (4)
1.一半导体集成电路包含:
一电源电位反应电路,由一连接在一电源电位节点和一连接节点之间的提升电路,以及一连接在该连接节点和一地电位节点之间的电容器组成;
一放电MOS晶体管在该电源电位节点和连接节点间按二极管方式连接以便从该连接节点至该电源电位节点配置成正向偏压的方向,该MOS晶体管的背栅极与其自身的一栅极相连接;以及
一保持电路,接收该连接节点的电位以及输出一电源启动复位信号,使电平从该连接节点的电位在电源电位开始上升后一预定期间后从第一电平改变为第二电平,与超出预设电平的连接节点的电位相对应,从而保持将该电源启动复位信号的第二电平。
2.如权利要求1所述的该半导体集成电路,该提升电路包含2个MOS晶体管,该2个MOS晶体管皆按二极管连接以便从电源电位节点至连接节点配置成正向偏压方向。
3.如权利要求2所述的该半导体集成电路,该2个MOS晶体管的背栅极分别与其本身的一栅极相连接。
4.如权利要求1所述的该半导体集成电路,该保持电路包含一对MOS连接成触发器的倒相器电路。
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JP7321760A JPH09162713A (ja) | 1995-12-11 | 1995-12-11 | 半導体集積回路 |
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CN96123112A Expired - Fee Related CN1090819C (zh) | 1995-12-11 | 1996-12-11 | 半导体集成电路 |
CN96119753A Expired - Fee Related CN1091974C (zh) | 1995-12-11 | 1996-12-11 | 升压脉冲产生电路 |
CN96119754A Expired - Fee Related CN1079981C (zh) | 1995-12-11 | 1996-12-11 | 电势生成电路 |
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KR940003153B1 (ko) * | 1991-04-12 | 1994-04-15 | 금성일렉트론 주식회사 | 백바이어스 발생회로 |
US5160860A (en) * | 1991-09-16 | 1992-11-03 | Advanced Micro Devices, Inc. | Input transition responsive CMOS self-boost circuit |
JP2771729B2 (ja) * | 1992-04-16 | 1998-07-02 | 三菱電機株式会社 | チャージポンプ回路 |
JP3381937B2 (ja) * | 1992-05-22 | 2003-03-04 | 株式会社東芝 | 中間電位発生回路 |
KR0135735B1 (ko) * | 1992-11-04 | 1998-05-15 | 기다오까 다까시 | 소음발생을 억제하는 개량된 출력 드라이버 회로 및 번인테스트를 위한 개량된 반도체 집적회로 장치 |
JPH06223568A (ja) * | 1993-01-29 | 1994-08-12 | Mitsubishi Electric Corp | 中間電位発生装置 |
JP3307453B2 (ja) * | 1993-03-18 | 2002-07-24 | ソニー株式会社 | 昇圧回路 |
JP3311133B2 (ja) * | 1994-02-16 | 2002-08-05 | 株式会社東芝 | 出力回路 |
JP3148070B2 (ja) * | 1994-03-29 | 2001-03-19 | 株式会社東芝 | 電圧変換回路 |
US5644266A (en) * | 1995-11-13 | 1997-07-01 | Chen; Ming-Jer | Dynamic threshold voltage scheme for low voltage CMOS inverter |
-
1995
- 1995-12-11 JP JP7321760A patent/JPH09162713A/ja active Pending
-
1996
- 1996-06-19 TW TW085107407A patent/TW293124B/zh active
- 1996-09-03 TW TW085110768A patent/TW409395B/zh not_active IP Right Cessation
- 1996-09-03 TW TW085110769A patent/TW381206B/zh not_active IP Right Cessation
- 1996-09-16 TW TW085111317A patent/TW321805B/zh active
- 1996-12-10 US US08/763,120 patent/US5815446A/en not_active Expired - Fee Related
- 1996-12-10 US US08/763,119 patent/US5812015A/en not_active Expired - Fee Related
- 1996-12-10 US US08/763,283 patent/US5717324A/en not_active Expired - Fee Related
- 1996-12-10 US US08/762,903 patent/US5726941A/en not_active Expired - Fee Related
- 1996-12-11 KR KR1019960064180A patent/KR100231951B1/ko not_active IP Right Cessation
- 1996-12-11 KR KR1019960064183A patent/KR100270002B1/ko not_active IP Right Cessation
- 1996-12-11 CN CN96119756A patent/CN1096118C/zh not_active Expired - Fee Related
- 1996-12-11 CN CN96123112A patent/CN1090819C/zh not_active Expired - Fee Related
- 1996-12-11 CN CN96119753A patent/CN1091974C/zh not_active Expired - Fee Related
- 1996-12-11 KR KR1019960064182A patent/KR100270001B1/ko not_active IP Right Cessation
- 1996-12-11 CN CN96119754A patent/CN1079981C/zh not_active Expired - Fee Related
- 1996-12-11 KR KR1019960064181A patent/KR100270000B1/ko not_active IP Right Cessation
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7638845B2 (en) | 2005-10-03 | 2009-12-29 | Seiko Epson Corporation | Semiconductor device with buried conductive layer |
CN110134175A (zh) * | 2018-02-08 | 2019-08-16 | 艾普凌科有限公司 | 基准电压电路以及半导体装置 |
CN110134175B (zh) * | 2018-02-08 | 2022-05-03 | 艾普凌科有限公司 | 基准电压电路以及半导体装置 |
Also Published As
Publication number | Publication date |
---|---|
CN1158516A (zh) | 1997-09-03 |
CN1091974C (zh) | 2002-10-02 |
KR970051294A (ko) | 1997-07-29 |
CN1158501A (zh) | 1997-09-03 |
KR100270002B1 (ko) | 2000-10-16 |
TW321805B (zh) | 1997-12-01 |
KR100270001B1 (ko) | 2000-10-16 |
US5726941A (en) | 1998-03-10 |
TW381206B (en) | 2000-02-01 |
KR100231951B1 (ko) | 1999-12-01 |
TW293124B (en) | 1996-12-11 |
CN1079981C (zh) | 2002-02-27 |
US5717324A (en) | 1998-02-10 |
CN1096118C (zh) | 2002-12-11 |
US5812015A (en) | 1998-09-22 |
KR970051173A (ko) | 1997-07-29 |
JPH09162713A (ja) | 1997-06-20 |
KR100270000B1 (ko) | 2000-10-16 |
TW409395B (en) | 2000-10-21 |
US5815446A (en) | 1998-09-29 |
KR970051145A (ko) | 1997-07-29 |
CN1158500A (zh) | 1997-09-03 |
CN1090819C (zh) | 2002-09-11 |
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