CN114242764A - 形成器件的方法和形成纳米线器件的方法 - Google Patents

形成器件的方法和形成纳米线器件的方法 Download PDF

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Publication number
CN114242764A
CN114242764A CN202111293250.5A CN202111293250A CN114242764A CN 114242764 A CN114242764 A CN 114242764A CN 202111293250 A CN202111293250 A CN 202111293250A CN 114242764 A CN114242764 A CN 114242764A
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source
silicon
forming
nanowire
substrate
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K·J·库恩
S·金
R·里奥斯
S·M·赛亚
M·D·贾尔斯
A·卡佩尔拉尼
T·拉克什特
P·常
W·瑞驰梅迪
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Sony Corp
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Sony Corp
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Priority claimed from CN201180058034.0A external-priority patent/CN103238208B/zh
Publication of CN114242764A publication Critical patent/CN114242764A/zh
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Abstract

本发明涉及形成器件的方法和形成纳米线器件的方法。其中，形成器件的方法可包括：在衬底上形成外延硅锗；在所述外延硅锗上形成外延硅；对布置在所述外延硅锗上的所述外延硅布图以形成鳍结构；在所述鳍结构上方形成牺牲栅电极；在所述牺牲栅电极的侧壁附近以及所述鳍结构上方形成间隔物；从所述衬底上的源极/漏极区去除所述鳍结构的半导体部分，然后在所述源极/漏极区上形成源极/漏极结构，其中所述源极/漏极区位于所述间隔物附近；从所述间隔物之间去除所述牺牲栅电极；以及从位于所述间隔物之间的所述鳍结构去除所述硅和所述外延硅锗中的一者。

Description

形成器件的方法和形成纳米线器件的方法
本申请是申请日为2011年11月23日、发明名称为“硅和硅锗纳米线结构”的申请号为201610421227.2的专利申请(下文称“子案”)的分案申请。
本申请是在国家知识产权局认为上述子案不符合单一性要求的情况下提出的，具体涉及所述子案的第1次审查意见通知书，其发文日为2018 年6月28日、发文序号为2018062501954570。
此外，上述子案是第201180058034.0号专利申请(下文称“母案”) 的分案申请，该母案的申请日是2011年11月23日，发明名称是“硅和硅锗纳米线结构”。
背景
随着微电子器件尺寸攀升过15nm的节点，保持迁移率改善和短沟道控制对器件制造提出了挑战。用于制造器件的纳米线提供改善的短沟道控制。例如，硅锗(Si x Ge 1-x)纳米线沟道结构(其中x＜0.5)提供在可观的Eg下的迁移率改善，这适用于利用较高电压操作的许多传统产品。此外，硅锗(Si x Ge 1-x)纳米线沟道(其中x＞0.5)在较低Eg下提供改善的迁移率(适用于例如移动/手持领域内的低电压产品)。
附图件数
尽管说明书以特别指出和独立地要求某些实施例的权利要求书作为结尾，但各实施例的优势可从下面结合附图对实施例的描述中得到更好的理解，在附图中：
图1a-1n示出根据各实施例形成结构的方法。
图2a-2i示出根据各实施例形成结构的方法。
图3a-3g示出根据各实施例形成结构的方法。
图4a-4m示出根据各实施例形成结构的方法。
图5a-5d示出根据各实施例形成结构的方法。
图6示出根据各实施例的系统。
详细描述
在对本发明实施例的如下详细描述中，对示出可投入实践的特定实施例的附图作出参照。充分详细地描述这些实施例，以使本领域技术人员将这些实施例投入实践。要理解，各实施例尽管是不同的，但不一定是相互排斥的。例如，这里结合一个实施例描述的特定特征、结构或特性可在其它实施例中实现而不脱离它们的精神和范围。另外要理解，可修正各公开实施例中的各个要素的位置或配置而不脱离它们的精神和范围。因此，下面的详细描述不具有限定意义，并且各实施例的范围仅由适当解释的所附权利权利要求连同这些权利要求授权的等效物的全部范围来定义。在附图中，相同的附图标记贯穿若干附图地表示相同或相似的功能。
描述了形成和利用诸如纳米线器件结构之类的微电子结构的方法和相关结构。这些方法和结构可包括：形成包含衬底的纳米线器件，该衬底包括源极/漏极结构，该源极/漏极结构包括在源极/漏极结构之间的纳米线，其中该纳米线沟道结构在彼此之上垂直地层叠。这里包括的各实施例随着器件尺寸攀升过15nm这一节点时允许迁移率改善和短沟道控制。这些实施例进一步改善了沟道与衬底的绝缘，缓解了与间隔物间隙间距相关的电容以及通过纳米线的垂直架构扩展(scaling)。
图1a-1n示出形成微电子结构(例如形成纳米线器件结构)的实施例。图1a示出一衬底100。在一个实施例中，衬底100可包括大块硅衬底100。在其它实施例中，衬底100可包括绝缘体衬底上硅(SOI)100，但也可包括任何类型的适宜的衬底材料。在一实施例中，第一硅锗102材料可通过外延生长在衬底100上生长。在一实施例中，第一硅材料104外延生长在外延的第一硅锗102上。第二硅锗层102’可形成在第一硅层102 上，并且第二硅层104’可形成在第二硅锗102’上。在另一实施例中，形成在衬底100上的交替的外延硅锗层102/外延硅层104的数目可根据具体应用而变化。在另一实施例中，可颠倒层顺序，即形成在衬底100上的外延硅104和外延硅锗102的交替层。
在一实施例中，可使用传统的布图/蚀刻技术(图1b)对硅锗/硅/硅锗/ 硅的外延叠层120进行布图。例如，叠层结构120可在沟槽蚀刻工艺中被蚀刻，例如在浅沟槽隔离(STI)工艺期间，其中沟槽101可形成在衬底 100内以形成鳍结构107。所形成的每个鳍结构107可通过氧化物103彼此隔开，氧化物103可形成在沟槽101中。
在一实施例中，鳍结构107可包括栅完全包围(GAA)纳米线器件的双沟道部分。器件中的沟道数目将依赖于鳍结构107中的层数。鳍结构 107可包括纳米线结构。间隔物106可形成在鳍结构107之上并横跨鳍结构107，并可相对于鳍结构107正交地设置(图1c)。在一实施例中，间隔物106可包括在对鳍结构107材料加工期间可选择的任何材料。
在一实施例中，栅电极材料108可形成在间隔物106内/之间，并可形成在鳍结构107位于间隔物106之间的诸个部分周围。在一实施例中，栅电极材料可形成在鳍结构107的部分周围，而间隔物106形成在栅的任一侧。在某些情形下，栅108可包括多晶硅，并可包括牺牲栅结构108。在一实施例中，可将一部分鳍结构107从衬底100去除以露出源极/漏极区109(图1d)。在一实施例中，可通过干蚀工艺蚀刻掉鳍结构107的一部分以使源极/漏极区109露出。在一实施例中，可蚀刻源极/漏极区109以使其终止在衬底100或底部线路(102或104)上。可利用供选择的下切湿蚀或干蚀工艺以根据具体器件需求去除栅极108区尖端(tip)重叠区内的附加材料。
在一实施例中，硅或硅锗源极漏极结构110可利用外延生长技术在源极/漏极区109中生长(图1e)，并可耦合至鳍结构107位于间隔物106 之间的部分。在一实施例中，外延源极/漏极结构110可以是用于NMOS 器件的n掺杂硅，或者是用于PMOS器件的p掺杂硅/硅锗，这依赖于具体应用的器件类型。可通过注入、通过等离子掺杂、通过固体源掺杂或业内公知的其它方法将掺杂引入到外延工艺中。
可通过将掺杂以不同掺杂物种类和浓度的外延层结合来设计尖端和源极/漏极结。例如，当利用硅锗源极/漏极来向PMOS器件的硅沟道中添加应变时可在源极/漏极硅锗外延结构110生长之前首先生长硅止蚀层 /尖端112，从而避免在后继的硅锗蚀刻工艺中在源极/漏极区110中作出蚀刻(图1f)。换句话说，PMOS末梢材料需要对后继的硅锗蚀刻工艺具有抗性。
中间层电介质(ILD)可在源极/漏极结构110和栅极108、间隔物106 之上形成在衬底100(未示出)上。在一实施例中，牺牲多晶栅极108的顶部可通过化学机械抛光(CMP)而敞开。然后将牺牲栅电极材料108从间隔物材料106之间除去(图1g)。图1h示出间隔物106之间的内侧图，其中鳍结构107被设置在两个间隔物(图中仅示出一个)之间。在一实施例中，可选择地将硅层104、104’从鳍结构107去除以在硅锗沟道102、 102’之间打开间隙111(图1i)。在一实施例中，可选择地通过湿蚀对硅层104、104’进行蚀刻，该湿蚀选择性地去除硅104、104’同时不蚀刻硅锗纳米线结构102、102’。可利用诸如亲水氢氧化物化学药剂(包括氢氧化铵和氢氧化钾)之类的蚀刻化学药剂来选择性地蚀刻硅。
在另一实施例中，可选择地将硅锗层102、102’从鳍结构107和从侧壁去除以在硅沟道层104、104’之间打开间隙113(图1j)。在一实施例中，可通过湿蚀选择性地蚀刻硅锗102、102’，该湿蚀选择性地去除硅锗而同时不蚀刻硅纳米线沟道104、104’。可利用诸如柠檬酸/硝酸/HF化学药剂以及柠檬酸/硝酸/HF之类的蚀刻化学药剂来选择性地蚀刻硅锗。因此，可将硅层从鳍结构107中去除，或者将硅锗层从鳍结构107去除以在间隔物106之间的沟道区内形成硅沟道纳米线104、104’结构。在一实施例中，硅和硅锗沟道材料可存在于同一晶片上、同一管芯内或同一电路上，例如逆变器结构中的NMOS Si和PMOS SiGe。在同一电路中具有NMOS Si和PMOS SiGe的实施例中，可相互选择Si沟道厚度(SiGe 中间层)和SiGe沟道厚度(Si中间层)以改善电路性能和/或电路最小工作电压。在一实施例中，可通过蚀刻工艺改变同一电路中的不同器件上的导线数以改善电路性能和/或电路最小工作电压。
可形成栅极电介质材料115以使其包围间隔物106之间的沟道区。在一实施例中，栅极电介质材料115可包括高k栅电极材料，其中介电常数可包括高于大约4的值。在一实施例中，栅极电介质材料115可完全包围间隔物106之间的硅纳米线结构104、104’共形地形成(图1k)。在另一实施例中，栅电极材料115可完全包围间隔物106之间的硅锗纳米线结构102、102’地形成(未示出)。
栅电极材料117然后可形成在栅极电介质材料115周围(图1l)。栅电极材料117可包括诸如纯金属和Ti、W、Ta、Al的合金的金属栅电极材料，包括诸如TaN、TiN的氮化物，还包括诸如Er、Dy的具有稀土的合金或诸如Pt的贵金属。硅纳米线结构104、104’之间的间隙113可用栅电极材料117填充。在另一实施例中，硅锗纳米线结构102、102’之间的间隙111可用栅电极材料117填充(未示出)。在一实施例中，可在衬底100上进一步执行标准CMOS加工以制造根据本文所述实施例的 CMOS器件。
在一实施例中，可形成NMOS和/或PMOS器件。图1m示出可形成的NMOS器件(示出一个硅沟道)，其中沟槽触头119耦合至源极漏极结构110，该源极漏极结构110在一些情形下可以是硅掺杂的n+，这依赖于具体应用。硅外延尖端112在某些情形下可以是n-掺杂的并可设置在源极漏极结构110和衬底100之间。栅电极材料117可包围硅纳米线沟道104。
图1n示出PMOS器件(示出一个硅沟道104)，其中沟槽触头119耦合至源极漏极结构110，该源极漏极结构110在一些情形下可以是硅锗掺杂的p+，这依赖于具体应用。在某些情形下可以是p-掺杂的硅外延尖端 /止蚀部120可设置在源极漏极结构110和衬底100之间。栅电极材料117 可围住硅沟道104，该硅沟道104在某些情形下可包括应变的硅沟道104。
在一些情形下，利用硅锗沟道结构(例如图1i中绘出的那些结构)的器件由于硅锗特性包含高载流子迁移率而具有优势。在一实施例中，栅完全包围硅锗沟道器件的工艺可类似于栅完全包围硅沟道器件工艺，除了外延层叠层120可能相反，也就是最初将硅材料104形成在衬底上并在硅上形成硅锗。由于硅下层将被选择性地去除至硅锗，因此源极/漏极可包括硅锗，并且牺牲栅电极材料下面的止蚀部也可包括硅锗以避免衬底蚀刻。
本文的实施例允许制造自对准的栅完全包围(GAA)硅和硅锗沟道晶体管结构和器件。由于短沟道效应(SCE)减少，纳米线沟道器件表现出较低的亚阈泄漏。GAA SiGe高迁移率沟道器件的实现例如抑制了SCE效应。(GAA)器件可最大化对沟道的静电栅控制。
在一实施例中，根据本文各实施例制造的器件可设置有增强的衬底绝缘。参见图2a，设置在衬底200上的底部纳米线沟道202在一些情况下可包括具有低劣子鳍泄漏的短三栅极。一种方案可包括在绝缘体上硅 (SOI)衬底201上形成器件(图2b-2c)，其中源极/漏极结构210和纳米线结构204被设置在诸如氧化物材料203之类的绝缘体材料203上，而不是设置在大块硅衬底200上(如图2a所示)。通过使用SOI衬底201，可在纳米线鳍结构(类似于例如图1b中的纳米线鳍结构107)的硅锗蚀刻之后和在形成栅电极材料(类似于例如图1l中的栅电极材料117)之前通过蚀刻底部氧化物来限定底部纳米线204的几何形状。
例如，图2d示出蚀刻电介质以形成一条纳米线和一个三栅极结构，而图2e示出蚀刻电介质以形成包含两条纳米线的器件。在另一实施例中，可通过在沟槽蚀刻后在鳍207侧壁上形成鳍间隔物211而取得改善的衬底绝缘(图2f)。然后可执行第二沟槽蚀刻214以露出底部鳍区216，并可氧化底部鳍区216的硅部分(图2g)。因此，器件的底部纳米线可被设置在氧化物上以改善衬底绝缘。在另一实施例中，鳍间隔物211可在沟槽蚀刻和填充之后形成在鳍207侧壁上(图2h)。鳍207的底硅部216可在 STI凹口成形/氧化物填充之后被氧化以改善衬底绝缘(图2i)。因此，器件的底部纳米线可被设置在氧化物上以改善衬底绝缘。
在一实施例中，在间隔物306中可存在通过将纳米线叠层307的硅区去除而留下的间隙311(图3a)。在添加诸如金属栅极结构(类似于例如图1l的栅极结构117)的栅极后，间隙311可在后继形成的栅极和源极漏极结构310之间形成非常高电容的寄生区。在一实施例中，可通过利用外延氧化物302而不是硅(可能需要或可能不需要硅衬底300上的取向改变)作为起始叠层来避免潜在的寄生区(图3b)。在一实施例中，可在外延氧化物材料302上形成外延半导体材料304的交替层，该外延氧化物材料302可形成在衬底300上。
例如，Gd 2O 3可外延生长在(111)硅上，然后在Gd 2O 3的顶上生长硅锗以在衬底上建立一多层叠层，该衬底可被蚀刻成鳍结构307，该鳍结构307之后可形成为硅锗线。在另一实施例中，二氧化铈可生长在 (111)硅上(或替代地生长在(100)硅上)以形成多层叠层。通过氧化物/半导体/氧化物叠层，存在对不蚀刻、部分蚀刻或完全蚀刻鳍结构307的氧化物材料302、302’的选择(分别示出于图3c-3e)。不蚀刻的选择(图3c)解决了电容问题，但其代价是较低劣的禁闭性(confinement)；部分蚀刻的选择(图3d)改善了禁闭性但其代价是某一程度的寄生电容。
在另一实施例中，在源极漏极外延生长之前，可用第二间隔物312 填充间隔物中位于鳍结构附近的间隙311(如图3a所示)，该第二间隔物 312包括从间隔物306的源极/漏极310侧开始的间隔物类材料312或低 k材料312(图3f)。例如，诸如但不限于SiON、SiN、SiC、SiOBN和低 k氧化物的材料可包括第二间隔物312材料。在一实施例中，在蚀刻叠层307中可去除所有的硅，以使替代栅极蚀刻(牺牲栅电极材料的去除)仅命中氧化物。在另一实施例中，仅一部分硅被去除，以使替代栅极蚀刻实际上侵蚀到硅。在另一实施例中，可(在栅极沉积之前)用间隔物类材料 312或低k材料312从栅极侧开始填充间隙311(图3g)。实施例包括执行叠层307的完全蚀刻或部分蚀刻(图示为完全蚀刻)。
在另一实施例中，可通过利用硅蚀刻的各向异性来填充间隙311以在从叠层307去除步骤期间使硅的蚀刻最小化。例如，可使用具有沿 <111>的沟道的(110)晶片。该结构将具有面向源极/漏极结构310的慢蚀 (111)平面，由此限制下切。这里选择的湿蚀也必须比Si更缓慢地蚀刻 SiGe，从而在去除SiGe纳米线之间的所有硅之后留出部分蚀刻的SiGe 纳米线。因此，可使用各向异性蚀刻来最小化间隔物306中的侧向蚀刻，其中蚀刻化学药剂对硅具有高度选择性而对硅锗不具有选择性。
在一实施例中，可利用纳米线实现垂直架构扩展。在一实施例中，硅锗或硅可从衬底外延生长到沟槽中，然后可使用例如氧化或蚀刻工艺来将鳍结构分割成多条纳米线，其中诸纳米线可垂直地层叠在彼此之上。在一实施例中，可对整条线进行氧化，其中源极/漏极区以SiGe(或Si和氧化物)层开始。可在硅衬底401上形成交替的氧化物404和氮化物层402(可使用更多的层来形成更多的导线)(图4a)。可对氧化物和氮化物层布图和蚀刻以形成沟槽405和背部406，其中沟槽405使衬底401的硅材料露出(图4b)。硅锗(或硅)407可在沟槽405和后部外延地生长，并可被抛光(图4c)。可在硅锗(或硅)407上形成硬掩模408，并可对其布图和蚀刻以使鳍410的侧面露出(图4d)。在一实施例中，可通过去除氮化物和氧化物交替层中未被硬掩模覆盖的一部分而形成鳍结构。
鳍410可被氧化以界定纳米线(图4e)。可去除鳍410的氧化部分以形成纳米线412，该纳米线412可充当器件的沟道结构并可基本横跨整个结构地形成。在一实施例中，第一纳米线412可垂直地设置在第二纳米线412’上方。在另一实施例中，线可仅被界定在沟道区(图4g-4j)。第二掩模材料413，例如SiC，可形成在鳍结构410周围。第二掩模材料413 对氧化物和氮化物可具有选择性。鳍结构410可包括交替的氧化物/氮化物膜，这与例如图4d中的那些类似。沟槽414可被打开以将栅极区界定在鳍结构410附近，此处可后继地形成栅电极材料并且其中一部分鳍结构410可露出(图4h)。可执行氧化以界定纳米线(图4i)，并可通过去除鳍结构的氧化部分来进一步界定这些线(图4j)。因此，这些线被形成在栅极区/沟槽414中，而不是源极/漏极区中。
为使布图纳米线的光刻考虑变得容易，可使用间隔物工艺。这里，可通过蚀刻围绕Si或SiGe鳍410的氮化物来露出Si或SiGe鳍410的侧部(而顶部可由例如SiC的硬掩模421覆盖)，并通过各向同性沉积和各向异性蚀刻的组合来形成间隔物420(图4k)。然后使用该间隔物420来作为蚀刻的掩模以使鳍410的侧壁露出。然后可将间隔物420去除。
在另一实施例中，各向异性湿蚀将鳍分割成如图4l所示的多条线。首先可使用湿蚀将氧化物蚀刻掉。接着，可使用Si或SiGe各向异性湿蚀来蚀刻鳍410露出的SiGe或Si。由于晶体方向上蚀刻速率相关性，可形成纳米线。在一实施例中，在两种蚀刻被执行后，可将纳米线形成为六边形。Si或SiGe鳍可在去除氧化物后形成(图4m)。
可实现纳米线的垂直扩展。由于声子散射可将纳米线尺寸限制至大约7nm，这可限制这类器件的长期扩展。一种方案是垂直地构造器件，其中要么N沟道要么P沟道位于底部线内而另一沟道位于顶部线内。在一实施例中，N+衬底可用于Vss。在另一实施例中，顶部和底部触头可以是不对准的。在另一实施例中，可形成具有左、右翼的线。图5a示出通过用于Vss的N+衬底500和栅极501完成的逆变器。注意这需要：高触头512(TCN)，用以连接N和P纳米线沟道514；短顶TCN 510，用以耦合于N和P纳米线沟道514中的一者；以及衬底插入物508/底部TCN，其耦合至N和P纳米线沟道514中的一者并耦合至衬底500。图5b示出未对准的顶部510和底部508TCN。图5c示出含左翼和右翼纳米线结构 514的N和P纳米线。图5d示出布线有左翼和右翼纳米线结构514的逆变器。
具有GAA的纳米线提供优于GAA非纳米线结构以及鳍和三栅极结构的改善。使用具有替代金属栅极(RMG)、栅完全包围处理的侧向纳米线是从具有RMG的平面至具有RMG的鳍的路线图的逻辑延伸。栅完全包围(GAA)纳米线结构给予与GAA非纳米线结构和鳍相比而言改善的短沟道控制的潜力。来自衬底的硅或硅锗纳米线结构中改善的底部线绝缘可根据本文实施例达成。
当最小纳米线尺寸由于声子散射而被限制在＞～7nm时，可允许密度扩展。硅和硅锗两者的侧向纳米线结构可结合替代金属栅极架构和对从这些结构改型的线(面向三栅极结构研发)生产兼容的制造技术。可实现通过纳米线的垂直架构扩展。这里允许使用纳米线在晶体管层本身内构造电路。
图6示出根据一实施例的计算机系统。在一些实施例中，系统600 包括处理器610、存储器器件620、存储器控制器630、图形控制器640、输入和输出(I/O)控制器650、显示器652、键盘654、定点设备656、外围设备658，所有这些部件通过总线660可通信地彼此耦合。处理器610 可以是通用处理器或专用集成电路(ASIC)。I/O控制器650可包括用于有线或无线通信的通信模块。存储器设备620可以是动态随机存取存储器 (DRAM)器件、静态随机存取存储器(SRAM)器件、闪存器件或这些存储器器件的组合。因此，在一些实施例中，系统600中的存储器器件620 不一定包括DRAM器件。
系统600中所示的一个或多个部件可包括本文中包含的各实施例中的一个或多个纳米线器件。例如，处理器610或存储器器件620或I/O 控制器650的至少一部分或这些部件的组合可包括在集成电路组件中，该集成电路组件包括本文所述结构的至少一个实施例。
这些部件执行它们业内公知的传统功能。尤其，在由处理器710执行期间，存储器设备620在某些情形下可用于提供对形成根据一些实施例的结构的方法的可执行指令的长期存储，而在其它实施例中可用来短期地存储用于形成根据这些实施例的结构的方法的可执行指令。另外，指令可被存储或以其它方式关联于与系统可通信耦合的机器可访问介质，机器可访问介质例如是紧凑盘只读存储器(CD-ROM)、数字多功能盘 (DVD)、软盘、载波和/或其它传播的信号。在一个实施例中，存储器设备620可向处理器610提供可执行的指令以供执行。
系统600可包括计算机(例如台式机、膝上计算机、手持计算机、服务器、Web设备、路由器等)、无线通信设备(例如蜂窝电话、无绳电话、寻呼机、个人数字助理等)、计算机关联的外围设备(例如打印机、扫描仪、监视器等)、娱乐设备(例如电视机、收音机、立体声、磁带和压缩盘播放器、视频卡带录像机、便携式摄像机、数字照相机、MP3(运动图像专家组，音频层3)播放机、视频游戏、手表等)，诸如此类。
尽管前面的说明书具有可用于实施例中的某些特定步骤和材料，然而本领域内技术人员将理解，可作出许多修正和替代。因此，所有这些修正、改变、替代和添加都应当被认为是落在实施例由所附权利要求书定义的精神和范围内。另外要理解，诸如晶体管器件的各种微电子结构是业内已知的。因此，这里给出的附图仅示出与实施例的实践相关的一部分示例性微电子结构。因此，实施例不限于本文描述的结构。

Claims (30)

1.一种形成器件的方法，包括：
在衬底上形成外延硅锗；
在所述外延硅锗上形成外延硅；
对布置在所述外延硅锗上的所述外延硅布图以形成鳍结构；
在所述鳍结构上方形成牺牲栅电极；
在所述牺牲栅电极的侧壁附近以及所述鳍结构上方形成间隔物；
从所述衬底上的源极/漏极区去除所述鳍结构的半导体部分，然后在所述源极/漏极区上形成源极/漏极结构，其中所述源极/漏极区位于所述间隔物附近；
从所述间隔物之间去除所述牺牲栅电极；以及
从位于所述间隔物之间的所述鳍结构去除所述硅和所述外延硅锗中的一者。
2.如权利要求1所述的方法，其中，所述器件包括栅完全包围纳米线器件的一部分。
3.如权利要求1所述的方法，其还包括在外延硅上形成外延硅锗的附加交替层。
4.如权利要求3所述的方法，其中，从所述鳍结构去除所述硅以形成通过间隙彼此隔开的硅锗纳米线结构。
5.如权利要求3所述的方法，其中，从所述鳍结构去除所述硅锗以形成通过间隙彼此隔开的硅纳米线结构。
6.如权利要求4所述的方法，其中，栅极电介质被形成在所述硅锗纳米线结构的所有侧周围。
7.如权利要求5所述的方法，其中，栅极电介质被形成在所述硅纳米线结构的所有侧周围。
8.如权利要求6所述的方法，其中，栅电极材料被形成在所述硅锗纳米线结构周围。
9.如权利要求7所述的方法，其中，栅电极材料被形成在所述硅纳米线结构周围。
10.如权利要求1所述的方法，其还包括布置在所述源极/漏极结构和所述衬底之间的外延尖端。
11.如权利要求9所述的方法，其中，所述栅电极材料包括金属。
12.如权利要求8所述的方法，其中，所述栅电极材料包括金属。
13.如权利要求9所述的方法，其中，沟槽触头耦合至所述源极/漏极结构，并且所述源极/漏极结构包括n+掺杂的硅。
14.如权利要求13所述的方法，其中，硅外延尖端被布置在所述源极/漏极结构和所述衬底之间。
15.如权利要求9所述的方法，其中，所述器件包括NMOS栅完全包围沟道器件的一部分。
16.如权利要求9所述的方法，其中，沟槽触头耦合至所述源极/漏极结构，其中所述源极/漏极结构包括p+硅锗。
17.如权利要求16所述的方法，其中，硅外延尖端被布置在所述源极/漏极结构和所述衬底之间。
18.如权利要求17所述的方法，其中，所述器件包括PMOS栅完全包围沟道器件的一部分，并且其中，所述硅纳米线包括应变的硅纳米线。
19.一种形成纳米线器件的方法，包括：
在衬底上形成外延硅锗上外延硅的交替层；
对所述交替层布图以形成鳍结构；
在所述鳍结构上方形成牺牲栅电极；
在所述牺牲栅电极的侧壁附近以及所述鳍结构上方形成间隔物；
从所述衬底上的源极/漏极区去除所述鳍结构的半导体部分，然后在所述源极/漏极区上形成源极/漏极结构，其中所述源极/漏极区位于所述间隔物附近；
在从所述源极/漏极区去除所述鳍结构的所述半导体部分之后，从所述间隔物之间去除所述牺牲栅电极；以及
从位于所述间隔物之间的所述鳍结构去除所述硅和所述外延硅锗中的一者。
20.如权利要求19所述的方法，其中，所述衬底是SOI衬底，并且其中，所述鳍结构的底部纳米线几何形状是通过控制对所述SOI衬底的底部氧化物部分的蚀刻来限定的。
21.如权利要求20所述的方法，其中，所述底部氧化物被蚀刻以形成两条纳米线。
22.一种形成器件的方法，包括：
在衬底上形成牺牲材料；
在所述牺牲材料上形成外延半导体；
对布置在所述牺牲材料上的所述外延半导体布图，以形成鳍结构；
在所述鳍结构上方形成牺牲栅电极；
在所述牺牲栅电极的侧壁附近以及所述鳍结构上形成间隔物；
从所述衬底上的源极/漏极区去除所述鳍结构的半导体部分，然后在所述源极/漏极区形成源极/漏极结构，其中，所述源极/漏极区在所述间隔物附近；
从所述间隔物之间去除所述牺牲栅电极；以及
从位于所述间隔物之间的所述鳍结构去除所述牺牲材料。
23.如权利要求22所述的方法，其中，所述器件包括栅完全包围纳米线器件。
24.如权利要求22所述的方法，其还包括外延半导体和牺牲材料的附加交替层。
25.如权利要求24所述的方法，其中，所述牺牲材料从所述鳍结构被去除，以形成通过间隙彼此隔开的半导体纳米线结构。
26.如权利要求25所述的方法，其中，栅极电介质被形成在所述半导体纳米线结构的所有侧周围。
27.如权利要求26所述的方法，其中，栅电极材料被形成在所述半导体纳米线结构周围。
28.如权利要求27所述的方法，其中，所述栅电极材料包括金属。
29.如权利要求22所述的方法，其中，半导体外延尖端被布置在所述源极/漏极结构和所述衬底之间。
30.如权利要求25所述的方法，其中，半导体纳米线包括应变的半导体纳米线。
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