CN105518840B - 用于纳米线晶体管的内部间隔体及其制造方法 - Google Patents

用于纳米线晶体管的内部间隔体及其制造方法 Download PDF

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CN105518840B
CN105518840B CN201380079334.6A CN201380079334A CN105518840B CN 105518840 B CN105518840 B CN 105518840B CN 201380079334 A CN201380079334 A CN 201380079334A CN 105518840 B CN105518840 B CN 105518840B
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sacrificial
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spacers
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CN105518840A (zh
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S·金
D·西蒙
N·拉哈尔乌拉比
C-H·林
K·库恩
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Abstract

可以采用内部间隔体，来生产本说明书的纳米线晶体管，在内部间隔体制造期间，通过使用牺牲间隔体来形成内部间隔体。一旦形成了纳米线晶体管，就可以去除(分别)位于晶体管栅极以及源极和漏极之间的牺牲间隔体。然后，可以去除纳米线晶体管的沟道纳米线之间的牺牲材料，并且可以沉积电介质材料以填充沟道纳米线之间的空间。可以去除不在沟道纳米线之间的电介质材料以形成内部间隔体。然后可以与内部间隔体和晶体管沟道纳米线相邻，形成(分别)位于晶体管栅极与源极和漏极之间的外部间隔体。

Description

用于纳米线晶体管的内部间隔体及其制造方法
技术领域
本说明书的实施例总体涉及纳米线微电子器件的领域，并且更具体而言，涉及使用内部间隔体所形成的纳米线晶体管。
背景技术
集成电路部件的更高性能、更低成本、加强的微型化，以及集成电路的更大封装密度是制造微电子器件的微电子行业的一直的目标。在实现这些目标时，微电子器件减小，即，变得更小，这增加了对每种集成电路部件的最优性能的需求，包括在减小短沟道效应、寄生电容和截止状态泄漏电流的同时管理晶体管驱动电流。
非平面晶体管，例如基于鳍和纳米线的器件，使得能够改善对短沟道效应的控制。例如，在基于纳米线的晶体管中，栅极电极包裹在纳米线的整个周边周围，使能沟道区中的更完全耗尽，并减小由于更陡峭的亚阈值电流摆幅(SS)和更小的漏极感应势垒降低(DIBL)导致的短沟道效应。纳米线器件中使用的周围包裹的栅极结构和源极/漏极接触还使得能够更好地管理有源区中的泄漏电流和电容，即使在驱动电流增大时也是如此，如本领域的技术人员将要理解的那样。
附图说明
在说明书的结论部分中具体指出并明确主张了本公开内容的主题。根据结合附图的以下描述及附属权利要求，本公开内容的上述和其它特征将变得更加完全地显而易见。要理解的是，附图仅仅示出了根据本公开内容的几个实施例，并且因此，不应被视为限制其范围。将利用附图以额外的特异性和细节来描述本公开内容，从而可以更容易确定本公开内容的优点，其中：
图1-17是根据本说明书的实施例的形成纳米线晶体管的过程的斜视图及侧视图。
图18是根据本说明书的实施例的制造纳米线晶体管的过程的流程图。
图19图示了根据本说明书的一种实施方式的计算设备。
具体实施方式
在以下具体实施方式中，参考了附图，附图通过图示方式示出了可以实践所主张的主题的具体实施例。这些实施例得到充分详细的描述，以使本领域的技术人员能够实践该主题。应当理解，各实施例尽管不同，但未必是相互排斥的。例如，可以在其它实施例中实施结合一个实施例在本文中描述的特定特征、结构或特性而不脱离所主张主题的精神和范围。在本说明书之内提到“一个实施例”或“实施例”表示结合实施例描述的特定特征、结构或特性被包括在本说明书之内所涵盖的至少一个实施方式中。因此，短语“一个实施例”或“在实施例中”的使用，未必是指相同实施例。此外，要理解的是，可以修改每个公开实施例之内独立的元件的位置或布置而不脱离所主张主题的精神和范围。因此，不应以限制性意义来理解以下具体实施方式，并且所主张主题的范围仅受经适当解释的附属权利要求连同附属权利要求所授权的等价物的全范围的限定。在附图中，相同的标号在所有几幅视图中指相同或相似的元件或功能，并且其中绘示的元件未必与彼此成比例，相反，可以放大或缩小独立的元件，以便在本说明书的语境中更容易理解该元件。
如本说明书中所使用的术语“牺牲”是指暂时形成并将被去除并由另一种结构或材料替代的结构或材料。如本文中使用的术语“在……上方”、“到”、“在……之间”和“在……上”可以指一层相对于其它层的相对位置。在另一层“上方”或“上”或结合“到”另一层的一层可以直接接触另一层，或者可以有一个或多个居间层。层“之间”的一层可以直接与这些层接触，或者可以具有一个或多个居间层。
本说明书的实施例包括在纳米线晶体管中并入内部间隔体。在一个实施例中，可以在内部间隔体制造期间，通过使用外部牺牲间隔体来形成内部间隔体。一旦形成了纳米线晶体管，就可以去除(分别)位于栅极结构(例如，栅极电极和栅极电介质)以及源极结构和漏极结构之间的牺牲间隔体。然后可以去除纳米线晶体管的沟道纳米线之间的牺牲材料，并可以沉积电介质材料以填充沟道纳米线之间的空间。可以去除不在沟道纳米线之间的电介质材料以形成内部间隔体。然后可以与内部间隔体和晶体管沟道纳米线相邻，形成(分别)位于栅极结构与源极结构和漏极结构之间的外部间隔体。内部间隔体可以提供栅极结构和源极/漏极接触之间的额外绝缘，这样减小了交叠电容、短路风险和电流泄露。内部间隔体可以由绝缘的、低k电介质材料形成。此外，内部间隔体可以由与外部间隔体相同或不同的材料形成。此外，内部间隔体可以与外部间隔体的厚度相同或不同。
图1-17图示了形成纳米线晶体管的方法。出于简洁和清楚的目的，将图示单纳米线晶体管的形成。如图1所示，微电子衬底110可以由任何适当的材料来提供或形成。在一个实施例中，微电子衬底110可以是由单晶材料形成的体衬底，单晶材料可以包括，但不限于硅、锗、硅-锗或Ⅲ-Ⅴ族化合物半导体材料。在其它实施例中，微电子衬底110可以包括绝缘体上硅衬底(SOI)，其中，在体衬底上设置了由可以包括但不限于二氧化硅、氮化硅或氮氧化硅的材料形成的上方绝缘体层。或者，微电子衬底110可以直接由体衬底形成，并使用局部氧化形成电绝缘部分以替代上述上方绝缘体层。
如图1中进一步所示，可以由任何已知技术，例如外延生长，在微电子衬底110上形成与多个沟道材料层(图示为元件1241、1242和1243)交替的多个牺牲材料层(图示为元件1221、1222和1223)，以形成分层堆叠体126。在一个实施例中，牺牲材料层1221、1222和1223可以是硅层，并且沟道材料层1241、1242和1243可以是硅锗层。在另一实施例中，牺牲材料层1221、1222和1223可以是硅锗层，并且沟道材料层1241、1242和1243可以是硅层。此外，沟道材料层1241、1242和1243还可以包括，但不限于，锗、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb和InP。尽管示出了三个牺牲材料层和三个沟道材料，但要理解可以使用任何适当数量的牺牲材料层和沟道材料层。
可以使用常规构图/蚀刻技术对分层的堆叠体126进行构图，以形成至少一个鳍结构128，如图2所示。例如，可以在沟槽蚀刻过程期间，例如在浅沟槽隔离(STI)过程期间，来蚀刻分层堆叠体126(见图1)，其中，可以在形成鳍结构128时在微电子衬底110中形成沟槽134，并且其中，可以在鳍结构128的相对侧上形成沟槽134。本领域的技术人员将要理解，一般同时形成多个基本平行的鳍结构128。
如图3所示，可以在邻近微电子衬底110的沟槽134之内形成或沉积电介质材料结构136，例如二氧化硅，以电学地分离鳍结构128。本领域的技术人员应当理解，形成电介质材料结构136的过程可以涉及多种过程，包括但不限于，沉积电介质材料、对电介质材料进行抛光/平坦化和回蚀电介质材料。
如图4所示，第一牺牲间隔体152和第二牺牲间隔体154可以形成在鳍结构128上并跨越鳍结构128，并且可以设置为基本关于鳍结构128正交。在实施例中，第一牺牲间隔体152和/或第二牺牲间隔体154可以包括可以被去除而不影响牺牲栅极材料、源极结构或漏极材料(接下来将论述其每者)的任何电介质材料，并可以包括，但不限于二氧化硅、氮化硅和氮氧化硅。
如图4进一步所示，可以在第一牺牲间隔体152和第二牺牲间隔体154之内/之间，以及在位于第一牺牲间隔体152和第二牺牲间隔体154之间的鳍结构128的部分周围，来形成牺牲栅极材料142。在实施例中，可以在鳍结构128的部分周围形成牺牲栅极材料142，并且第一牺牲间隔体152和第二牺牲间隔体154可以在牺牲栅极材料142的相对侧上。牺牲栅极材料142可以包括任何适当的牺牲材料，包括，但不限于多晶硅、氮化硅和二氧化硅。
如图5所示，可以去除每个鳍结构128的在牺牲栅极材料142、第一牺牲间隔体152和第二牺牲间隔体154外部的部分，以暴露微电子衬底110的部分112。可以通过现有技术中已知的任何工艺，包括但不限于干法蚀刻工艺，来去除每个鳍结构128的部分。
如图6所示，可以例如通过硅或硅锗的外延生长，在鳍结构128的相对端上的微电子衬底部分112(见图6)上形成源极结构160和漏极结构170，它们可以耦合到设置于第一牺牲间隔体152和第二牺牲间隔体154之间的鳍结构128的部分。在实施例中，根据用于具体应用的器件类型，源极结构160或漏极结构170可以是用于NMOS器件的n掺杂硅，或者可以是用于PMOS器件的p掺杂硅/硅锗。可以在外延工艺中通过注入、通过等离子体掺杂、通过固体源掺杂或通过现有技术中已知的其它方法来引入掺杂。
如图7所示，可以在微电子衬底110上，在源极结构160、漏极结构170、牺牲栅极材料142、第一牺牲间隔体152和第二牺牲间隔体154上方形成层间电介质层180，其中，可以例如通过化学机械抛光来对层间电介质层180进行平面化，以暴露第一牺牲间隔体152、第二牺牲间隔体154和牺牲栅极材料142。
然后，如图8所示，可以例如通过蚀刻工艺，从第一牺牲间隔体152和第二牺牲间隔体154之间去除牺牲栅极材料142，蚀刻工艺包括，但不限于湿法蚀刻、湿法蚀刻和氧化的组合或干法蚀刻(等离子体或无等离子体蚀刻)。
如图9所示，可以在沟道材料层1241、1242和1243(见图8)之间从鳍结构128(见图8)选择性地去除牺牲材料层1221、1222和1223(见图8)，以形成在源极结构160(见图6)和漏极结构170之间延伸的沟道纳米线(图示为元件1201、1202和1203，并且在这里可以被统称为“沟道纳米线120n”)，其中，沟道纳米线120n可以被垂直(例如，z方向)对准并与彼此间隔开。在实施例中，可以利用选择性去除牺牲材料层1221、1222和1223而不蚀刻沟道材料层1241、1242和1243的湿法蚀刻、湿法蚀刻和氧化的组合或干法蚀刻(等离子体或无等离子体)，来蚀刻牺牲材料层1221、1222和1223。在一个实施例中，其中牺牲材料层1221、1222和1223是硅并且沟道材料层1241、1242和1243是硅锗，湿法蚀刻可以包括，但不限于包括氢氧化铵和氢氧化钾的含水氢氧化物化学物。在另一实施例中,其中牺牲材料层1221、1222和1223是硅锗并且沟道材料层1241、1242和1243是硅，湿法蚀刻可以包括，但不限于碳酸/硝酸/氢氟酸溶液和柠檬酸/硝酸/氢氟酸的溶液。
在实施例中，硅和硅锗沟道纳米线120n都可以存在于同一晶片上、同一管芯中或同一电路上，例如作为反相器结构中的NMOS Si和PMOS SiGe。在NMOS Si和PMOS SiGe都在同一电路中的实施例中，可以相互选择Si沟道厚度(SiGe居间层)和SiGe沟道厚度(Si居间层)以提高电路性能和/或电路最小工作电压。在实施例中，可以通过蚀刻工艺来改变同一电路中不同器件上的纳米线数量，以提高电路性能和/或电路最小工作电压。
如图10所示(沿图9的线10-10的横截面)，可以形成栅极电介质材料182，以围绕第一牺牲间隔体152和第二牺牲间隔体154之间的沟道纳米线1201、1202和1203。在实施例中，栅极电介质材料182可以包括高k栅极电介质材料，其中，介电常数可以包括大于大约4的值。高k栅极电介质材料的示例可以包括，但不限于氧化铪、硅氧化铪、氧化镧、氧化锆、硅氧化锆、氧化钛、氧化钽、钛酸钡锶、钛酸钡、钛酸锶、氧化钇、氧化铝、铅氧化钪和铌锌酸铅。在一个实施例中，可以在沟道纳米线1201、1202和1203周围基本保形地形成栅极电介质材料182，并且可以在第一牺牲间隔体152和第二牺牲间隔体154上形成基本保形层。可以利用现有技术中公知的任何方法来沉积栅极电介质材料182，以获得保形层，例如，但不限于原子层沉积(ALD)和化学气相沉积(CVD)的各种实施方式，例如，大气压CVD(APCVD)、低压CVD(LPCVD)和等离子体增强CVD(PECVD)。
如图11所示，于是可以围绕沟道纳米线1201、1202和1203来形成栅极电极材料144，以形成栅极电极140并由此形成微电子结构102。栅极电极材料144可以包括任何适当的导电材料，包括，但不限于，纯金属和钛、钨、钽、铝、铜、钌、钴、铬、铁、钯、钼、锰、钒、金、银和铌的合金。也可以使用导电性较差的金属碳化物，例如，碳化钛、碳化锆、碳化钽、碳化钨和碳化钨。栅极电极材料也可以由诸如氮化钛和氮化钽的金属氮化物，或诸如氧化钌的导电金属氧化物制成。栅极电极材料还可以包括与诸如铽和镝的稀土元素的合金，或诸如铂的贵金属。
如图12和13所示，可以去除第一牺牲间隔体152和第二牺牲间隔体154(见图11)。可以由包括但不限于蚀刻工艺的任何适当的工艺，来去除第一牺牲间隔体152和第二牺牲间隔体154。
如图13所示，(沿图12的线13-13的侧视图)，第一牺牲间隔体152和第二牺牲间隔体154的去除暴露了牺牲材料层1221、1222和1223。如图14所示，可以通过选择性地去除牺牲材料层1221、1222和1223而不蚀刻沟道纳米线1241、1242和1243的任何适当技术，例如湿法蚀刻、湿法蚀刻和氧化的组合或干法蚀刻(等离子体或无等离子体)，来去除牺牲材料层1221、1222和1223。在一个实施例中，其中牺牲材料层1221、1222和1223是硅并且沟道纳米线1241、1242和1243是硅锗，湿法蚀刻可以包括，但不限于包括氢氧化铵和氢氧化钾的含水氢氧化物化学物质。在另一实施例中，其中牺牲材料层1221、1222和1223是硅锗并且沟道纳米线1241、1242和1243是硅，湿法蚀刻可以包括，但不限于碳酸/硝酸/氢氟酸溶液和柠檬酸/硝酸/氢氟酸溶液。
如图15所示，可以沉积间隔体材料以形成填充沟道纳米线1241、1242和1243(见图14)之间的空间的第一间隔体192和第二间隔体194，以形成纳米线器件100。用于形成第一间隔体192和第二间隔体194的间隔体材料可以是任何适当的电介质材料，例如，二氧化硅、氮氧化硅或氮化硅。在实施例中，间隔体材料是低k电介质材料，即，具有小于3.6的介电常数。
在图16所示的另一实施例中，可以去除第一间隔体192和第二间隔体194的一部分，以在沟道纳米线1241、1242和1243之间界定内部间隔体1901、1902和1903。如图17所示，然后可以沉积与内部间隔体1901、1902和1903的电介质材料不同的电介质材料以形成围绕内部间隔体1901、1902和1903以及沟道纳米线1201、1202和1203(见图16)并位于栅极电极140及其相应的源极结构160或漏极结构170之间的第一外部间隔体196和第二外部间隔体198。
图18是根据本说明书的实施例的制造纳米线晶体管结构的过程200的流程图。如方框202中所述，可以形成微电子衬底。如方框204中所述，可以在微电子衬底上形成包括至少一个牺牲材料层和至少一个沟道材料层的堆叠层。如方框206中所述，可以由分层堆叠形成至少一个鳍结构，如方框208中所述。如方框208中所述，可以跨越鳍结构形成至少两个牺牲间隔体。可以在至少两个牺牲间隔体之间形成牺牲栅极材料，如方框210中所述。如方框212中所述，可以去除鳍结构在牺牲栅极材料和间隔体以外的部分，以暴露微电子衬底的部分。可以在鳍结构的相对端上的微电子衬底部分上形成源极结构和漏极结构，如在方框214中所述。可以在源极结构和漏极结构上方形成层间电介质层，如方框216中所述。可以在间隔体之间去除牺牲栅极材料，如方框218中所述。如方框220中所述，可以从沟道材料层之间选择性地去除牺牲材料层，以形成至少一个沟道纳米线。如方框222中所述，可以形成栅极电介质材料以在间隔体之间围绕沟道纳米线。可以在栅极电介质材料上形成栅极电极材料，如方框224中所述。如方框226中所述，可以去除牺牲间隔体。可以选择性地去除沟道纳米线之间的牺牲材料层，如方框228中所述。如方框230中所述，可以沉积电介质材料，以形成至少一个间隔体，其中，将电介质材料设置于沟道纳米线之间。
图19示出了根据本说明书的一个实施方式的计算设备300。计算设备300容纳板302。板302可以包括多个部件，该多个部件包括但不限于处理器304和至少一个通信芯片306。处理器304物理地和电地耦合到板302。在一些实施方式中，至少一个通信芯片306也物理地和电地耦合到板302。在另外的实施方式中，通信芯片306是处理器304的一部分。
取决于计算设备300的应用，计算设备300可以包括其它部件，这些部件可以或可以不物理地和电地耦合到板302。这些其它部件包括但不限于，易失性存储器(例如，DRAM)、非易失性存储器(例如，ROM)、闪存存储器、图形处理器、数字信号处理器、密码处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编解码器、视频编解码器、功率放大器、全球定位系统(GPS)设备、罗盘、加速度计、陀螺仪、扬声器、照相机、以及大容量存储设备(例如，硬盘驱动器、光盘(CD)、数字多功能盘(DVD)等)。
通信芯片306使能用于来往于计算设备300的数据的传输的无线通信。术语“无线”及其派生词可以用于描述可以通过使用经由非固体介质调制的电磁辐射来传送数据的电路、设备、系统、方法、技术、通信信道等。该术语并不暗示相关联的设备不包含任何接线，尽管在一些实施例中它们可以不包含接线。通信芯片306可以实施多种无线标准或协议中的任何无线标准或协议，包括但不限于：Wi-Fi(IEEE 802.11族)、WiMAX(IEEE 802.16族)、IEEE 802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、及其派生物，以及被称为3G、4G、5G或更高代的任何其它无线协议。计算设备300可以包括多个通信芯片306。例如，第一通信芯片306可以专用于诸如Wi-Fi和蓝牙等较短距离无线通信，并且第二通信芯片306可以专用于诸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等较长距离无线通信。
计算设备300的处理器304包括封装在处理器304内的集成电路管芯。在本说明书的一些实施方式中，处理器的集成电路管芯包括一个或多个器件，例如，根据本说明书的实施方式所构建的纳米线晶体管。术语“处理器”可以指代处理来自寄存器和/或存储器的电子数据以将该电子数据转换成可以被存储在寄存器和/或存储器中的其它电子数据的任何设备或设备的部分。
通信芯片306还包括封装在通信芯片306内的集成电路管芯。根据本说明书的另一个实施方式，通信芯片的集成电路管芯包括一个或多个器件，例如，根据本说明书的实施方式所构建的纳米线晶体管。
在另外的实施方式中，计算设备300内所容纳的另一个部件可以包含集成电路管芯，该集成电路管芯包括一个或多个器件，例如，根据本说明书的实施方式所构建的纳米线晶体管。
在各种实施方式中，计算设备300可以是膝上型电脑、上网本、笔记本、超级本、智能电话、平板电脑、个人数字助理(PDA)、超级移动PC、移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字照相机、便携式音乐播放器、或数字视频录像机。在另外的实施方式中，计算设备300可以是处理数据的任何其它电子设备。
要理解的是，本说明书的主题未必限于图1-19中所图示的特定应用。本领域的技术人员将要理解，可以将该主题应用于其它微电子器件和组件应用以及任何适当的晶体管应用。
以下示例涉及进一步的实施例，其中，示例1是一种形成纳米线晶体管的方法，包括：提供微电子结构，所述微电子结构具有：设置在衬底上的鳍结构，其具有多个沟道纳米线；邻接所述鳍结构的一部分的栅极电极，其中，所述栅极电极围绕所述鳍结构中的所述多个沟道纳米线中的每个沟道纳米线；邻接所述栅极电极的一端的牺牲间隔体，其中，所述间隔体邻接所述鳍结构中的包括由牺牲材料分开的所述沟道纳米线的部分；以及邻接所述鳍结构的一端和所述牺牲间隔体的源极和漏极的其中之一；去除所述牺牲间隔体；从所述沟道纳米线之间去除所述牺牲材料；以及沉积电介质材料以形成间隔体，其中，所述电介质材料设置在所述沟道纳米线之间。
在示例2中，示例1的主题可以可选地包括沉积电介质材料以形成间隔体，这包括沉积低k电介质材料以形成间隔体。
在示例3中，示例1至2中的任一个的主题可以可选地包括牺牲间隔体，牺牲间隔体包括二氧化硅、氮化硅和氮氧化硅中的至少一种。
在示例4中，示例1至3中的任一个的主题可以可选地包括去除间隔体的一部分以在沟道纳米线之间界定内部间隔体；以及沉积与内部间隔体的电介质材料不同的另一种电介质材料，以在栅极电极与源极和漏极的其中之一之间形成外部间隔体，其中，外部间隔体围绕内部间隔体和沟道纳米线。
在示例5中，示例1至4中的任一个的主题可以可选地包括牺牲材料，牺牲材料包括硅，并且其中，沟道纳米线包括硅锗。
在示例6中，示例1至4中的任一个的主题可以可选地包括牺牲材料，牺牲材料包括硅锗层，并且其中，沟道纳米线包括硅。
以下示例涉及进一步的实施例，其中，示例7是一种形成纳米线晶体管的方法，包括：提供微电子结构，所述微电子结构具有：设置在衬底上的鳍结构，其具有多个沟道纳米线；邻接所述鳍结构的一部分的栅极电极，其中，所述栅极电极围绕所述鳍结构中的所述多个沟道纳米线中的每个沟道纳米线；邻接所述栅极电极的一端的第一牺牲间隔体，其中，所述第一间隔体邻接所述鳍结构中的包括由牺牲材料分开的所述沟道纳米线的部分；邻接所述栅极电极的另一端的第二牺牲间隔体，其中，所述第二牺牲间隔体邻接所述鳍结构中的包括由所述牺牲材料分开的所述多个沟道纳米线的另一部分；邻接所述鳍结构的一端和所述第一牺牲间隔体的源极；以及邻接所述鳍结构的相对端和所述第二牺牲间隔体的漏极；去除所述第一牺牲间隔体和所述第二牺牲间隔体；从所述沟道纳米线之间去除所述牺牲材料；以及沉积电介质材料以形成第一间隔体和第二间隔体，其中，所述电介质材料设置在所述沟道纳米线之间。
在示例8中，示例7的主题可以可选地包括沉积电介质材料以形成第一间隔体和第二间隔体，这包括沉积k电介质材料以形成第一间隔体和第二间隔体。
在示例9中，示例7至8中的任一个的主题可以可选地包括第一牺牲间隔体和第二牺牲间隔体的至少其中之一，牺牲间隔体包括二氧化硅、氮化硅和氮氧化硅中的至少一种。
在示例10中，示例7至9中的任一个的主题可以可选地包括去除第一间隔体的一部分和第二间隔体的一部分以在沟道纳米线之间界定内部间隔体；以及沉积与内部间隔体的电介质材料不同的电介质材料以在栅极电极和源极之间形成第一外部间隔体并且在栅极电极之间形成第二外部间隔体，其中，第一外部间隔体和第二外部间隔体围绕内部间隔体和沟道纳米线。
在示例11中，示例7至10中的任一个的主题可以可选地包括牺牲材料，所述牺牲材料包括硅，并且其中，沟道纳米线包括硅锗。
在示例12中，示例7至10中的任一个的主题可以可选地包括牺牲材料，所述牺牲材料包括硅锗层，并且其中，沟道纳米线包括硅。
以下示例涉及进一步的实施例，其中，示例13是一种形成纳米线晶体管的方法，包括：形成微电子衬底；在所述微电子衬底上形成包括至少一个牺牲材料层和至少一个沟道材料层的堆叠层；形成由分层的堆叠体所形成的至少一个鳍结构；跨越所述鳍结构形成至少两个牺牲间隔体；在所述至少两个牺牲间隔体之间形成牺牲栅极材料；去除所述鳍结构的在所述牺牲栅极材料和所述牺牲间隔体外部的部分，以暴露所述微电子衬底的部分；在所述鳍结构的相对端上的微电子衬底部分上形成源极结构和漏极结构；在所述源极结构和所述漏极结构上方形成层间电介质层；从所述牺牲间隔体之间去除所述牺牲栅极材料；从所述沟道材料层之间选择性地去除所述牺牲材料层，以形成至少一个沟道纳米线；形成栅极电介质材料以在所述至少两个牺牲间隔体之间围绕所述沟道纳米线；在所述栅极电介质材料上形成栅极电极；去除所述至少两个牺牲间隔体；在所述沟道纳米线之间选择性地去除所述牺牲材料层；以及沉积电介质材料，以形成至少一个间隔体，其中，所述电介质材料设置在所述沟道纳米线之间。
在示例14中，示例13的主题可以可选地包括沉积电介质材料以形成至少一个间隔体，这包括沉积低k电介质材料以形成至少一个间隔体。
在示例15中，示例13至14中的任一个的主题可以可选地包括至少两个牺牲间隔体的至少其中之一，牺牲间隔体包括二氧化硅、氮化硅和氮氧化硅中的至少一种。
在示例16中，示例13至15中的任一个的主题可以可选地包括去除至少一个间隔体的一部分以在沟道纳米线之间界定内部间隔体；以及沉积与内部间隔体的电介质材料不同的另一种电介质材料，以形成围绕内部间隔体和沟道纳米线的至少一个外部间隔体。
在示例17中，示例13至16中的任一个的主题可以可选地包括在微电子衬底上形成具有至少一个牺牲材料层和至少一个沟道材料层的堆叠层，这包括在微电子衬底上形成包括至少一个硅牺牲层和至少一个硅锗沟道层的堆叠层。
在示例18中，示例13至16中的任一个的主题可以可选地包括在微电子衬底上形成具有至少一个牺牲材料层和至少一个沟道材料层的堆叠层，这包括在微电子衬底上形成包括至少一个硅锗牺牲层和至少一个硅沟道层的堆叠层。
已经这样详细描述了本说明书的实施例，但要理解，由附属权利要求定义的本说明书不受以上说明书中阐述的特定细节的限制，因为在不脱离其精神或范围的情况下，其很多明显变化都是可能的。

Claims (15)

1.一种形成纳米线晶体管的方法，包括：
提供微电子结构，所述微电子结构具有：
设置在衬底上的鳍结构，所述鳍结构具有多个沟道纳米线；
邻接所述鳍结构的一部分的栅极结构，其中，所述栅极结构包括栅极电介质和栅极电极，所述栅极电介质围绕所述鳍结构中的所述多个沟道纳米线中的每个沟道纳米线，所述栅极电极邻接所述栅极电介质；
邻接所述栅极电极的一端的牺牲间隔体，其中，所述牺牲间隔体邻接所述鳍结构中的包括由牺牲材料分开的所述沟道纳米线的部分；以及
源极和漏极的其中之一，其邻接所述鳍结构的一端和所述牺牲间隔体；
去除所述牺牲间隔体；
从所述沟道纳米线之间去除所述牺牲材料；
沉积电介质材料以形成间隔体，其中，所述电介质材料设置在所述沟道纳米线之间；
去除所述间隔体的一部分，以在所述沟道纳米线之间界定内部间隔体；以及
沉积与所述内部间隔体的电介质材料不同的另一种电介质材料，以在所述栅极电极与所述源极和漏极的所述其中之一之间形成外部间隔体，其中，所述外部间隔体围绕所述内部间隔体和所述沟道纳米线，并且其中，界定所述内部间隔体和形成所述外部间隔体都发生在形成所述源极和所述漏极之后。
2.根据权利要求1所述的方法，其中，沉积所述电介质材料以形成所述间隔体包括沉积低k电介质材料以形成所述间隔体。
3.根据权利要求1所述的方法，其中，所述牺牲间隔体包括二氧化硅、氮化硅和氮氧化硅中的至少一种。
4.根据权利要求1-3中的任一项所述的方法，其中，所述牺牲材料包括硅，并且其中，所述沟道纳米线包括硅锗。
5.根据权利要求1-3中的任一项所述的方法，其中，所述牺牲材料包括硅锗层，并且其中，所述沟道纳米线包括硅。
6.一种形成纳米线晶体管的方法，包括：
提供微电子结构，所述微电子结构具有：
设置在衬底上的鳍结构，所述鳍结构具有多个沟道纳米线；
邻接所述鳍结构的一部分的栅极结构，其中，所述栅极结构包括栅极电介质和栅极电极，所述栅极电介质围绕所述鳍结构中的所述多个沟道纳米线中的每个沟道纳米线，所述栅极电极邻接所述栅极电介质；
邻接所述栅极电极的一端的第一牺牲间隔体，所述第一牺牲间隔体邻接所述鳍结构中的包括由牺牲材料分开的所述沟道纳米线的部分；
邻接所述栅极电极的另一端的第二牺牲间隔体，所述第二牺牲间隔体邻接所述鳍结构中的包括由所述牺牲材料分开的所述多个沟道纳米线的另一部分；
邻接所述鳍结构的一端和所述第一牺牲间隔体的源极；以及
邻接所述鳍结构的相对端和所述第二牺牲间隔体的漏极；
去除所述第一牺牲间隔体和所述第二牺牲间隔体；
从所述沟道纳米线之间去除所述牺牲材料；
沉积电介质材料以形成第一间隔体和第二间隔体，其中，所述电介质材料设置在所述沟道纳米线之间；
去除所述第一间隔体的一部分和所述第二间隔体的一部分，以在所述沟道纳米线之间界定内部间隔体；以及
沉积与所述内部间隔体的电介质材料不同的电介质材料，以在所述栅极电极与所述源极之间形成第一外部间隔体，并且在所述栅极电极与所述漏极之间形成第二外部间隔体，其中，所述第一外部间隔体和所述第二外部间隔体围绕所述内部间隔体和所述沟道纳米线，并且其中，界定所述内部间隔体和形成所述第一外部间隔体和所述第二外部间隔体都发生在形成所述源极和所述漏极之后。
7.根据权利要求6所述的方法，其中，沉积所述电介质材料以形成所述第一间隔体和所述第二间隔体包括沉积低k电介质材料以形成所述第一间隔体和所述第二间隔体。
8.根据权利要求6所述的方法，其中，所述第一牺牲间隔体和所述第二牺牲间隔体的至少其中之一包括二氧化硅、氮化硅和氮氧化硅中的至少一种。
9.根据权利要求6-8中的任一项所述的方法，其中，所述牺牲材料包括硅，并且其中，所述沟道纳米线包括硅锗。
10.根据权利要求6-8中的任一项所述的方法，其中，所述牺牲材料包括硅锗层，并且其中，所述沟道纳米线包括硅。
11.一种形成纳米线晶体管的方法，包括：
形成微电子衬底；
在所述微电子衬底上形成包括至少一个牺牲材料层和至少一个沟道材料层的堆叠层；
形成由分层的堆叠体所形成的至少一个鳍结构；
跨越所述鳍结构形成至少两个牺牲间隔体；
在所述至少两个牺牲间隔体之间形成牺牲栅极材料；
去除所述鳍结构的在所述牺牲栅极材料和所述牺牲间隔体外部的部分，以暴露所述微电子衬底的部分；
在所述鳍结构的相对端上的微电子衬底部分上形成源极结构和漏极结构；
在所述源极结构和所述漏极结构上方形成层间电介质层；
从所述牺牲间隔体之间去除所述牺牲栅极材料；
从所述沟道材料层之间选择性地去除所述牺牲材料层，以形成至少一个沟道纳米线；
形成栅极电介质材料以围绕所述至少两个牺牲间隔体之间的所述沟道纳米线；
在所述栅极电介质材料上形成栅极电极；
去除所述至少两个牺牲间隔体；
在所述沟道纳米线之间选择性地去除所述牺牲材料层；
沉积电介质材料，以形成至少一个间隔体，其中，所述电介质材料设置在所述沟道纳米线之间；
去除所述至少一个间隔体的一部分，以在所述沟道纳米线之间界定至少一个内部间隔体；以及
沉积与所述至少一个内部间隔体的电介质材料不同的电介质材料，以在所述栅极电极和所述源极或漏极结构之间形成至少一个外部间隔体，其中所述至少一个外部间隔体围绕所述至少一个内部间隔体和所述沟道纳米线，并且其中，界定所述至少一个内部间隔体和形成所述至少一个外部间隔体都发生在形成所述源极结构和所述漏极结构之后。
12.根据权利要求11所述的方法，其中，沉积所述电介质材料以形成所述至少一个间隔体包括沉积低k电介质材料以形成所述至少一个间隔体。
13.根据权利要求11所述的方法，其中，所述至少两个牺牲间隔体的至少其中之一包括二氧化硅、氮化硅和氮氧化硅中的至少一种。
14.根据权利要求11-13中的任一项所述的方法，其中，在所述微电子衬底上形成包括至少一个牺牲材料层和至少一个沟道材料层的堆叠层包括：在所述微电子衬底上形成包括至少一个硅牺牲层和至少一个硅锗沟道层的所述堆叠层。
15.根据权利要求11-13中的任一项所述的方法，其中，在所述微电子衬底上形成包括至少一个牺牲材料层和至少一个沟道材料层的堆叠层包括：在所述微电子衬底上形成包括至少一个硅锗牺牲层和至少一个硅沟道层的所述堆叠层。
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