TW201526238A - 奈米線電晶體之內部間隔物及其製造方法 - Google Patents

奈米線電晶體之內部間隔物及其製造方法 Download PDF

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TW201526238A
TW201526238A TW103132993A TW103132993A TW201526238A TW 201526238 A TW201526238 A TW 201526238A TW 103132993 A TW103132993 A TW 103132993A TW 103132993 A TW103132993 A TW 103132993A TW 201526238 A TW201526238 A TW 201526238A
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sacrificial
channel
gate
layer
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TWI556435B (zh
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Sei-Yon Kim
Daniel A Simon
Nadia Rahhal-Orabi
Chul-Hyun Lim
Kelin J Kuhn
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Intel Corp
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    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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Abstract

本說明之一種奈米線電晶體可能生產具有藉由在其製造期間使用犧牲間隔物所形成的內部間隔物。一旦形成了奈米線電晶體，就可能移除犧牲間隔物，其(分別)係在電晶體閘極與源極和汲極之間的位置。可能接著移除在奈米線電晶體的通道奈米線之間的犧牲材料且可能沉積一介電材料以填充在通道奈米線之間的間隔。可能移除不在通道奈米線之間的介電材料以形成內部間隔物。可能接著相鄰於內部間隔物和電晶體通道奈米線地形成外部間隔物，其(分別)係在電晶體閘極與源極和汲極之間的位置。

Description

奈米線電晶體之內部間隔物及其製造方法
本說明之實施例一般關於奈米線微電子裝置的領域，尤其是，關於使用內部間隔物所形成的奈米線電晶體。
積體電路的更高效能、更低成本、增加之最小化的積體電路元件、以及更大封裝密度係用於微電子裝置之製造之微電子工業正在發展的目標。隨著實現這些目標，微電子裝置縮小(即，變得更小)，其從每個積體電路元件增加對最佳效能的需要，包括管理電晶體驅動電流，同時降低短通道效應、寄生電容、及截止狀態洩漏。
非平面電晶體(如鰭片和奈米線為基的裝置)能提高控制短通道效應。例如，在奈米線為基的電晶體中，閘極電極環繞奈米線的全周長，在通道區中能更充分地耗盡，且由於較陡的次臨界電流擺幅(SS)和較小的汲極感應障壁降低(DIBL)而降低短通道效應。在奈米線裝置中使用的環繞式閘極結構和源極/汲極接點也能更好地管理在有 效區域中的洩漏和電容，甚至隨著驅動電流而增加，如本領域之那些技術者所將了解。
110‧‧‧微電子基板
1221‧‧‧犧牲材料層
1222‧‧‧犧牲材料層
1223‧‧‧犧牲材料層
1241‧‧‧通道材料層
1242‧‧‧通道材料層
1243‧‧‧通道材料層
126‧‧‧層狀堆疊
128‧‧‧鰭片結構
134‧‧‧溝槽
136‧‧‧介電材料結構
142‧‧‧犧牲閘極材料
152‧‧‧第一犧牲間隔物
154‧‧‧第二犧牲間隔物
112‧‧‧部分
160‧‧‧源極結構
170‧‧‧汲極結構
180‧‧‧層間介電層
1201‧‧‧通道奈米線
1202‧‧‧通道奈米線
1203‧‧‧通道奈米線
182‧‧‧閘極介電材料
102‧‧‧微電子結構
140‧‧‧閘極電極
144‧‧‧閘極電極材料
100‧‧‧奈米線裝置
192‧‧‧第一間隔物
194‧‧‧第二間隔物
1901‧‧‧內部間隔物
1902‧‧‧內部間隔物
1903‧‧‧內部間隔物
196‧‧‧第一外部間隔物
198‧‧‧第二外部間隔物
200‧‧‧程序
202-230‧‧‧方塊
300‧‧‧計算裝置
302‧‧‧主機板
304‧‧‧處理器
306‧‧‧通訊晶片
在本說明書的結論部分中特別地指出並清楚地主張本揭露之主題。本揭露之上述及其他特徵將從下面的說明及所附之申請專利範圍、結合附圖變得更完全地顯而易見。了解附圖僅描繪依照本揭露之數個實施例，且因此不被認為限制其範圍。將透過使用附圖以附加特徵和細節來說明本揭露，使得能更容易地確定本揭露之優點，其中：第1-17圖係根據本說明之一實施例之形成奈米線電晶體的程序之斜視和側視圖。
第18圖係根據本說明之一實施例之製造奈米線電晶體的程序之流程圖。
第19圖繪示依照本說明之一個實作的計算裝置。
【發明內容及實施方式】
在下面的詳細說明中，參考附圖，其透過圖示來顯示其中可能實行所主張之主題的具體實施例。充分詳細地說明這些實施例以使本領域之那些技術者能實行主題。將了解各種實施例雖然不同，但不一定是互斥的。例如，結合一實施例之本文所述的特定特徵、結構、或特性 在不脫離所主張主題之精神和範圍下可能在其他實施例內實作。在本說明書內提到「一個實施例」或「一實施例」表示結合實施例所述之特定特徵、結構、或特性係包括在包含在本說明內的至少一實作中。因此，使用「一個實施例」或「在一實施例中」之說法不一定都指相同實施例。另外，將了解在每個揭露之實施例內之個別元件的位置或佈置在不脫離所主張主題之精神和範圍下可能被修改。因此，下面的詳細說明不被視為限制意義，且主題之範圍係僅由所附之申請專利範圍定義，連同被賦予所附之申請專利範圍權利之等效範圍的全範圍一起被適當地解釋。在圖中，類似數字係指整篇數個圖的相同或類似元件或功能，且本文所示之元件不一定彼此縮放，而是個別元件可能被放大或縮小以更容易地了解在本說明之內文中的元件。
如本說明所使用的「犧牲」之詞係指暫時地形成且將被移除並以另一結構或材料替代的結構或材料。如本文所使用之「上方」、「至」、「之間」和「上」之詞可能指一層相對於其他層的相對位置。在另一層「上方」或「上」或黏合「至」另一層的一層可能與另一層直接接觸或可能具有一或更多中間層。在層「之間」的一層可能與層直接接觸或可能具有一或更多中間層。
本說明之實施例包括在奈米線電晶體中結合內部間隔物。在一實施例中，內部間隔物可能在其製造期間藉由使用犧牲外部間隔物來形成。一旦形成了奈米線電晶體，就可能移除犧牲間隔物，其(分別)係在閘極結構(例 如，閘極電極和閘極介電質)與源極結構和汲極結構之間的位置。可能接著移除在奈米線電晶體的通道奈米線之間的犧牲材料且可能沉積一介電材料以填充在通道奈米線之間的間隔。可能移除不在通道奈米線之間的介電材料以形成內部間隔物。接著可能相鄰於內部間隔物和電晶體通道奈米線地形成外部間隔物，其(分別)係在閘極結構與源極結構和汲極結構之間的位置。內部間隔物可能在閘極結構與源極/汲極接點之間提供額外絕緣，其降低重疊電容、短路風險、及電流洩漏。內部間隔物可能由絕緣、低k介電材料形成。再者，內部間隔物可能由與外部間隔物相同或不同的材料形成。此外，內部間隔物可能與外部間隔物相同或不同的厚度成。
第1-17圖繪示形成奈米線電晶體的方法。為了簡明和清楚起見，將繪示出單一奈米線電晶體之形成。如第1圖所示，可能從任何適當材料提供或形成微電子基板110。在一實施例中，微電子基板110可能是由可能包括，但不限於矽、鍺、鍺化矽或Ⅲ-V化合物半導體材料的材料之單晶組成的塊體基板。在其他實施例中，微電子基板110可能包含絕緣體上覆矽基板(SOI)，其中由可能包括，但不限於二氧化矽、氮化矽或氧氮化矽之材料組成的上絕緣體層係設置在塊體基板上。另外，可能從塊體基板直接地形成微電子基板110且使用局部氧化來形成電絕緣部分來代替上述上絕緣體層。
如第1圖進一步所示，與複數個通道材料層 (繪示成元件1241、1242、和1243)交替的複數個犧牲材料層(繪示成1221、1222、和1223)可能藉由任何已知技術(例如，藉由外延生長)來形成在微電子基板110上以形成層狀堆疊126。在一實施例中，犧牲材料層1221、1222、和1223可能是矽層，且通道材料層1241、1242、和1243可能是鍺化矽層。在另一實施例中，犧牲材料層1221、1222、和1223可能是鍺化矽層，且通道材料層1241、1242、和1243可能是矽層。此外，通道材料層1241、1242、和1243可能也包括，但不限於鍺、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、和InP。雖然顯示出三個犧牲材料層和三個通道材料層，但了解可能使用任何適當數量的犧牲材料層和通道材料層。
可能使用傳統圖案化/蝕刻技術來圖案化層狀堆疊126以形成至少一鰭片結構128，如第2圖所示。例如，層狀堆疊126(參見第1圖)可能在溝槽蝕刻程序期間(如在淺溝槽隔離(STI)程序期間)被蝕刻，其中溝槽134在形成鰭片結構128中可能形成在微電子基板110中，且其中溝槽134可能形成在鰭片結構128的相對側上。如本領域之那些技術者所將了解，通常同時地形成複數個實質上平行的鰭片結構128。
如第3圖所示，介電材料結構136(如二氧化矽)可能形成或沉積在接近微電子基板110的溝槽134內以電性分離鰭片結構128。如本領域之那些技術者所將了解，形成介電材料結構136的程序可能包含各種程序，包 括但不限於沉積介電材料、拋光/平面化介電材料、及回蝕介電材料。
如第4圖所示，第一犧牲間隔物152和第二犧牲間隔物154可能形成在和跨過鰭片結構128上，且可能實質上正交於鰭片結構128地設置。在一實施例中，第一犧牲間隔物152及/或第二犧牲間隔物154可能包含能被移除而不影響犧牲閘極材料、源極結構、或汲極材料(其中之各者將隨後被討論)的任何介電材料，且可能包括，但不限於二氧化矽、氮化矽、及氧氮化矽。
如第4圖中進一步所示，犧牲閘極材料142可能形成在第一犧牲間隔物152與第二犧牲間隔物154內/之間，且可能形成在位於第一犧牲間隔物152與第二犧牲間隔物154之間之鰭片結構128的部分周圍。在一實施例中，犧牲閘極材料142可能形成在鰭片結構128的部分周圍，且第一犧牲間隔物152和第二犧牲間隔物154可能在犧牲閘極材料142的相對側上。犧牲閘極材料142可能包含任何適當的犧牲材料，包括但不限於多晶矽、氮化矽、及二氧化矽。
如第5圖所示，可能移除在犧牲閘極材料142、第一犧牲間隔物152、和第二犧牲間隔物154外部之每個鰭片結構128的一部分以暴露微電子基板110的部分112。可能藉由本領域所知的任何程序(包括但不限於乾蝕刻程序)來移除每個鰭片結構128的部分。
如第6圖所示，源極結構160和汲極結構170 可能形成在鰭片結構128之相對端上的微電子基板部分112(參見第6圖)上(例如藉由矽或鍺化矽的外延生長)，且可能耦接至設置於第一犧牲間隔物152與第二犧牲間隔物154之間之鰭片結構128的部分。在一實施例中，源極結構160或汲極結構170可能是用於NMOS裝置的n摻雜矽，或可能是用於PMOS裝置的p摻雜矽/鍺化矽，這取決於用於特定應用的裝置類型。可能藉由植入、藉由電漿摻雜、藉由固體來源摻雜或藉由如本領域所知的其他方法來在外延程序中引入摻雜。
如第7圖所示，層間介電層180可能形成在源極結構160、汲極結構170、犧牲閘極材料142、第一犧牲間隔物152、和第二犧牲間隔物154上方的微電子基板110上，其中可能例如藉由化學機械拋光來平面化層間介電層180以暴露第一犧牲間隔物152、第二犧牲間隔物154、和犧牲閘極材料142。
如第8圖所示，接著可能例如藉由蝕刻程序(包括但不限於濕蝕刻、濕蝕刻與氧化之組合、或乾蝕刻(電漿或無電漿蝕刻))來從第一犧牲間隔物152與第二犧牲間隔物154之間移除犧牲閘極材料142。
如第9圖所示，可能從在通道材料層1241、1242、和1243(參見第8圖)之間的鰭片結構128(參見第8圖)選擇性地移除犧牲材料層1221、1222、和1223(參見第8圖)以形成在源極結構160(參見第6圖)與汲極結構170之間延伸的通道奈米線(繪示成1201、1202、和1203，且 可能在本文中統稱為「通道奈米線120n」)，其中通道奈米線120n可能被垂直地排列(例如，z方向)且彼此隔開。在一實施例中，可能以濕蝕刻、濕蝕刻與氧化之組合、或乾蝕刻(電漿或無電漿)來蝕刻犧牲材料層1221、1222、和1223，其選擇性地移除犧性材料層1221、1222、和1223，而不蝕刻通道材料層1241、1242、和1243。在一實施例中，其中犧牲材料層1221、1222、和1223係矽且通道材料層1241、1242、和1243係鍺化矽，濕蝕刻可能包括，但不限於水性氫氧化物化學，包括氫氧化銨和氫氧化鉀。在另一實施例中，其中犧牲材料層1221、1222、和1223係鍺化矽且通道材料層1241、1242、和1243係矽，濕蝕刻可能包括，但不限於羧酸/硝酸/氫氟酸的溶液、和檸檬酸/硝酸/氫氟酸的溶液。
在一實施例中，矽和鍺化矽兩者的通道奈米線120n可能存在於與例如在反向器結構中之NMOS Si和PMOS SiGe相同的晶圓上、相同的晶粒中、或相同的電路上。在具有在相同電路中之NMOS Si和PMOS SiGe的一實施例中，可能相互選擇Si通道厚度(SiGe層間)和SiGe通道厚度(Si層間)以提高電路效能及/或電路最小操作電壓。在一實施例中，可能透過蝕刻程序來改變在相同電路中之不同裝置上的奈米線數量以提高電路效能及/或電路最小操作電壓。
如第10圖所示(沿著第9圖之線10-10的剖面)，可能形成閘極介電材料182以圍繞在第一犧牲間隔 物152與第二犧牲間隔物154之間的通道奈米線1201、1202、和1203。在一實施例中，閘極介電材料182可能包含高k閘極介電材料，其中介電常數可能包含大於約4的值。高k閘極介電材料的實例可能包括但不限於氧化鉿，氧化鉿矽，氧化鑭，氧化鋯，氧化鋯矽，氧化鈦，氧化鉭、鈦酸鍶鋇、鈦酸鋇、鈦酸鍶、氧化釔、氧化鋁、氧化鉛鈧鉭、及鈮酸鉛鋅。在一實施例中，閘極介電材料182可能實質上保形地形成在通道奈米線1201、1202、和1203周圍，且可能實質上保形地形成在第一犧牲間隔物152和第二犧牲間隔物154上。可能使用本領域熟知的任何方法來沉積閘極介電材料182以產生保形層，例如，但不限於原子層沉積(ALD)和化學蒸氣沉積(CVD)的各種實作，例如大氣壓力CVD(APCVD)、低壓CVD(LPCVD)、和電漿增強CVD(PECVD)。
如第11圖所示，閘極電極材料144可能接著形成在通道奈米線1201、1202、和1203周圍以形成閘極電極140且藉此形成微電子結構102。閘極電極材料144可能包含任何適當的導電材料，包括，但不限於純金屬和鈦、鎢、鉭、鋁、銅、釕、鈷、鉻、鐵、鈀、鉬、錳、釩、金、銀與鈮的合金。可能也使用較低導電的材料碳化物，例如，碳化鈦、碳化鋯、碳化鉭，碳化鎢、和碳化鎢。閘極電極材料可能也從如碳化鈦和氮化鉭的金屬氮化物、或如氧化釕的導電金屬氧化物製成。閘極電極材料可能也包括具有如鋱和鏑之稀土的合金、或如白金的貴金 屬。
如第12和13圖所示，可能移除第一犧牲間隔物152和第二犧牲間隔物154(參見第11圖)。可能藉由任何適當程序(包括，但不限於蝕刻程序)來移除第一犧牲間隔物152和第二犧牲間隔物154。
如第13圖所示(沿著第12圖之線13-13的側視圖)，移除第一犧牲間隔物152和第二犧牲間隔物154暴露犧牲材料層1221、1222、和1223。如第14圖所示，可能藉由任何適當技術(例如濕蝕刻、濕蝕刻與氧化之組合、或乾蝕刻(電漿或無電漿蝕刻))來移除犧牲材料層1221、1222、和1223，其選擇性地移除犧牲材料層1221、1222、和1223，而不蝕刻通道奈米線1241、1242、和1243。在一實施例中，其中犧牲材料層1221、1222、和1223係矽且通道奈米線1241、1242、和1243係鍺化矽，濕蝕刻可能包括，但不限於水性氫氧化物化學，包括氫氧化銨和氫氧化鉀。在另一實施例中，其中犧牲材料層1221、1222、和1223係鍺化矽且通道奈米線1241、1242、和1243係矽，濕蝕刻可能包括，但不限於羧酸/硝酸/氫氟酸的溶液、和檸檬酸/硝酸/氫氟酸的溶液。
如第15圖所示，可能沉積間隔物材料以形成第一間隔物192和第二間隔物194，其填充在通道奈米線1241、1242、和1243(參見第14圖)之間的間隔以形成奈米線裝置100。用以形成第一間隔物192和第二間隔物194的間隔物材料可能是任何適當的介電材料，例如二氧化 矽、氧氮化矽、或氮化矽。在一實施例中，間隔物材料係低k介電材料，即，具有小於3.6的介電常數。
在如第16圖所示之另一實施例中，可能移除第一間隔物192和第二間隔物194的一部分以定義在通道奈米線1241、1242、和1243之間的內部間隔物1901、1902、和1903。如第17圖所示，可能接著沉積不同於內部間隔物1901、1902、和1903的介電材料以形成圍繞內部間隔物1901、1902、和1903、和通道奈米線1201、1202、和1203(參見第16圖)且位於閘極電極140與其各別源極結構160或汲極結構170之間的第一外部間隔物196和第二外部間隔物198。
第18圖係根據本說明之一實施例之製造奈米線電晶體結構的程序200之流程圖。如方塊202所述，可能形成微電子基板。包含至少一犧牲材料層和至少一通道材料層的堆疊層可能形成在微電子基板上，如方塊204所述。如方塊206所述，可能從堆疊層形成至少一鰭片結構，如方塊208所述。如方塊208所述，可能跨鰭片結構地形成至少兩個犧牲間隔物。犧牲閘極材料可能形成在至少兩個犧牲間隔物之間，如方塊210所述。如方塊212所述，可能移除在犧牲閘極材料和間隔物外部之鰭片結構的一部分以暴露部分的微電子基板。可能在鰭片結構之相對端上的微電子基板部分上形成源極結構和汲極結構，如方塊214所述。如方塊216所述，可能在源極結構和汲極結構上方形成層間介電層。可能從間隔物之間移除犧牲閘極 材料，如方塊218所述。如方塊220所述，可能從通道材料層之間選擇性地移除犧牲材料層以形成至少一通道奈米線。如方塊222所述，可能形成閘極介電材料以圍繞在間隔物之間的通道奈米線。閘極電極材料可能形成在閘極介電材料上，如方塊224所述。如方塊226所述，可能移除犧牲間隔物。可能選擇性地移除在通道奈米線之間的犧牲材料層，如方塊228所述。如方塊230所述，可能沉積介電材料以形成至少一間隔物，其中介電材料係設置於通道奈米線之間。
第19圖繪示依照本說明之一個實作的計算裝置300。計算裝置300容納主機板302。主機板302可能包括一些元件，包括但不限於處理器304和至少一個通訊晶片306。處理器304係實體且電性耦接至主機板302。在一些實作中，至少一個通訊晶片306也是實體且電性耦接至主機板302。在其他實作中，通訊晶片306是處理器304的一部分。
依據其應用，計算裝置300可能包括可能或可能不是實體且電性耦接至主機板302的其他元件。這些其他元件包括，但不限於揮發性記憶體(例如，DRAM)、非揮發性記憶體(例如，ROM)、快閃記憶體、圖形處理器、數位信號處理器、密碼處理器、晶片組、天線、顯示器、觸控顯示器、觸控控制器、電池、音頻編解碼器、視頻編解碼器、功率放大器、全球定位系統(GPS)裝置、羅盤、加速計、陀螺儀、揚聲器、照相機、及大容量儲存裝 置(如硬碟機、光碟(CD)、數位化多功能光碟(DVD)等等)。
通訊晶片306啟動無線通訊來傳輸資料至計算裝置300且從計算裝置300傳輸資料。「無線」之詞及其衍生詞可能用以說明可能藉由使用透過非固態媒體之調變的電磁輻射來傳遞資料之電路、裝置、系統、方法、技術、通訊通道等。此詞並不意味著相關裝置不包含任何線路，雖然在一些實施例中它們可能並非如此。通訊晶片306可能實作一些無線標準或協定，包括但不限於WiFi(IEEE 802.11家族)、WiMAX(IEEE 802.16家族)、IEEE 802.20、長期演進(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍芽、其衍生物之任一者、以及指定為3G、4G、5G以上的任何其他無線協定。計算裝置300可能包括複數個通訊晶片306。例如，第一通訊晶片306可能專用於如WiFi和藍芽之較短範圍的無線通訊，且第二通訊晶片306可能專用於如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等之較長範圍的無線通訊。
計算裝置300的處理器304包括封裝在處理器304內的積體電路晶粒。在本說明之一些實作中，處理器的積體電路晶粒包括一或更多裝置，如依照本說明之實作建立之奈米線電晶體。「處理器」之詞可能指任何裝置或部分之處理來自暫存器及/或記憶體的電子資料以將電 子資料轉換成可能儲存在暫存器及/或記憶體中之其他電子資料的裝置。
通訊晶片306也包括封裝在通訊晶片306內的積體電路晶粒。依照本說明之另一實作，通訊晶片的積體電路晶粒包括一或更多裝置，如依照本說明之實作建立之奈米線電晶體。
在其他實作中，容納在計算裝置300內的另一元件可能包含積體電路晶粒，其包括一或更多裝置，如依照本說明之實作建立之奈米線電晶體。
在各種實作中，計算裝置300可能是膝上型電腦、筆記型電腦、小筆電、纖薄筆記型電腦、智慧型手機、平板電腦、個人數位助理(PDA)、纖薄型行動PC、行動電話、桌上型電腦、伺服器、印表機、掃描機、監視器、機上盒、娛樂控制單元、數位相機、可攜式音樂播放器、或數位攝影機。在其他實作中，計算裝置300可能是任何其他處理資料的電子裝置。
了解本說明之主題不一定限於第1-19圖所示之特定應用。主題可能適用於其他微電子裝置和組件應用、以及如本領域之那些技術者將了解之任何適當的電晶體應用。
下面的實例關於其他實施例，其中實例1係一種形成一奈米線電晶體的方法，包含：提供一微電子結構，具有：一鰭片結構，具有複數個通道奈米線、設置於一基板上；一閘極電極，鄰接鰭片結構的一部分，其中閘 極電極圍繞在鰭片結構中的複數個通道奈米線之各者；一犧牲間隔物，鄰接閘極電極的一端，其中間隔物鄰接鰭片結構的一部分，其包含被犧牲材料分離的通道奈米線；及一源極和一汲極之其一者，鄰接鰭片結構的一端和犧牲間隔物；移除犧牲間隔物；從通道奈米線之間移除犧牲材料；及沉積一介電材料以形成一間隔物，其中介電材料係設置於通道奈米線之間。
在實例2中，實例1之主題能可選地包括沉積介電材料以形成間隔物，包含沉積一低k介電材料以形成間隔物。
在實例3中，實例1至實例2之任一者之主題能可選地包括犧牲間隔物，包含二氧化矽、氮化矽、及氧氮化矽之至少一者。
在實例4中，實例1至實例3之任一者之主題能可選地包括移除間隔物的一部分以定義在通道奈米線之間的內部間隔物；及沉積不同於內部間隔物之介電材料的另一介電材料，以形成在閘極電極與一源極和一汲極之其一者之間的一外部間隔物，其中外部間隔物圍繞內部間隔物和通道奈米線。
在實例5中，實例1至實例4之任一者之主題能可選地包括包含矽的犧牲材料且其中通道奈米線包含鍺化矽。
在實例6中，實例1至實例4之任一者之主題能可選地包括包含鍺化矽層的犧牲材料且其中通道奈米 線包含矽。
下面的實例關於其他實施例，其中實例7係一種形成一奈米線電晶體的方法，包含：提供一微電子結構，具有：一鰭片結構，具有複數個通道奈米線、設置於一基板上；一閘極電極，鄰接鰭片結構的一部分，其中閘極電極圍繞在鰭片結構中的複數個通道奈米線之各者；一第一犧牲間隔物，鄰接閘極電極的一端，第一間隔物鄰接鰭片結構的一部分，其包含被犧牲材料分離的通道奈米線；一第二犧牲間隔物，鄰接閘極電極的另一端，第二犧牲間隔物鄰接鰭片結構的另一部分，其包含被犧牲材料分離的複數個通道奈米線；一源極，鄰接鰭片結構的一端和第一犧牲間隔物；及一汲極，鄰接鰭片結構的一相對端和第二犧牲間隔物；移除第一犧牲間隔物和第二犧牲間隔物；從通道奈米線之間移除犧牲材料；及沉積一介電材料以形成一第一間隔物和一第二間隔物，其中介電材料係設置於通道奈米線之間。
在實例8中，實例7之主題能可選地包括沉積介電材料以形成第一間隔物和第二間隔物，包含沉積一低k介電材料以形成第一間隔物和第二間隔物。
在實例9中，實例7至實例8之任一者之主題能可選地包括第一犧牲間隔物和第二犧牲間隔物之至少一者，包含二氧化矽、氮化矽、及氧氮化矽之至少一者。
在實例10中，實例7至實例9之任一者之主題能可選地包括移除第一間隔物的一部分和第二間隔物的 一部分以定義在通道奈米線之間的內部間隔物；及沉積不同於內部間隔物之介電材料的一介電材料，以形成在閘極電極與源極之間的一第一外部間隔物、及在閘極電極之間的一第二外部間隔物，其中第一外部間隔物和第二外部間隔物圍繞內部間隔物和通道奈米線。
在實例11中，實例7至實例10之任一者之主題能可選地包括包含矽的犧牲材料且其中通道奈米線包含鍺化矽。
在實例12中，實例7至實例10之任一者之主題能可選地包括包含鍺化矽層的犧牲材料且其中通道奈米線包含矽。
下面的實例關於其他實施例，其中實例13係一種形成一奈米線電晶體的方法，包含：形成一微電子基板；在微電子基板上形成包含至少一犧牲材料層和至少一通道材料層的一堆疊層；形成從層狀堆疊形成的至少一鰭片結構；跨鰭片結構地形成至少兩個犧牲間隔物；在至少兩個犧牲間隔物之間形成一犧牲閘極材料；移除在犧牲閘極材料和犧牲間隔物外部之鰭片結構的一部分以暴露部分的微電子基板；在鰭片結構之相對端上的微電子基板部分上形成一源極結構和一汲極結構；在源極結構和汲極結構上方形成一層間介電層；從犧牲間隔物之間移除犧牲閘極材料；從通道材料層之間選擇性地移除犧牲材料層以形成至少一通道奈米線；形成一閘極介電材料以圍繞在至少兩個犧牲間隔物之間的通道奈米線；在閘極介電材料上形成 一閘極電極；移除至少兩個犧牲間隔物；選擇性地移除在通道奈米線之間的犧牲材料層；及沉積一介電材料以形成至少一間隔物，其中介電材料係設置於通道奈米線之間。
在實例14中，實例13之主題能可選地包括沉積介電材料以形成至少一間隔物，包含沉積一低k介電材料以形成至少一間隔物。
在實例15中，實例13至實例14之任一者之主題能可選地包括至少兩個犧牲間隔物之至少一者，包含二氧化矽、氮化矽、及氧氮化矽之至少一者。
在實例16中，實例13至實例15之任一者之主題能可選地包括移除至少一間隔物的一部分以定義在通道奈米線之間的內部間隔物；及沉積不同於內部間隔物之介電材料的另一介電材料，以形成圍繞內部間隔物和通道奈米線的至少一外部間隔物。
在實例17中，實例13至實例16之任一者之主題能可選地包括在微電子基板上形成具有至少一犧牲材料層和至少一通道材料層的一堆疊層，包含在微電子基板上形成包含至少一矽犧牲材料層和至少一鍺化矽通道層的堆疊層。
在實例18中，實例13至實例16之任一者之主題能可選地包括在微電子基板上形成具有至少一犧牲材料層和至少一通道材料層的一堆疊層，包含在微電子基板上形成包含至少一鍺化矽犧牲層和至少一矽通道層的堆疊層。
因此，已詳細說明本說明之實施例，了解由所附之申請專利範圍定義的本說明並不限於上述說明所提出之特定細節，因為其許多明顯的變化在不脫離其精神和範圍下係可能的。

Claims (18)

  1. 一種形成一奈米線電晶體的方法，包含：提供一微電子結構，具有：一鰭片結構，具有複數個通道奈米線，該鰭片結構設置於一基板上；一閘極結構，鄰接該鰭片結構的一部分，其中該閘極結構包含一閘極介電質，圍繞在該鰭片結構中的該複數個通道奈米線之各者、及鄰接該閘極介電質的一閘極電極；一犧牲間隔物，鄰接該閘極電極的一端，其中該間隔物鄰接該鰭片結構的一部分，其包含被犧牲材料分離的該些通道奈米線；及一源極和一汲極之其一者，鄰接該鰭片結構的一端和該犧牲間隔物；移除該犧牲間隔物；從該些通道奈米線之間移除該犧牲材料；及沉積一介電材料以形成一間隔物，其中該介電材料係設置於該些通道奈米線之間。
  2. 如申請專利範圍第1項所述之方法，其中沉積該介電材料以形成該間隔物包含沉積一低k介電材料以形成該間隔物。
  3. 如申請專利範圍第1項所述之方法，其中該犧牲間隔物包含二氧化矽、氮化矽、及氧氮化矽之至少一者。
  4. 如申請專利範圍第1項所述之方法，更包括： 移除該間隔物的一部分以定義在該些通道奈米線之間的內部間隔物；及沉積不同於該些內部間隔物之介電材料的另一介電材料，以形成在該閘極電極與一源極和一汲極之該其一者之間的一外部間隔物，其中該外部間隔物圍繞該些內部間隔物和該些通道奈米線。
  5. 如申請專利範圍第1項所述之方法，其中該犧牲材料包含矽且其中該些通道奈米線包含鍺化矽。
  6. 如申請專利範圍第1項所述之方法，其中該犧牲材料包含鍺化矽層且其中該些通道奈米線包含矽。
  7. 一種形成一奈米線電晶體的方法，包含：提供一微電子結構，具有：一鰭片結構，具有複數個通道奈米線，該鰭片結構設置於一基板上；一閘極結構，鄰接該鰭片結構的一部分，其中該閘極結構包含一閘極介電質，圍繞在該鰭片結構中的該複數個通道奈米線之各者、及鄰接該閘極介電質的一閘極電極；一第一犧牲間隔物，鄰接該閘極電極的一端，該第一間隔物鄰接該鰭片結構的一部分，其包含被犧牲材料分離的該些通道奈米線；一第二犧牲間隔物，鄰接該閘極電極的另一端，該第二犧牲間隔物鄰接該鰭片結構的另一部分，其包含被犧牲材料分離的該複數個通道奈米線； 一源極，鄰接該鰭片結構的一端和該第一犧牲間隔物；及一汲極，鄰接該鰭片結構的一相對端和該第二犧牲間隔物；移除該第一犧牲間隔物和該第二犧牲間隔物；從該些通道奈米線之間移除該犧牲材料；及沉積一介電材料以形成一第一間隔物和一第二間隔物，其中該介電材料係設置於該些通道奈米線之間。
  8. 如申請專利範圍第7項所述之方法，其中沉積該介電材料以形成該第一間隔物和該第二間隔物包含沉積一低k介電材料以形成該第一間隔物和該第二間隔物。
  9. 如申請專利範圍第7項所述之方法，其中該第一犧牲間隔物和該第二犧牲間隔物之至少一者包含二氧化矽、氮化矽、及氧氮化矽之至少一者。
  10. 如申請專利範圍第7項所述之方法，更包括：移除該第一間隔物的一部分和該第二間隔物的一部分以定義在該些通道奈米線之間的內部間隔物；及沉積不同於該些內部間隔物之介電材料的一介電材料，以形成在該閘極電極與該源極之間的一第一外部間隔物、及在該閘極電極之間的一第二外部間隔物，其中該第一外部間隔物和該第二外部間隔物圍繞該些內部間隔物和該些通道奈米線。
  11. 如申請專利範圍第7項所述之方法，其中該犧牲材料包含矽且其中該些通道奈米線包含鍺化矽。
  12. 如申請專利範圍第7項所述之方法，其中該犧牲材料包含鍺化矽層且其中該些通道奈米線包含矽。
  13. 一種形成一奈米線電晶體的方法，包含：形成一微電子基板；在該微電子基板上形成包含至少一犧牲材料層和至少一通道材料層的一堆疊層；形成從該堆疊層形成的至少一鰭片結構；跨該鰭片結構地形成至少兩個犧牲間隔物；在該至少兩個犧牲間隔物之間形成一犧牲閘極材料；移除在該犧牲閘極材料和該些犧牲間隔物外部之該鰭片結構的一部分以暴露部分的該微電子基板；在該鰭片結構之相對端上的該些微電子基板部分上形成一源極結構和一汲極結構；在該源極結構和該汲極結構上方形成一層間介電層；從該些犧牲間隔物之間移除該犧牲閘極材料；從該些通道材料層之間選擇性地移除該些犧牲材料層以形成至少一通道奈米線；形成一閘極介電材料以圍繞在該至少兩個犧牲間隔物之間的該通道奈米線；在該閘極介電材料上形成一閘極電極；移除該至少兩個犧牲間隔物；選擇性地移除在該些通道奈米線之間的該些犧牲材料層；及沉積一介電材料以形成至少一間隔物，其中該介電材 料係設置於該些通道奈米線之間。
  14. 如申請專利範圍第13項所述之方法，其中沉積該介電材料以形成該至少一間隔物包含沉積一低k介電材料以形成該至少一間隔物。
  15. 如申請專利範圍第13項所述之方法，其中該至少兩個犧牲間隔物之至少一者包含二氧化矽、氮化矽、及氧氮化矽之至少一者。
  16. 如申請專利範圍第13項所述之方法，更包括：移除該至少一間隔物的一部分以定義在該些通道奈米線之間的內部間隔物；及沉積不同於該些內部間隔物之介電材料的另一介電材料，以形成圍繞該些內部間隔物和該些通道奈米線的至少一外部間隔物。
  17. 如申請專利範圍第13項所述之方法，其中在該微電子基板上形成包含至少一犧牲材料層和至少一通道材料層的一堆疊層包含在該微電子基板上形成包含至少一矽犧牲材料層和至少一鍺化矽通道層的該堆疊層。
  18. 如申請專利範圍第13項所述之方法，其中在該微電子基板上形成包含至少一犧牲材料層和至少一通道材料層的一堆疊層包含在該微電子基板上形成包含至少一鍺化矽犧牲層和至少一矽通道層的該堆疊層。
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US20160211322A1 (en) 2016-07-21
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US20170047452A1 (en) 2017-02-16
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