CN107204311A - 纳米线半导体器件及其制造方法 - Google Patents

纳米线半导体器件及其制造方法 Download PDF

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Publication number
CN107204311A
CN107204311A CN201610150107.3A CN201610150107A CN107204311A CN 107204311 A CN107204311 A CN 107204311A CN 201610150107 A CN201610150107 A CN 201610150107A CN 107204311 A CN107204311 A CN 107204311A
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China
Prior art keywords
nano wire
substrate
semiconductor device
active areas
nanowire semiconductor
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CN201610150107.3A
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Inventor
肖德元
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Zing Semiconductor Corp
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Zing Semiconductor Corp
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Priority to CN201610150107.3A priority Critical patent/CN107204311A/zh
Priority to US15/157,421 priority patent/US9721846B1/en
Priority to TW105127931A priority patent/TW201735363A/zh
Priority to US15/491,989 priority patent/US20170271211A1/en
Publication of CN107204311A publication Critical patent/CN107204311A/zh
Pending legal-status Critical Current

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    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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Abstract

在本发明提供的纳米线半导体器件及其制造方法中，通过在PMOS有源区和NMOS有源区上分别形成高空穴迁移率的第一纳米线和高电子迁移率的第二纳米线，从而提高纳米线半导体器件的性能。

Description

纳米线半导体器件及其制造方法
技术领域
本发明涉及半导体技术领域，特别涉及一种纳米线半导体器件及其制造方法。
背景技术
在过去的四十年里，微电子工业发展一直遵循着摩尔定律。为了跟上摩尔定律的脚步，人们不断地缩小半导体器件的特征尺寸。当前，半导体器件的物理尺寸已到极限，通过缩小物理尺寸来提高性能已经非常困难。
为此，业内设计开发了各种新型的半导体器件以适应市场需求，例如纳米线场效应晶体管(Nanowire Field-Effect Transistor，简称NWFET)。NWFET的结构中具有一维纳米线沟道，由于量子限制效应，沟道内载流子远离表面分布，故载流子输运受表面散射和沟道横向电场影响小，可以获得较高的迁移率。另一方面，NWFET具有较小尺寸的沟道并且通常采用围栅结构，栅极可以从多个方向对所述沟道进行调制，从而增强栅极的调控能力，改善阈值特性。因此NWFET可以很好地抑制短沟道效应，使场效应晶体管的尺寸得以进一步缩小。同时，由于NWFET利用自身的细沟道和围栅结构改善了栅极调控能力，因此缓解了减薄栅介质厚度的需求，进而减小栅极的漏电流。基于以上优势，NWFET已经越来越受到科研人员的关注。
然而，在实际的制造和使用过程中发现，现有的纳米线半导体器件的性能比较差，还不能满足市场要求。如何进一步提升纳米线半导体器件的性能仍是本领域技术人员亟待解决的技术问题。
发明内容
本发明的目的在于提供一种纳米线半导体器件及其制造方法，以解决现有技术中纳米线半导体器件的性能差的问题。
为解决上述问题，本发明提供一种纳米线半导体器件的制造方法，所述纳米线半导体器件的制造方法包括：
提供一基底，所述基底包括NMOS有源区和PMOS有源区；
进行第一次选择性外延生长工艺，以在所述NMOS有源区中形成多边形结构的第一纳米线；
进行第二次选择性外延生长工艺，以在所述PMOS有源区中形成多边形结构的第二纳米线；
通过刻蚀工艺去除部分基底，使得所述第一纳米线悬空于所述基底的上方；
对所述第一纳米线进行氧化退火处理；以及
在所述基底、第一纳米线和第二纳米线上依次形成栅介质层和栅电极层。
可选的，在所述的纳米线半导体器件的制造方法中，在进行第一次选择性外延生长工艺，以在所述NMOS有源区中形成多边形结构的第一纳米线之前，提供一基底之后，还包括：在所述基底上形成隔离结构。
可选的，在所述的纳米线半导体器件的制造方法中，进行第一次选择性外延生长工艺，以在所述NMOS有源区中形成多边形结构的第一纳米线的过程包括：
在所述基底和隔离结构上形成图形化的第一硬掩膜层，所述第一硬掩膜层中具有第一通孔，所述第一通孔的底部暴露出部分NMOS有源区的基底；
通过第一次选择性外延生长工艺在所述第一通孔暴露出的基底上形成多边形结构的第一纳米线；以及
去除所述第一硬掩膜层。
可选的，在所述的纳米线半导体器件的制造方法中，进行第二次选择性外延生长工艺，以在所述PMOS有源区中形成多边形结构的第二纳米线的过程包括：
在所述基底、隔离结构以及第一纳米线上形成图形化的第二硬掩膜层，所述第二硬掩膜层中具有第二通孔，所述第二通孔的底部暴露出部分PMOS有源区的基底；
对所述第二通孔暴露出的基底进行湿法刻蚀以形成凹陷；
通过第二次选择性外延生长工艺在所述凹陷上形成多边形结构的第二纳米线；以及
去除所述第二硬掩膜层。
可选的，在所述的纳米线半导体器件的制造方法中，对所述第一纳米线进行氧化退火处理的过程包括：
对所述第一纳米线进行热氧化；
通过湿法刻蚀工艺去除所述第一纳米线表面的氧化层；以及
在氢气环境中对所述第一纳米线的进行高温退火。
可选的，在所述的纳米线半导体器件的制造方法中，所述第一纳米线和第二纳米线采用的材料均为III-V族半导体材料。
可选的，在所述的纳米线半导体器件的制造方法中，所述第一纳米线采用的材料为锗，所述第二纳米线采用的材料为铟镓砷。
本发明还提供一种纳米线半导体器件，所述纳米线半导体器件包括：基底，所述基底包括PMOS有源区和NMOS有源区；形成于所述PMOS有源区上的第一纳米线；形成于所述NMOS有源区上的第二纳米线；完全包围所述第一纳米线并部分包围所述第二纳米线的栅介质层和栅电极层。
可选的，在所述的纳米线半导体器件中，所述第一纳米线的长度范围在2纳米到50纳米之间，所述第一纳米线的直径范围在2纳米到5纳米之间。
可选的，在所述的纳米线半导体器件中，所述第一纳米线为锗纳米线，所述锗纳米线的截面形状为圆形、椭圆形或棱形。
所述第二纳米线为铟镓砷纳米线，所述第二纳米线的截面形状为多边形。
可选的，在所述的纳米线半导体器件中，所述第一纳米线中锗的含量范围在65％到100％之间。
可选的，在所述的纳米线半导体器件中，所述栅介质层为高k介质层，所述栅介质层采用的材料为Al2O3或TiSiOx；
所述栅电极层为金属电极层，所述栅电极层采用的材料为TiN、NiAu或CrAu中的任意一种。
综上所述，在本发明提供的纳米线半导体器件及其制造方法中，通过在PMOS有源区和NMOS有源区上分别形成高空穴迁移率的第一纳米线和高电子迁移率的第二纳米线，从而提高纳米线半导体器件的性能。
附图说明
图1是本发明实施例的纳米线半导体器件的制作方法的流程图；
图2至图12是本发明实施例的纳米线半导体器件的制作过程的结构示意图。
具体实施方式
以下结合附图和具体实施例对本发明提出的纳米线半导体器件及其制造方法作进一步详细说明。根据下面说明和权利要求书，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
请参考图1，其为本发明实施例的纳米线半导体器件的制作方法的流程图。如图1所示，所述纳米线半导体器件的制造方法包括：
S10：提供一基底，所述基底包括NMOS有源区和PMOS有源区；
S11：进行第一次选择性外延生长工艺，以在所述NMOS有源区上形成多边形结构的第一纳米线；
S12：进行第二次选择性外延生长工艺，以在所述PMOS有源区上形成多边形结构的第二纳米线；
S13：通过刻蚀工艺去除部分基底，使得所述第一纳米线悬空于所述基底的上方；
S14：对所述第一纳米线进行氧化退火处理；
S15：在所述基底、第一纳米线和第二纳米线上依次形成栅介质层和栅电极层280。
图2～12为本发明实施例的纳米线半导体器件的制作过程的结构示意图，请参考图1所示，并结合图2～图12，详细说明本发明提出所述纳米线半导体器件的制作方法：
首先，如图2所示，提供一基底210，所述基底210包括图形化的NMOS有源区210b和PMOS有源区210a。
接着，如图3所示，在所述基底210上形成氧化物层并采用化学机械研磨去除多余的氧化物层，以形成隔离结构220，所述隔离结构220的顶部与所述基底210的顶部大致齐平。
然后，进行第一次选择性外延生长工艺，以在所述PMOS有源区210a上形成多边形结构的第一纳米线240。形成第一纳米线240的具体过程包括：
步骤一：在所述基底210和隔离结构220上形成图形化的第一硬掩膜层230，所述第一硬掩膜层230中具有第一通孔230a，所述第一通孔230a的底部暴露出部分PMOS有源区210a的基底210；
步骤二：通过第一次选择性外延生长工艺在所述第一通孔230a暴露出的基底210上形成多边形结构的第一纳米线240；
步骤三：去除所述第一硬掩膜层230。
如图4所示，执行步骤一之后，在所述基底210和隔离结构220的上面形成有图形化的第一硬掩膜层230，位于所述PMOS有源区210a的部分第一硬掩膜层230被刻蚀掉了，形成了第一通孔230a，所述第一通孔230a的底部暴露出所述基底210。
如图5所示，执行步骤二之后，形成了多边形结构的第一纳米线240，所述第一纳米线240与所述PMOS有源区210a的基底210相接触。
之后，进行第二次选择性外延生长工艺，以在所述NMOS有源区210b上形成多边形结构的第二纳米线260。形成第二纳米线260的具体过程包括：
步骤一：在所述基底210、隔离结构220以及第一纳米线240的上面形成图形化的第二硬掩膜层250，所述第二硬掩膜层250中具有第二通孔250a，所述第二通孔250a的底部暴露出部分NMOS有源区210b的基底210；
步骤二：对所述第二通孔250a暴露出的基底210进行湿法刻蚀以形成凹陷212；
步骤三：通过第二次选择性外延生长工艺在所述凹陷212上形成多边形结构的第二纳米线260；
步骤四：去除所述第二硬掩膜层250。
如图6所示，执行步骤一之后，在所述基底210、隔离结构220以及第一纳米线240的上面形成了图形化的第二硬掩膜层250，位于所述NMOS有源区210b的部分第二硬掩膜层250被刻蚀掉了，形成了第二通孔250a，所述第二通孔250a的底部暴露出所述基底210。
如图7所示，对所述第二通孔250a暴露出的基底210进行刻蚀之后，所述基底210中形成了凹陷212。优选的，所述凹陷212的截面形状为V型，所述刻蚀工艺采用的刻蚀液为四甲基氢氧化铵(TMAH)或KOH。
如图8所示，执行步骤三之后，在所述V型凹陷212上形成了多边形结构的第二纳米线260，所述第二纳米线260所述第二纳米线260与所述NMOS有源区210b的基底210相接触。
之后，通过第二次刻蚀工艺去除部分隔离结构220和基底210，使得所述第一纳米线240悬空于所述基底210的上方。所述第二次刻蚀工艺采用的刻蚀液为四甲基氢氧化铵(TMAH)。
如图9所示，第二次刻蚀工艺之后，所述第一纳米线240悬空于所述基底210的上方，即所述第一纳米线240与所述基底210不接触。
此后，对所述第一纳米线240进行氧化退火处理。对所述第一纳米线240进行氧化退火处理的具体过程包括：
步骤一：对所述第一纳米线240进行热氧化；
步骤二：通过湿法刻蚀工艺去除所述第一纳米线240表面的氧化层；
步骤三：在氢气环境中，对所述第一纳米线240的进行高温退火。
如图10所示，在氧化退火处理过程中，锗硅进行氧化浓缩，使得所述第一纳米线240的锗浓缩形成锗纳米线，氧化和湿法刻蚀使得所述锗纳米线具有更光滑的表面，氧化退火处理之后，所述第一纳米线240(即锗纳米线)的截面形状由多边形变为圆形、椭圆形或棱形。
最后，在所述基底210、第一纳米线240和第二纳米线260上依次形成栅介质层270和栅电极层280。
如图11所示，在所述基底210、隔离结构220、第一纳米线240以及第二纳米线260上形成栅介质层270之后，所述栅介质层270覆盖在所述基底210、隔离结构220、第一纳米线240以及第二纳米线260的表面上。
如图12所示，在所述栅介质层270上形成栅电极层280之后，所述栅电极层280完全包围所述第一纳米线240，同时包围所述第二纳米线260大部分的表面。
所述栅介质层270的形成工艺可以是原子层沉积(ALD)工艺、金属有机化合物化学气相沉积(MOCVD)工艺或化学气相沉积(CVD)工艺或其他现有的工艺技术。所述栅电极层280的形成工艺可以是原子层沉积(ALD)工艺、金属有机化合物化学气相沉积(MOCVD)工艺或分子束外延(MBE)工艺或其他现有的工艺技术。
至此，形成了所述纳米线半导体器件200。所述纳米线半导体器件200的PMOS有源区210a上形成有锗纳米线，NMOS有源区210b上形成有铟镓砷纳米线。由于，所述锗纳米线(Ge)具有较高的空穴迁移率，所述铟镓砷纳米线(InGaAs)具有较高的电子迁移率，因此所述纳米线半导体器件200的性能得以提高。
对纳米线半导体器件而言，纳米线的制作是其关键工艺，直接关系到纳米线半导体器件的性能。现有的锗纳米线的制作过程通常包括：首先，形成具有硅核的纳米线；接着，通过氧化退火处理，使锗向中心聚集以形成锗纳米线。然而，由于内核中硅的含量较高，因此提高锗纳米线中锗含量的工艺难度较大。所形成的纳米线半导体器件中，纳米线的锗含量较低，对半导体器件的性能造成了不利影响。
本实施例中，锗纳米线在制作过程中不需要先形成具有硅核的纳米线，直接利用锗进行外延生长，后续氧化退火处理后所形成的锗纳米线具有较高的锗含量。
试验证明，所述纳米线半导体器件200中第一纳米线240的锗含量在65％到100％之间，明显高于现有的锗纳米线的锗含量(通常在50％以下)。由此可见，采用所述纳米线半导体器件的制造方法制作的半导体器件，能够有效地提升器件性能。
相应的，本发明还提供一种纳米线半导体器件。请参考图12，其为本发明实施例的纳米线半导体器件的结构示意图。如图12所示，所述纳米线半导体器件包括：基底210，所述基底210包括PMOS有源区210a和NMOS有源区210b；：形成于所述PMOS有源区210a上的第一纳米线240；形成于所述NMOS有源区210b上的第二纳米线260；完全包围所述第一纳米线240并部分包围所述第二纳米线260的栅介质层270和栅电极层280。
具体的，所述第一纳米线240和第二纳米线260分别形成于所述基底210的PMOS有源区210a和NMOS有源区210b，所述栅介质层270形成于所述基底210、第一纳米线240和第二纳米线260上，所述栅电极层280形成于所述栅介质层270上。所述第一纳米线240被所述栅介质层270与栅电极层280完全包围，所述第二纳米线260中位于隔离结构220上方的区域也被所述栅介质层270与栅电极层280包围。
其中，所述栅介质层270为高k介质层。例如，所述栅介电层270的材料为Al2O3或TiSiOx。采用高k材料制作栅介质层270，能够提高纳米线半导体器件的电学性能。所述栅电极层280为金属电极层，所述栅电极层280采用的材料为TiN、NiAu或CrAu中的一种。
所述第一纳米线240和第二纳米线260采用的材料为III-V族半导体材料，所述III-V族半导体材料包括硅、硅锗、碳化硅或锗。优选的，所述第一纳米线240采用的材料为锗(Ge)，所述第二纳米线260采用的材料为铟镓砷(InGaAs)。
所述第一纳米线240的截面形状为圆形，所述第二纳米线260的截面形状为多边形。优选的，所述第二纳米线260的截面形状为边长数大于或等于五的多边形。
优选的，所述第一纳米线240的长度范围在2纳米到50纳米之间，所述第一纳米线240的直径范围在2纳米到5纳米之间。
综上可见，在本发明实施例提供的纳米线半导体器件及其制造方法中，通过在PMOS有源区和NMOS有源区上分别形成高空穴迁移率的第一纳米线和高电子迁移率的第二纳米线，从而提高纳米线半导体器件的性能。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。

Claims (12)

1.一种纳米线半导体器件的制造方法，其特征在于，包括：
提供一基底，所述基底包括NMOS有源区和PMOS有源区；
进行第一次选择性外延生长工艺，以在所述NMOS有源区中形成多边形结构的第一纳米线；
进行第二次选择性外延生长工艺，以在所述PMOS有源区中形成多边形结构的第二纳米线；
通过刻蚀工艺去除部分基底，使得所述第一纳米线悬空于所述基底的上方；
对所述第一纳米线进行氧化退火处理；以及
在所述基底、第一纳米线和第二纳米线上依次形成栅介质层和栅电极层。
2.如权利要求1所述的纳米线半导体器件的制造方法，其特征在于，在进行第一次选择性外延生长工艺，以在所述NMOS有源区中形成多边形结构的第一纳米线之前，提供一基底之后，还包括：在所述基底上形成隔离结构。
3.如权利要求2所述的纳米线半导体器件的制造方法，其特征在于，进行第一次选择性外延生长工艺，以在所述NMOS有源区中形成多边形结构的第一纳米线的过程包括：
在所述基底和隔离结构上形成图形化的第一硬掩膜层，所述第一硬掩膜层中具有第一通孔，所述第一通孔的底部暴露出部分NMOS有源区的基底；
通过第一次选择性外延生长工艺在所述第一通孔暴露出的基底上形成多边形结构的第一纳米线；以及
去除所述第一硬掩膜层。
4.如权利要求2所述的纳米线半导体器件的制造方法，其特征在于，进行第二次选择性外延生长工艺，以在所述PMOS有源区中形成多边形结构的第二纳米线的过程包括：
在所述基底、隔离结构以及第一纳米线上形成图形化的第二硬掩膜层，所述第二硬掩膜层中具有第二通孔，所述第二通孔的底部暴露出部分PMOS有源区的基底；
对所述第二通孔暴露出的基底进行湿法刻蚀以形成凹陷；
通过第二次选择性外延生长工艺在所述凹陷上形成多边形结构的第二纳米线；以及
去除所述第二硬掩膜层。
5.如权利要求1所述的纳米线半导体器件的制造方法，其特征在于，对所述第一纳米线进行氧化退火处理的过程包括：
对所述第一纳米线进行热氧化；
通过湿法刻蚀工艺去除所述第一纳米线表面的氧化层；以及
在氢气环境中对所述第一纳米线的进行高温退火。
6.如权利要求1所述的纳米线半导体器件的制造方法，其特征在于，所述第一纳米线和第二纳米线采用的材料均为III-V族半导体材料。
7.如权利要求6所述的纳米线半导体器件的制造方法，其特征在于，所述第一纳米线采用的材料为锗，所述第二纳米线采用的材料为铟镓砷。
8.一种纳米线半导体器件，其特征在于，包括：基底，所述基底包括PMOS有源区和NMOS有源区；形成于所述PMOS有源区上的第一纳米线；形成于所述NMOS有源区上的第二纳米线；完全包围所述第一纳米线并部分包围所述第二纳米线的栅介质层和栅电极层。
9.如权利要求8所述的纳米线半导体器件，其特征在于，所述第一纳米线的长度范围在2纳米到50纳米之间，所述第一纳米线的直径范围在2纳米到5纳米之间。
10.如权利要求8所述的纳米线半导体器件，其特征在于，所述第一纳米线为锗纳米线，所述锗纳米线的截面形状为圆形、椭圆形或棱形；
所述第二纳米线为铟镓砷纳米线，所述第二纳米线的截面形状为多边形。
11.如权利要求10所述的纳米线半导体器件，其特征在于，所述第一纳米线中锗的含量范围在65％到100％之间。
12.如权利要求8所述的纳米线半导体器件，其特征在于，所述栅介质层为高k介质层，所述栅介质层采用的材料为Al2O3或TiSiOx；
所述栅电极层为金属电极层，所述栅电极层采用的材料为TiN、NiAu或CrAu中的任意一种。
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