CN1117205A - 半导体器件的布线结构及其制造方法 - Google Patents
半导体器件的布线结构及其制造方法 Download PDFInfo
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Abstract
一种半导体器件的布线结构填埋一个开口(如接触孔或通孔)。该布线结构包括半导体衬底、在衬底上形成的绝缘层(该绝缘层中形成有开口)、在该开口内侧壁上形成的不带由难熔金属或难熔金属化合物组成的晶粒边界的平坦表面的扩散阻挡膜,以及在该扩散阻挡膜上形成的金属层。该扩散阻挡膜侧壁上的金属层由均匀和连续形成的、具有良好台阶覆盖范围的铝膜组成。因此,有效地填埋具有高纵横比的接触孔和提高器件的可靠性。
Description
本发明涉及用于制造一种半导体器件的方法,更详细地说,涉及用于填埋诸如接触孔或通孔之类的开口的一种半导体器件的布线结构以及用于制造该结构的方法。
一般来说,在半导体器件的制造工艺中最关键的部分是布线,这是因为该器件的工作速度、成品率和可靠性全取决于该布线方法。在一种常规的低集成度的半导体器件内,金属的台阶覆盖不是一个重要的问题。但是近年来越来越高的集成度已使接触孔变得越来越小(即,直径是半个微米或更小),并使半导体衬底内的杂质注入区变得很薄。如采用常规的铝布线方法,要充填一个小于1μm的接触孔是困难的,结果在该接触孔内可能形成一个空洞,从而降低了该金属布线的可靠性。
在制造半导体器件的早期阶段,使用纯铝在一个硅衬底上形成一个金属布线层。但在其后的烧结阶段内,当温度增加时,所形成的铝层从该衬底吸收硅原子,故产生结(Al)的尖峰。因而已广泛地使用Al—1%Si(用硅对铝进行超饱和处理后得到的合金)作为金属布线层的材料。
但当使用Al—1%Si来形成半导体器件的布线时,硅在进行高于450℃的温度下的热处理期间从该铝膜中析出,从而形成一种硅的剩余物。此外,通过硅原子的固相外延生长在接触孔内形成硅的球结,从而增加了布线电阻和接触电阻。
为了防止由于在金属布线层与半导体衬底之间的相互作用而产生的上述铝尖峰、硅的剩余物和硅的球结,在该布线层与硅衬底间或该布线层与一个绝缘层间形成一扩散阻挡膜。例如,由Yokoyama等在美国专利No.4,897,709中公开的一种在一个接触孔的内壁上形成作为扩散阻挡膜的氮化钛(TiN)膜的方法。此外,在日本专利公开No.61—183942中公开了一种如下的技术:形成一种由一种难熔金属(Ti)膜和TiN膜组成的双层膜,并对其进行热处理来作为一种扩散阻挡层,以及钛(Ti)层与半导体衬底相互作用以形成一种在与该半导体衬底相连的一个接触孔的底部内由热稳定化合物组成的难熔金属硅化层,从而增强了阻挡效应。一般来说,这样一种扩散阻挡膜是在一种氮气气氛内进行退火的。若不对该扩散阻挡膜进行退火,当在超过450℃的一个温度下溅射铝或铝合金时或在进行烧结时,会产生结的尖峰,而这种尖峰是不希望出现的。此外,使用一种TiN或TiW膜作为扩散阻挡膜。但在该TiN或TiW膜内存在一种不能完全防止铝或硅在晶粒边界处的扩散的微结构缺陷。
此外,已提出了一种通过使用一种氧填塞法来阻塞晶粒间界处的扩散通道的方法(参见由J.B.Stimmel和B.N.Mehrotra写的“氧在反应溅射的TiN膜上的效应”,第375—382页,发表于“应用于VLSI的钨和其它难熔金属III,1988)。一般来说,在淀积TiN和将其暴露于环境气氛时,该暴露的TiN与环境气氛中少量的氧混合,从而增加了扩散阻挡效应。这种效应被称为填塞效应。更具体地说,Stimmel和Mehrotra告诉我们,氧在阻挡金属的表面以及在晶粒间界处以氧化物的形式存在,这就解释了填塞效应。
但如果把由淀积Ti或TiN形成的一个阻挡层暴露于环境气氛中,或如果通过与氧混合来淀积TiN,或如果在一种混有氧的氮气气氛中对TiN进行退火,接触电阻就可能增加。因此,TiN膜的阻挡特性依暴露在环境气氛中的时间、在淀积期间内流入的氧的量、在退火中的氧的量以及温度而改变。对该阻挡层进行退火的工艺条件是:温度在450℃至550℃之间、氮气气氛以及持续时间为30—60分。已知该工艺条件是一种最佳条件。
但是,在对扩散阻挡膜进行退火时引入的氧填塞效应引起该扩散阻挡膜表面的氧化,因而在其后的工艺中通过使用铝对接触孔进行填埋时引起诸如接触特性等方面的问题。因此,此种氧填塞效应降低了半导体器件的可靠性。为了提高半导体器件的可靠性,已提出一种用于插入一个改善该金属层的可沾性的润湿层的方法以及一种在形成硅烷化层和进行氢处理之后填埋接触孔的方法。
在其它方法中,为了增强在该阻挡金属与铝布线间的可沾性和提高布线质量和成品率,在对TiN层(即阻挡层)进行退火后通过离子注入法来注入Si或O2(Higatta Masafumi的日本专利公开No.88—176035)。
在另一种公开的方法中,在溅射铝之前淀积钛以及在其后淀积一种高温铝以充填一个大小为0.5μm、纵横比为1.6的通孔的情况下,如钛层薄的话,充填效应就下降(参见:VMIC 170—176,1991)。但当接触孔的尺寸变小时(即小于0.5μm),该接触孔未被完全填满,或在该接触孔内产生空洞,从而降低了可靠性。
图1—3是显示一种常规的填埋开口(接触孔)的布线结构的剖面图,其中举例说明了在充填接触孔时可能产生的各种问题。首先,在半导体衬底上形成一个将变成源/漏区的杂质扩散区4。然后在由此得到的结构上形成一个具有部分地暴露杂质扩散区4的一个接触孔6的绝缘层8。(这里为了解释的方便起见,没有示出在MOS结构中的栅电极)。之后在接触孔6的内侧壁表面上、在由接触孔6暴露的杂质扩散区4上和在绝缘层8上相继地形成作为欧姆接触层的钛层(未示出)和作为扩散阻挡层的TiN层10。此外,在TiN层10上形成用于充填接触孔6的铝层12。
同时,可按下述方式来制造上述填埋接触孔的布线结构。
首先,通过一种普通的硅局部氧化法(LOCOS)在半导体衬底2上形成一个场氧化膜(未示出),并在该场氧化膜之间的半导体衬底2上淀积一种杂质,从而形成作为源/漏区的杂质扩散区4。然后,用普通的化学汽相淀积(CVD)法在由此得到的结构上淀积一种绝缘材料,例如氧化硅(SiO2),从而形成绝缘层8。之后在绝缘层8上形成一个用于形成接触孔6的光致抗蚀剂图形(未示出),然后应用该光致抗蚀剂图形作为刻蚀掩模对绝缘层8进行刻蚀,直到暴露出杂质扩散区4为止,从而形成开口6。然后在开口6的内侧壁表面上、在由开口6暴露出的杂质扩散区4和绝缘层8上用溅射法淀积厚度为300至900的钛层,从而形成欧姆接触层。接着通过一种溅射法在该钛层上形成厚度为600至2000的扩散阻挡层(层10)。用溅射法在由此得到的结构上淀积铝以形成用于填埋开口6的铝层12。
在上述常规的填埋接触孔的布线结构和制造该结构的方法中,主要通过一种溅射法形成Ti层(即欧姆接触层)、TiN层10(即扩散阻挡层)和铝层12。但是当该接触孔的纵横比增加时,通过常规的溅射法进行淀积时会产生如图1和图2中示出的空洞14,从而降低了制成的器件的可靠性。而且按照该常规技术,铝层的台阶覆盖范围也较差(如在图3中示出的),以致于有产生布线短路的趋势。因而降低了器件的可靠性。
图4说明当在图1—3中示出的扩散阻挡膜上淀积铝时,铝膜的一种起始的成核现象,图4还包括说明该起始成核现象的该侧壁部分的放大视图。这里,参照数字10表示TiN层,10a表示TiN晶粒,12表示铝层,而12a表示铝晶粒。以下将参照图4来说明在开口的内侧壁内形成的该TiN层的特性和铝层的一种表面形态。
由于当进行淀积时在一个开口的内侧壁上形成的该TiN层,其表面在结构上垂直于靶,故只淀积相对来说较少量的溅射原子。当应用一种准直技术时,就明显地产生这种趋势。此外,由于TiN易于在<111>方向上生长,故形成柱状的晶粒10a。
同时,一般来说,由溅射法或CVD法得到的TiN层不是非晶态的。因此,形成较少量的溅射原子的该接触孔的内侧壁具有一个粗糙的表面。因此,在该粗糙的扩散阻挡膜上形成的铝原子的起始淀积特性是较差的。换言之,铝围绕该相对来说较大的TiN晶粒的成核现象不是均匀地产生的,正如在该放大图中示出的那样,铝的淀积是以一种不平坦和不连续的方式进行的。因而,即使在其后的工艺过程中通过在接触孔中淀积铝而进行热处理,但还是产生了空洞,而且在一个具有高纵横比的接触孔内产生这样的空洞变得更容易。因此就降低了半导体器件的可靠性。
因此,本发明的目的是提供一种半导体器件的布线结构,这种结构用于形成一个扩散阻挡膜的一个平坦的表面,从而有效地填埋具有高台阶的一个接触孔。
本发明的另一个目的是提供一种适合于形成具备平坦表面的扩散阻挡膜的半导体器件布线结构的方法。
为了达到本发明的上述目的,所提供的一种半导体器件的布线结构包括:一个半导体衬底;一个形成在该半导体衬底上并包括一个开口的绝缘层;一个具有平坦表面的扩散阻挡膜,该平坦表面是通过在该开口的两侧壁上进行一种等离子体辐照而形成的;以及在该扩散阻挡膜上形成的一个金属层。
该扩散阻挡膜由一种难熔金属或一种难熔金属化合物组成。具体地说,该难熔金属可以是Ti,该难熔金属化合物可以是TiN。此外,该开口是一个用于暴露该半导体衬底的杂质扩散区的接触孔或是一个用于暴露一较低的导电层的通孔。该金属层可以由铝或铝合金形成。
此外还提供了一种半导体器件的布线结构,该结构包括:一个半导体衬底;一个形成在该半导体衬底上、且其中包括一个开口的绝缘层;具有一个平坦表面的扩散阻挡膜,该平坦表面是通过在该开口的两侧壁上进行一种等离子体辐照而形成的;以及填埋于形成该扩散阻挡膜的该开口内的一个金属层。
本发明所提供的一种用于形成半导体器件布线结构的方法包括以下步骤:在一个半导体衬底上形成一个绝缘层;在该绝缘层上形成一个开口;在该绝缘层上、在由该开口暴露出的衬底上和在该开口的内侧壁上形成一个扩散阻挡膜,对在该开口的内侧壁上形成的扩散阻挡膜的表面进行等离子体辐照;以及在该经过等离子体辐照的扩散阻挡膜上形成一个金属层。
在本发明中应用等离子体来使该扩散阻挡膜的表面变得平坦。该等离子体是通过应用一种隋性气体的电子回旋共振(ECR)等离子体装置、高频等离子体装置或一种磁控管增强的等离子体装置来形成的。具体地说,可通过把氢加到该隋性气体中来增强等离子体处理效果。
此外,可通过一种化学汽相淀积(CVD)法来形成该金属层以及可在形成该扩散阻挡层的步骤之后再进行一个热处理过程。此外,可在形成该金属层的步骤之后还包括进行热处理过程的一个步骤以填埋该开口。
此外,本发明的方法还可包括在填埋该开口的步骤之后形成一个第二金属层的步骤。可通过二种淀积工艺来形成该金属层,首先在一个第一温度下淀积,其次在一个第二温度下淀积。该第一温度应低于该第二温度。
提供了本发明的另一个实施例,包括以下步骤:在半导体衬底上形成一个绝缘层;在该绝缘层上形成一个开口;在该绝缘层上、在由该开口暴露出的衬底上和该开口的内侧壁上形成一个第一扩散阻挡膜;对在该开口的侧壁上形成的该第一扩散阻挡膜的表面进行等离子体辐照;在该已经过等离子体辐照的第一扩散阻挡膜上形成一个第二扩散阻挡膜;在形成了该第二扩散阻挡膜的整个衬底上形成一个金属层;以及通过在该金属层上进行一个热处理过程来填埋该开口。
该金属层可在形成该第二扩散阻挡膜之后不中止真空的情况下形成。此外,在形成该金属层的步骤之后还可包括形成一个第二金属层的步骤。
再者,可在形成该第二扩散阻挡膜的步骤之后进行一个热处理过程。而且可在对第一扩散阻挡膜的表面进行等离子体辐照的步骤之后进行一个热处理过程。
提供了一种用于形成一种半导体器件的布线的方法,包括以下步骤:在一个半导体衬底上形成一个绝缘层;在该绝缘层上形成一个开口;在该绝缘层上、在由该开口暴露出的衬底上和该开口的内侧壁上形成一个第一扩散阻挡膜;用等离子体辐照该开口的侧壁上形成的第一扩散阻挡膜的表面;在该已经过等离子体辐照的第一扩散阻挡膜上形成一个第二扩散阻挡膜;以及在形成该第二扩散阻挡膜的整个衬底上进行高温溅射从而填埋该开口。
由于铝原子的起始淀积特性是良好的,故在光滑的扩散阻挡膜上形成该金属层(即一个铝膜),以使铝膜均匀地和连续地淀积,从而使其具有一种良好的台阶覆盖范围。因此就可有效地填埋一个具有高台阶的接触孔,从而提高器件的可靠性。
通过在参照附图的情况下详细地描述较佳实施例,本发明的上述目的和其它优点将变得更明显。这些附图如下:
图1、2和3是表明常规填埋布线结构的各种问题的剖面图;
图4说明当在图1—3中示出的该扩散阻挡膜上淀积铝时铝膜的一种起始成核现象;
图5说明本发明半导体器件的一种布线层结构和金属层在一个开口的侧壁上的起始成核现象;
图6A—6D示出一种用于形成本发明的半导体器件布线层的方法的实施例1,其中图6B和6C各包括一个显示该开口的侧壁上形成的扩散阻挡膜表面的放大视图;
图7A—7C是一种用于形成本发明的半导体器件布线层的方法的实施例2的剖面图;
图8A—8C是一种用于形成本发明的半导体器件布线层的方法的实施例3的剖面图;
图9A—9C是一种用于形成本发明的半导体器件布线层的方法的实施例5的剖面图,其中图9A包括显示该开口的侧壁上形成的该扩散阻挡层表面的一个放大视图;
图10A—10C是一种用于形成本发明的半导体器件布线层的方法的实施例6的剖面图;以及
图11和12分别是一个按照本发明进行了等离子体辐照的TiN表面和一个常规的未进行等离子体辐照的TiN表面的SEM照片。
以下将参照图5说明按照本发明的一种半导体器件金属布线层的结构。(为了简化本发明的说明,未示出栅区,并省略了有关该栅区的说明)。
参照图5,在半导体衬底31上形成将成为源/漏区的一个杂质扩散区33。该杂质可以是N+也可以是P+型,可在该杂质扩散区的右边和左边形成一个场氧化膜(未示出)。这里,在半导体衬底31内形成的杂质扩散区33只是适合于达到本发明目的的一个硅层的实施例,这是提供一种用于把硅层内的上部导电层填埋到一个开口(例如接触孔或通孔)的较低部分的填埋接触孔的结构。举例来说,在半导体衬底内形成的杂质扩散区33可由一个较低的导电层(未示出)来代替,例如,该较低的导电层是一个在该半导体衬底顶部的一个任意的较低结构上形成的多晶硅层。该填埋接触孔的结构(在以下部分进行描述)的实施例可适用于在该较低的导电层上形成的填埋通孔结构。
在由此得到的结构上形成一个带有开口(接触孔)的绝缘层35,该开口用于暴露该杂质扩散区。绝缘层35由例如氧化硅的绝缘材料组成。该开口可以是一个用于暴露出杂质扩散区33的接触孔或是一个用于暴露出较低的导电层(如多晶硅)的通孔。
然后形成一个扩散阻挡膜37。该扩散阻挡膜37可以是在Ti层(未示出)上形成的TiN层。在该开口的内表面上、在由该开口暴露出的杂质扩散区33上和绝缘层35上形成该Ti层。该扩散阻挡层37也可以是一个Ti层。
然后通过一种溅射法在由此得到的结构上淀积铝,从而形成用于填埋该开口的一个金属层41。
在图5中,用在该开口的侧壁上形成的扩散阻挡膜和金属层的一个详细视图显示该金属层的一种起始成核现象。在这里,在该开口的侧壁上形成一个没有晶粒边界的、光滑的扩散阻挡膜37。在扩散阻挡膜37的侧壁上的铝原子的起始淀积特性是良好的。换言之,由于均匀的TiN晶粒或TiN膜的光滑表面而均匀地产生铝膜的成核过程。因此,与常规的技术不同,采用本发明的方法可均匀地和连续地淀积该铝膜。实施例1
图6A—6D是显示一种用于形成本发明的半导体器件布线层的方法的实施例1的剖面图,其中图6B和6C包括说明该开口内侧壁上形成的扩散阻挡膜的一个表面的放大视图。
图6A说明在半导体衬底31上形成具有一个开口的绝缘层35的步骤。
通过一种普通的LOCOS法在半导体衬底31上形成一个场氧化膜(未示出),以及在场氧化膜间的半导体衬底31上以离子注入方式注入一种N+或P+型杂质,从而形成用作源/漏区的杂质扩散区33。在这里,形成该场氧化膜的工艺是任意的,而且按照本发明的目的,该杂质扩散区可由一个任意的硅层(例如多晶硅)来代替。
用一种普通的CVD法在由此得到的结构上淀积一种绝缘材料,例如氧化硅(SiO2),从而形成一个绝缘材料层。应用硼磷硅酸盐玻璃(BPSG)形成厚度为0.8至1.6μm的绝缘材料层。其后在该绝缘材料层上形成用于形成开口的光致抗蚀剂图形(未示出)。然后把该光致抗蚀剂图形用作一个刻蚀掩模,对该绝缘材料层进行刻蚀直到露出杂质扩散区33,从而形成具有一个开口的绝缘层35。
图6B显示在形成该开口的整个衬底上形成扩散阻挡层37的步骤。
在全部绝缘层35上、在开口36的内部和在暴露的半导体衬底31的表面上形成扩散阻挡膜37。更详细地说,在一种氩气气氛中和真空度为2毫乇的条件下用溅射法淀积厚度为200A至300A的Ti,以及在氩气的流量为30—50sccm和氮气的流量为50—85sccm的条件下用溅射法淀积厚度为300A至500A的氮化钛,从而形成扩散阻挡膜37。当淀积该Ti层时,淀积速率约为500A/分。此外,当淀积Ti或TiN时,衬底温度为200℃。
具体地说,当淀积Ti层或TiN层时,可使用一种准直技术。该准直器的尺寸是5/8″,纵横比是1.5∶1。此外,在该开口的侧壁上形成的TiN层在该接触孔的侧壁内有一个粗糙的表面,正如在图6B的放大视图内示出的,在该接触孔的侧壁处形成较少量的溅射原子。
图6C示出对TiN层37的表面进行等离子体辐照的步骤。
用氩等离子体对TiN层37的表面进行腐蚀,应用ECR(电子回旋共振)等离子体、高频等离子体或一种磁控管增强的等离子体装置来进行该等离子体辐照。
更详细地说,在应用该氩等离子体进行等离子体辐照期间,通过在侧壁上形成的TiN层与氩离子(Ar+)之间的碰撞或通过氩离子的动量在TiN层内的吸收对该TiN层进行腐蚀。其结果是形成了具有一个光滑表面的、没有晶粒边界的TiN层39b和具有一个粗糙表面的TiN层39a。
首先将对应用ECR等离子体的一种等离子体辐照进行说明。
通过应用ECR等离子体在加上一个约为50V的高频偏压的状态下对TiN层37的表面进行等离子体辐照。更详细地说,该ECR等离子体装置是在以下的工艺条件下进行该工艺过程的:微波功率是1千瓦(磁控管频率:2.45GHz),氩气压力是5毫乇和衬底温度是环境温度。当一个标准的氧化膜(SiO2)被刻蚀100A时该TiN层约被刻蚀30A。具体地说,当应用ECR等离子体装置时,把一个小的偏压加到衬底上可能是有利的,而且可通过加入氢来增加表面处理效果。
以下将对通过一个高频或磁控管增强的等离子体装置进行的等离子体辐照进行说明。
该溅射装置是在以下的条件下进行等离子体辐照的:频率是13.56MHz,偏置电压是960V,氩气气压是7毫乇和衬底温度是200℃。在这里,等离子体辐照的溅射刻蚀是以100A的氧化膜(SiO2)作为一个标准来进行的。当对一个超过100A的标准氧化膜进行刻蚀时,其效果是相同的。对该开口的侧壁上的TiN晶粒的粗糙表面进行腐蚀,从而形成如在图6C的放大视图中示出的、具有平坦表面的TiN层。
图6D示出形成用于填埋一个开口的金属层41的步骤。
更详细地说,用溅射法在该开口的内侧壁和由该开口暴露出的杂质扩散区33上淀积铝,从而形成用于填埋该开口的金属层41。金属层41的淀积是在以下的条件下进行的:淀积温度是200℃,氩气气压是4毫乇和淀积速率是每秒50至150A。更希望把淀积速率控制在每秒125A。正如以上所描述的,由于在光滑的TiN层上形成的一个铝层的成核过程是均匀地发生的,故可提高淀积特性和台阶覆盖范围。
同时,为了得到更好的台阶覆盖范围,首先在低于100℃的温度和每秒50A至100A的淀积速率下淀积铝。然后在高于200℃的温度和每秒100A至150A的较高的淀积速率下淀积铝。因此,可同时得到在低温淀积时的良好的台阶覆盖范围和在高温淀积时的原子迁移率的改善。实施例2
图7A—7C是一种用于形成本发明的半导体器件布线层的方法的实施例2的剖面图。除了在低温下形成金属层和进行一个真空热处理过程的步骤外,实施例2与实施例1是相同的。在这里,用于实施例1相同的参照数字表示同样的元素。在实施例2中进行的第一批步骤也与对应于在实施例1中的图6A—6C的第一批步骤相同。
图7A显示形成第一金属层43a的步骤。更详细地说,在开口的内侧壁上、在由该开口暴露出的一个衬底上和在一个扩散阻挡膜上形成由铝或一种铝合金(例如,Al—Si—Cu)组成的一个第一金属层43a。应用一种直流磁控管装置形成第一金属层43a,其工艺条件如下:温度低于200℃(所希望的低温是25℃),真空度低于5.0E—7乇(更希望真空度低于5.0E—8乇)和淀积速率是每秒100A。在形成第一金属层43a时,可使用低压溅射或准直技术,为了减少在该开口的顶部的一种悬垂现象,以上工艺要在一个工作压力低于2毫乇的条件下进行。
图7B显示在第一金属层43a上进行一个热处理过程的步骤。在这里,通过提高该直流磁控管装置的温度或把该衬底转移到一个高温室中对在该开口上形成的第一金属层43a进行真空热处理。更详细地说,该真空热处理是以下述方式来进行的:在不中止真空的情况下对第一金属层43a进行2分钟的热处理,该热处理的条件为:温度是该铝合金的熔点的50%至90%(例如高于450℃),以及气氛为氩气气氛或低于10毫乇的减压气氛。通过以上热处理来移动在低温下溅射的铝合金的原子。其结果如图7B所示,该开口被填埋,从而形成填埋了的第一金属层43b。在这里,当进行淀积或真空热处理时,热处理的温度可随真空度的提高降低。
图7C说明在该填埋了的第一金属层43b上形成第二金属层47的步骤。更详细地说,通过使用与在该填埋了的第一金属层43b上的第一金属层43a相同的材料形成一个第二金属层47。但是在因为形成第一金属层43a使其达到所希望的厚度并对该金属层进行热处理而把该开口填埋,故较少发生悬垂现象的情况下,该形成第二金属层47的步骤可能不是必需的。实施例3
图8A—8c是一种用于形成本发明的半导体器件布线层的方法的实施例3的剖面图。除了通过首先在一个低于200℃的温度下淀积一种金属材料和其次在一个高于400℃的温度下进行淀积来形成第一金属层43c和43d以外,实施例3与实施例2相同。在这里,与实施例2相同的参考数字表示同样的部分。在实施例3中进行的第一批步骤也与对应于实施例1中图6A—6C的第一批步骤相同。
图8A显示形成第一金属层43c和43d的步骤。在这里,在开口的侧壁上、在由该开口暴露的衬底上和在扩散阻挡膜上形成由Al—Si—Cu组成的第一金属层43c和43d。更详细地说,通过下述工艺形成第一金属层43c和43d。首先在200℃或更低的温度下淀积铝或一种铝合金(例如,Al—Si—Cu),使其厚度小于所希望的厚度的一半,其次在一个所希望的450℃的温度下淀积铝合金(Al—Si—Cu)。这里,在低温下(即200℃或更低)淀积速率必定低于100A/秒,在高温下(即400℃或更高)淀积速率为150A/秒。
图8B显示在第一金属层43c和43d上进行热处理过程的步骤。更详细地说,通过提高一个直流磁控管装置的温度或把该衬底转移到一个高温室中来对在该开口上形成的第一金属层43c和43d进行真空热处理。由于此种真空热处理,铝的表面原子发生移动。因此如图8B中所示填埋该开口,从而形成填埋了的第一金属层43e。在这里,当进行淀积或真空热处理时,随真空度的提高可降低热处理的温度。
图8C显示在该填埋了的第一金属层43e上形成一个第二金属层49的步骤。更详细地说,使用与在该填埋了的第一金属层43e上的第一金属层43c和43d相同的材料形成第二金属层49。因为可形成第一金属层43e使其达到一个所需的厚度以及对该金属层进行热处理从而填埋该开口,故该形成第二金属层49的步骤可能是不必要的。实施例4
除了在实施例3中形成第二金属层之后进行第二真空热处理过程之外,实施例4与实施例3相同。更详细地说,按顺序进行实施例3的工艺步骤,并在其后进行一个第二真空热处理过程。该第二真空热处理在第一真空热处理的温度下(例如450°)进行。或者该第二真空热处理在第一真空热处理的一个低温下进行。实施例5
图9A—9C是显示一种用于形成本发明的半导体器件布线层的方法的实施例5的剖面图,其中图9A包括一个显示形成在该开口的侧壁上的扩散阻挡膜的一个表面的放大视图。除了在形成第一金属层之前形成第二扩散阻挡膜之外,实施例5与实施例3和4相同。在这里,用与实施例4相同的参考数字表示同样的部分。在实施例5中进行的第一批步骤也与对应于实施例1中的图6A—6C的第一批步骤相同。
图9A说明形成第二扩散阻挡膜42和第一金属层43f的步骤。
在进行对应于图6C的步骤之后,在450℃的一种氮气气氛中对该第一扩散阻挡膜进行热处理,从而增强该扩散阻挡膜的热耐久性。这样一种热持久性的增强来自于氧填塞效应和在该TiN层下形成的Ti层中的硅化过程。换言之,当在该TiN层下的Ti与其后形成的铝发生反应时,形成Al3Ti。这样一来,由于硅和Al3Ti具有一种高溶解度,在温度达到450℃时产生结的尖峰。所以,在Ti与Si之间的反应产生TiSi2/TiN结构,从而增强该扩散阻挡膜的热持久性。此外,在进行热处理之后,第一扩散阻挡膜(即TiN层)在该开口的侧壁上保持一个平坦的表面。
然后,为了增强铝膜的可沾性,通过在该开口的侧壁上、在由该开口暴露出的衬底上和在该第一扩散阻挡膜上淀积厚度达100A至200A的Ti或TiN来形成第二扩散阻挡膜42。具体地说,在该开口的侧壁的平坦表面上形成非常小和具有规则的尺寸的TiN晶粒(即第二扩散阻挡膜42)。
形成由铝或一种铝合金(即Al—Si—Cu)组成的第一金属层43f。由于是在该开口侧壁的平坦表面上以非常小和有规则的尺寸形成该TiN晶粒,故该第一金属层的起始成核过程是均匀地发生的,而且可形成一种良好的台阶覆盖范围。第一金属层43f可通过如在实施例3和4中描述的两个步骤来形成。
图9B显示在第一金属层43f上进行热处理的步骤。
更详细地说,对在该开口上形成的第一金属层43f进行真空热处理。由于如图9B所示的真空热处理,铝膜的表面原子移动至该开口并被填埋于其内,从而形成一个填埋的第一金属层43g。由于该填埋的第一金属层43g在铝淀积的早期阶段表现出均匀的成核现象并且具有良好的台阶覆盖范围,故当进行热处理时可改善填埋特性。其结果是可提高半导体器件的可靠性。
除了上述紧接着在第一金属层形成之后进行热处理的填埋方法以外,可通过在超过400℃的一个温度下的高温溅射来形成该填埋的第一金属层。
图9C显示在该填埋的第一金属层43g上形成一个第二金属层51的步骤。
更详细地说,通过应用与第一金属层43g相同的材料在该填埋的第一金属层43g上形成第二金属层51。但在悬垂现象较少发生的情况下,形成第二金属层51的步骤可能是不必要的,这是因为可形成第一金属层43g使其达到一个所需要的厚度,并可对该金属层进行热处理使其填埋该开口。实施例6
图10A—10C是表示用于形成本发明的半导体器件布线层的方法的实施例6的剖面图。除了在用CVD法形成一个第一金属层之后对该第一金属层进行真空热处理,或在该第一金属层上溅射一种铝合金并进行真空热处理从而填埋该开口以外,实施例6与实施例2至5是相同的。在这里,用与实施例2相同的参考数字表示同样的元素。在实施例6中进行的第一批步骤也与对应实施例1中的图6A—6C的第一批步骤相同。
图10A表示形成第一金属层43h的步骤。在开口的侧壁上、在由该开口暴露出的该衬底上和在扩散阻挡膜上通过CVD法形成由铝组成的第一金属层43h。更详细地说,可通过一种普通的CVD法进行铝或一种铝合金的淀积。例如,可应用一种有机金属化合物,例如三异丁基铝(TIBA)或二甲基氢化铝((CH3)2AlH:DMAH),作为一种源进行上述淀积。当通过应用TIBA进行淀积时,应用一种冷壁型装置以在引入TIBA时保持一个低于90℃(希望是在84—86℃间)的汽相温度。此外,使一种隋性气体(例如氩气)鼓泡而用作为一种携带气体。在这里,所希望的氩气的流速约为71/分。该TIBA的热分解的淀积温度约为250℃,而这由于淀积速率高而是不希望的。由于淀积速率随温度的降低而降低,故为了降低淀积速率可在一个较低的温度下进行淀积。在这种条件下,淀积速率约为1000A/分,对于一个尺寸为0.2μm的接触孔来说,用TIBA进行约1分钟的铝淀积。
另一种可采用的方法是用一种氢化铝(如DMAH等)来淀积第一金属层43h。此时,氢化铝保存在一个低温下,并且在一个超过50℃的温度下进行淀积,以便防止该氢化铝的热分解。可通过一种隋性气体(例如氩)控制源温。此外,可通过降低衬底温度和减少源量来降低淀积速率。在应用氢化铝进行的淀积方法中,通过使用一种合适的源可以降低淀积温度。上述淀积在一个气压为0.01—10乇和温度为50—150℃的反应室内进行。由于是在该开口侧壁上形成的TiN的平坦表面上由CVD法形成第一金属层43h,故如图10A所示,得到了良好的台阶覆盖范围。
图10B表示通过在第一金属层43h上进行热处理而填埋一个开口的步骤。更详细地说,在不中止真空的情况下对在该开口上形成的第一金属层43h进行真空热处理,或者在该第一金属层43h上溅射一种铝合金(例如Al—Si—Cu),并进行真空热处理。该铝膜的表面原子由于真空热处理而产生移动,从而如图10B中所示那样填埋该开口,由此形成填埋的第一金属层43i。当进行淀积或真空热处理时,热处理的温度可随真空度的增加而降低。
同时,当通过CVD法形成第二金属层时,如该第二金属层的厚度达到该开口尺寸的一半的话,则可在无缝隙或空洞的情况下填埋该开口。这样一来,就可在不进行真空热处理的情况下填埋该开口。如果产生了缝隙或空洞,可通过其后的真空热处理过程将其除去。因此,该真空热处理过程是可选择的。
图10C显示出在该填埋的第一金属层43i上形成第二金属层53的步骤。更详细地说,通过一种溅射法,应用与在该填埋的第一金属层43i上的第一金属层43h相同的材料形成第二金属层53。在另一种方式下,在该填埋的第一金属层43i上溅射与第一金属层43h相同的材料,从而形成将对其进行真空热处理的第二金属层53。因为可以形成第一金属层43h使其达到一个所希望的厚度,并且对其进行热处理从而填埋该开口,故该形成第二金属层53的步骤可能是不必要的。比较例
图11和12分别是按照本发明进行了等离子体辐射的TiN表面的SEM照片和未进行等离子体辐照的常规的TiN表面的SEM照片。在图11中,TiN的表面是平坦的,且没有晶粒边界。在图12中,常规技术得到的TiN表面是粗糙的。
按照本发明,由于铝原子的起始淀积特性是良好的,故可均匀地和连续地形成该金属层的一个铝膜。这样一来,在该平坦的扩散阻挡膜的侧壁上形成的该金属层的铝膜具有良好的台阶覆盖范围。因此,可在不产生空洞的情况下有效地填埋具有高纵横比的一个接触孔,从而提高制成器件的可靠性。
不言而喻,对于本领域的专业人员来说,以上的描述只涉及该公开的器件的较佳实施例,在不偏离本发明的精神和范围的前提下可在本发明中作各种变动和修正。
Claims (20)
1.一种半导体器件的布线结构,其特征在于包括:
一个半导体衬底;
在上述半导体衬底上形成的一个绝缘层,且该绝缘层包括一个形成在其中的开口;
一个具有平坦表面的扩散阻挡膜,该平坦表面是在上述开口的两侧壁上通过一种等离子体辐照形成的;以及
在上述扩散阻挡膜上形成的一个金属层。
2.按照权利要求1的半导体器件布线结构,其中,上述扩散阻挡膜由一种难熔金属或难熔金属化合物组成。
3.按照权利要求2的半导体器件布线结构,其中,上述难熔金属是Ti,上述难熔金属化合物是TiN。
4.按照权利要求1的半导体器件布线结构,其中,上述开口是用于暴露出上述半导体衬底的一个杂质扩散区的接触孔或一个用于暴露出一个较低的导电层的通孔。
5.一种半导体器件的布线结构,其特征在于包括:
一个半导体衬底;
在上述半导体衬底上形成的一个绝缘层,且该绝缘层包括一个形成在其中的开口;
一个具有平坦表面的扩散阻挡膜,该平坦表面是在上述开口的两侧壁上通过一种等离子体辐照形成的;以及
一个填埋于形成上述扩散阻挡膜的上述开口内的金属层。
6.一种用于形成半导体器件布线结构的方法,其特征在于包括以下步骤:
(a)在一个半导体衬底上形成一个绝缘层;
(b)在上述绝缘层上形成一个开口;
(c)在上述绝缘层、由上述开口暴露的衬底和上述开口的内侧壁上形成一扩散阻挡膜;
(d)对在上述开口的内侧壁上形成的扩散阻挡膜的表面进行等离子体辐照;以及
(e)在上述经过等离子体辐照的扩散阻挡膜上形成一个金属层。
7.按照权利要求6的用于形成一半导体器件布线结构的方法,其中,等离子体是由从下列一组装置中选出的一种形成的:使用一种惰性气体的ECR等离子体装置、高频等离子体装置和磁控管增强的等离子体装置。
8.按照权利要求7的用于形成半导体器件布线结构的方法,其中,通过把氢加入到上述隋性气体中来促进等离子体效果。
9.按照权利要求6的用于形成半导体器件布线结构的方法,其中,通过CVD法形成上述金属层。
10.按照权利要求6的用于形成半导体器件布线结构的方法,其特征在于:还包括在上述步骤(c)后进行热处理的步骤。
11.按照权利要求6的用于形成半导体器件布线结构的方法,其特征在于:还包括在上述步骤(e)后进行热处理从而填埋上述开口的步骤。
12.按照权利要求11的用于形成半导体器件布线结构的方法,其特征在于:还包括在上述填埋上述开口的步骤后形成第二金属层的步骤。
13.按照权利要求6的用于形成半导体器件布线结构的方法,其中,通过两步工艺形成上述金属层,首先在一个第一温度,其次在一个第二温度下进行。
14.按照权利要求13的用于形成半导体器件布线结构的方法,其中,上述第一温度低于上述第二温度。
15.用于形成一个半导体器件布线结构的方法,其特征在于包括以下步骤:
(a)在半导体衬底上形成一个绝缘层;
(b)在上述绝缘层上形成一个开口;
(c)在上述绝缘层、由上述开口暴露的衬底上和上述开口的内侧壁上形成一个第一扩散阻挡膜;
(d)对在上述开口的侧壁上形成的第一扩散阻挡膜的表面进行等离子体辐照;
(e)在上述经过腐蚀的第一扩散阻挡膜上形成第二扩散阻挡膜;
(f)在形成上述第二扩散阻挡膜的整个衬底上形成一个金属层;以及
(g)通过在上述金属层上进行热处理来填埋上述开口。
16.按照权利要求15的用于形成半导体器件布线结构的方法,其中,在上述步骤(e)后在不中止真空的情况下形成上述金属层。
17.按照权利要求15的用于形成半导体器件布线结构的方法,其特征在于:还包括在上述步骤(f)后形成一个第二金属层的步骤。
18.按照权利要求15的用于形成半导体器件布线结构的方法,其特征在于:还包括在上述步骤(e)后进行热处理的步骤。
19.按照权利要求15的用于形成半导体器件布线结构的方法,其特征在于:还包括在上述步骤(d)后进行热处理的步骤。
20.一种用于形成半导体器件布线结构的方法,其特征在于包括以下步骤:
在一个半导体衬底上形成一个绝缘层;
在上述绝缘层上形成一个开口;
在上述绝缘层、由上述开口暴露的衬底上和上述开口的内侧壁上形成一个第一扩散阻挡膜;
对在上述开口的侧壁上形成的第一扩散阻挡膜的表面进行等离子体辐照;
在上述经过刻蚀的第一扩散阻挡膜上形成一个第二扩散阻挡膜;以及
在形成上述第二扩散阻挡膜的整个衬底上进行高温溅射从而填埋上述开口。
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- 1995-06-07 GB GB9511567A patent/GB2290166B/en not_active Expired - Fee Related
- 1995-06-09 CN CN95107381A patent/CN1061782C/zh not_active Expired - Fee Related
- 1995-06-09 DE DE19521150A patent/DE19521150B4/de not_active Expired - Fee Related
- 1995-06-09 JP JP16832995A patent/JP3963494B2/ja not_active Expired - Fee Related
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1997
- 1997-06-12 US US08/873,869 patent/US5998870A/en not_active Expired - Lifetime
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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CN1314100C (zh) * | 2001-11-07 | 2007-05-02 | 株式会社日立制作所 | 半导体器件的制造方法和半导体器件 |
CN101001973B (zh) * | 2004-08-10 | 2010-07-14 | 日矿金属株式会社 | 柔性铜衬底用阻挡膜和用于形成阻挡膜的溅射靶 |
US8681084B2 (en) | 2004-09-17 | 2014-03-25 | Gold Charm Limited | Semiconductor device, method for driving same, display device using same and personal digital assistant |
CN105810735A (zh) * | 2015-01-20 | 2016-07-27 | 台湾积体电路制造股份有限公司 | 金属栅极及其制造方法 |
CN105810735B (zh) * | 2015-01-20 | 2020-05-01 | 台湾积体电路制造股份有限公司 | 金属栅极及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
GB9511567D0 (en) | 1995-08-02 |
GB2290166B (en) | 1998-09-09 |
DE19521150A1 (de) | 1995-12-14 |
KR0144956B1 (ko) | 1998-08-17 |
DE19521150B4 (de) | 2009-07-02 |
CN1061782C (zh) | 2001-02-07 |
KR960002480A (ko) | 1996-01-26 |
GB2290166A (en) | 1995-12-13 |
US5998870A (en) | 1999-12-07 |
JPH07335759A (ja) | 1995-12-22 |
JP3963494B2 (ja) | 2007-08-22 |
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