CN110574151A - 经加工的堆叠管芯 - Google Patents

经加工的堆叠管芯 Download PDF

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Publication number
CN110574151A
CN110574151A CN201880028854.7A CN201880028854A CN110574151A CN 110574151 A CN110574151 A CN 110574151A CN 201880028854 A CN201880028854 A CN 201880028854A CN 110574151 A CN110574151 A CN 110574151A
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China
Prior art keywords
microelectronic
dielectric layer
semiconductor die
die
component
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CN201880028854.7A
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CN110574151B (zh
Inventor
C·E·尤佐
G·高
L·W·米卡里米
G·G·小方丹
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Evans Technology
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Evans Technology
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Priority to CN202311589853.9A priority Critical patent/CN117497456A/zh
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Abstract

技术和方法的代表性实施方式包括加工分割的管芯以准备用于键合。可以从晶圆部件分割多个半导体管芯部件，该半导体管芯部件各自具有基本平面的表面。可以从多个半导体管芯部件的边缘移除材料的颗粒和碎片。另外，多个半导体管芯部件中的一个或多个可以经由基本平面的表面键合到准备好的键合表面。

Description

经加工的堆叠管芯
优先权要求和相关申请的交叉引用
本申请要求2018年4月23日提交的美国专利申请号15/960,179和2017年5月11日提交的临时申请号62/504,834根据35 U.S.C.§119(e)(1)所享有的权益，这些申请据此以引用方式全文并入。
技术领域
以下描述涉及集成电路(“IC”)的加工。更具体地说，以下描述涉及用于加工准备键合的已分割管芯的技术。
背景技术
管芯可以作为各种微电子封装方案的一部分以三维布置堆叠。这可以包括在较大的基础管芯上堆叠一个或多个管芯的层、以竖直布置堆叠多个管芯以及两者的各种组合。管芯也可以堆叠在晶圆上，或者晶圆可以在分割之前堆叠在其他晶圆上。管芯或晶圆可以使用各种键合技术以堆叠布置来键合，包括使用直接电介质键合、非粘合技术，诸如直接键合技术或混合键合技术，这两种技术均可从Xperi Corp的子公司Invensas Bonding Technologies,Inc.(以前的Ziptronix,Inc.)获得(例如，参见美国专利号6,864,585和7,485,968，其以引用方式全文并入本文中)。
当使用直接键合技术键合堆叠的管芯时，希望待键合管芯的表面极其平坦和光滑。例如，表面应具有非常小的表面拓扑变化，使得表面可以紧密配合，以形成持久的键合。还希望表面清洁并且没有杂质、颗粒和/或其他残留物。例如，不期望的颗粒的存在可导致在颗粒的位置处的键合有缺陷或不可靠。例如，残留在键合表面上的一些颗粒和残留物可在堆叠管芯之间的键合界面处产生空隙。如果空隙显著小于金属电互连尺寸，它们可能是可接受的。然而，导致尺寸接近或超过电互连尺寸的键合缺陷的颗粒通常是不能容忍的，因为它们可能对互连的导电性产生负面影响。
因为半导体晶圆(例如，硅晶圆)是易碎的，所以当它们被分割时，在管芯的边缘处产生缺陷或颗粒是常见的。作为示例，硅在切割期间可能破裂，形成松散的颗粒。机械切割或锯切通常留下粗糙的边缘，并且还可能在切割的管芯的边缘上或附近留下硅颗粒或碎片。此外，机械锯切割通常将材料从划片片转移到分割的管芯的侧壁和边缘。激光切割也可能在管芯的表面或边缘上留下颗粒。在切割后，可以使用各种工艺来清洁管芯的表面。然而，这些工艺通常会在管芯的外围或管芯的边缘壁处留下一些颗粒。即使在管芯表面被抛光时，碎片仍可能存在于管芯的边缘或侧壁上。留下的松散颗粒和碎片可能会给形成可靠的键合带来麻烦。另外，这些松散或部分松散的颗粒可能会在后续操作中再次污染感兴趣的键合表面或键合工具等。
附图说明
参考附图阐述了详细描述。在这些图中，参考标号的一个或多个最左边的数字标识首次出现参考标号的图。在不同图中使用相同的附图标记表示相似或相同的项目。
对于该讨论，图中所示的装置和系统被示出为具有多个部件。如本文所述，装置和/或系统的各种具体实施可以包括较少的部件并且仍然在本公开的范围内。另选地，装置和/或系统的其他具体实施可以包括附加部件或所描述部件的各种组合，并且仍然在本公开的范围内。
图1(A)是显示根据实施方案的管芯的顶表面上的缺陷的剖面图。图1(B)是显示具有缺陷的键合管芯的截面的剖面图。图1(C)是显示没有缺陷的键合管芯的截面的剖面图。
图2是示出根据实施方案的加工堆叠管芯的示例性过程的图形流程图。
图3是示出根据另一个实施方案的加工堆叠管芯的示例性过程的图形流程图。
图4是示出根据又一个实施方案的加工堆叠管芯的示例性过程的图形流程图。
图5(A)是根据实施方案的具有凹进氧化物区域的管芯的剖面图。图5(B)是具有凹进氧化物区域的管芯的剖面图的放大图。图5(C)是具有凹进氧化物区域的键合管芯布置的示例。
图6是示出根据实施方案的用于加工堆叠管芯的示例性过程的流程图。
发明内容
可以使用各种实施方案和技术来加工准备用于键合的分割的管芯。这些实施方案包括补救在管芯上发现的缺陷累积的技术，并且包括移除、溶解或蚀刻在管芯的边缘处的颗粒以提供平滑的键合表面。管芯可以由半导体或非半导体材料构成。半导体材料可以例如包括直接带隙半导体或间接带隙半导体及其组合。非半导体材料可以包括例如电介质材料，例如玻璃、陶瓷、玻璃陶瓷、碳化硅、碳氧化硅、氮化硅或氮氧化硅、金刚石、氧化硅等，或者它们的组合。
微电子系统可以包括至少第一微电子部件，该第一微电子部件包括基础半导体层和电介质层，该电介质层具有基本平面的表面。另外，第二微电子部件可以在没有粘合剂的情况下直接键合到第一微电子部件的电介质层，该电介质层在电介质层的外围处具有底切，使得电介质层的面积小于第一微电子部件和/或第二微电子部件的覆盖区的面积。另选地，第二微电子部件可以包括至少第二基础半导体层和第二电介质层，第二电介质层具有基本平面的表面。另外，第二电介质层可以在第一基本平面的表面和第二基本平面的表面处在没有粘合剂的情况下直接键合到第一电介质层，第一基础半导体层和第二基础半导体层分别在第一基础半导体层和第二基础半导体层的外围处具有底切，使得第一基础半导体层的覆盖区的面积和第二基础半导体层的覆盖区的面积小于第一电介质层和/或第二电介质层的面积。
在第一实施方案中，在第一微电子部件和/或第二微电子部件的基础半导体层的外围处的底切可以对应于在第一微电子部件和/或第二微电子部件的电介质层的外围处的底切。
在第二实施方案中，第二微电子部件可以包括至少基础半导体层和具有基本平面表面的电介质层，第一微电子部件的电介质层直接键合到第二微电子部件的电介质层，并且第二微电子部件的电介质层在第二微电子部件的电介质层的外围处具有底切，使得第二微电子部件的电介质层的面积小于第一微电子部件和/或第二微电子部件的覆盖区的面积。
用于形成微电子系统的方法可以包括从晶圆部件中分割多个半导体管芯部件，半导体管芯部件各自具有基本平面的表面。可以从多个半导体管芯部件的边缘移除材料的颗粒和碎片。另外，多个半导体管芯部件中的一个或多个可以经由基本平面的表面键合到准备好的键合表面。
在第三实施方案中，可以通过蚀刻多个半导体管芯部件的边缘来移除材料的颗粒和碎片。当多个半导体管芯部件在切割载体(诸如划片片、划片带等)上时，多个半导体管芯部件的边缘可以被蚀刻。另外，多个半导体管芯部件的边缘可以使用化学蚀刻剂蚀刻。在实施方式中，化学蚀刻剂可以包括氢氟酸和硝酸，其具有苯并三唑(BTA)或抑制铜在蚀刻剂中溶解的其他化学品。此外，多个半导体管芯部件的边缘可以使用等离子体蚀刻来蚀刻。另外，多个半导体管芯部件的边缘可以被蚀刻以减小多个半导体管芯部件的厚度，使得在多个半导体管芯部件中的每一个的一个或多个边缘处产生空间。半导体管芯部件可以包括作为基本平面的表面的氧化物层，并且蚀刻可以包括移除在多个半导体管芯部件的边缘处的氧化物层的至少一部分。多个半导体管芯部件的基本平面的表面仍然可以被蚀刻。基本平面的表面可以被蚀刻到预选深度或蚀刻达预选持续时间。
在第四实施方案中，在蚀刻之前，可以将保护涂层施加到多个半导体管芯部件的基本平面的表面，以保护基本平面的表面免受蚀刻剂的影响。
在第五实施方案中，可以在分割后加热多个半导体管芯部件，以使保护涂层从多个半导体管芯部件的外围后退。另外，多个半导体管芯部件的外围可以被蚀刻到预选深度。此外，多个半导体管芯部件可以包括在基础半导体层上方的电介质层。另外，多个半导体管芯部件的外围可以被蚀刻，以移除电介质层并暴露在多个半导体管芯部件的外围处的基础半导体层。
在第六实施方案中，多个半导体管芯部件中的一个或多个可以通过没有粘合剂的直接键合技术或者金属对金属扩散键合来键合。
在第七实施方案中，可以从多个半导体管芯部件的侧壁移除材料的颗粒和碎片，其中通过蚀刻多个半导体管芯部件的侧壁来从侧壁移除颗粒和碎片。
在一个实施方案中，在分割步骤之后，可以通过在一种或多种碱性流体中的超声波或兆频超声波辐射从管芯的侧壁移除材料的颗粒和碎片。在颗粒移除之后，可以进一步蚀刻管芯的侧壁，以移除管芯的侧壁的部分和平面电介质层的部分。
一些公开的过程可以使用方框流程图来示出，包括图形流程图和/或文本流程图。描述所公开的过程的顺序不旨在被解释为限制，并且可以以任何顺序组合任何数量的所描述的过程框以实现该过程或另选过程。另外，在不脱离本文描述的主题的实质和范围的情况下，可以从这些过程中删除各个框。此外，在不脱离本文描述的主题的范围的情况下，所公开的过程可以在任何合适的制造或加工设备或系统中连同任何硬件、软件、固件或它们的组合一起实现。
下面使用多个示例更详细地解释具体实施。尽管在此处和下文讨论了各种具体实施和示例，但是通过组合各个具体实施和示例的特征和元素，其他具体实施和示例也是可能的。
具体实施方式
概述
可以使用各种实施方案和技术来加工准备用于键合的分割的管芯。这些实施方案包括补救在管芯上发现的颗粒累积(包括在管芯的分割期间产生的颗粒)的技术，并且包括移除、溶解或蚀刻在管芯的边缘处的碎片以提供平滑的键合表面。
图1(A)是显示根据实施方案的管芯的顶表面上的缺陷的剖面图。如图所示，第一管芯102被示出为没有任何缺陷。相比之下，第二管芯104被示出为具有缺陷106。当然，应当理解，缺陷106可以出现在第一管芯102和/或第二管芯104的任何表面、侧壁和/或边缘上。
第一管芯102和/或第二管芯104可以从晶圆、电路板、封装、内插器、具有或不具有嵌入金属层的结构、导电互连108、一个或多个器件等上分割和/或移除，所述晶圆为诸如GaAs、金刚石涂覆衬底、碳化硅、氧化硅、氮化硅、硅晶圆、铌酸锂、钽酸锂、平板、玻璃、陶瓷。在一个实施方案中，缺陷106可以包括颗粒和/或碎片，并且可以通过管芯切割、划片和/或分割第一管芯102和/或第二管芯104而产生。例如，第一管芯102和/或第二管芯104的机械切割(即锯切)可能导致诸如颗粒106的缺陷，特别是在边缘和/或侧壁处。另外，当第一管芯102和/或第二管芯104被切割时(甚至使用激光)，第一管芯102和/或第二管芯104可能破裂和/或产生颗粒106(诸如氧化硅颗粒)。此外，在抛光第一管芯102和/或第二管芯104之后，颗粒106的碎片可能仍然存在于第一管芯102和/或第二管芯104的边缘和/或侧壁上。
图1(B)是显示具有诸如颗粒106的缺陷的键合管芯的截面的剖面图。如图所示，在缺陷106存在于第二管芯104的键合表面的一部分上的情况下，第一管芯102不能完全键合到第二管芯104。这由第一管芯102和第二管芯104之间发现的间隙110(或空隙)示出。如果键合的完整性受到损害，或者如果间隙110大到足以负面影响在管芯102和104的键合表面处的匹配电互连108(如果存在)的导电性，则该间隙110可能是不可容忍的。如上所述，尽管缺陷106可能在第二管芯104的键合表面上发现，但是可以沿着第一管芯102和/或第二管芯104的另一表面和/或侧壁发现附加的或其他的缺陷(诸如颗粒)。
图1(C)是显示没有缺陷的紧密键合管芯的截面的剖面图。如图所示，第一管芯102完全和完整地键合到第二管芯104。在管芯102和104的表面处的任何导电互连108也被键合，在互连108之间具有可靠的导电性。图1(C)显示了在各自已经被适当地准备以用于键合之后的第一管芯102和第二管芯104。例如，第一管芯102和/或第二管芯104的边缘和侧壁可以被清洁和蚀刻，以移除硅的颗粒和碎片。当第一管芯102和/或第二管芯104在分割之后仍然在载体(例如，划片片或带、夹环等)上时，可以用干(等离子体)蚀刻和/或湿(化学)蚀刻来蚀刻第一管芯102和/或第二管芯104的边缘。保护涂层可以施加到第一管芯102和/或第二管芯104的键合表面，以在分割和蚀刻期间保护该表面。在一个示例中，第一管芯102和/或第二管芯104的表面和侧壁可以被蚀刻，而在另一个示例中，蚀刻可以限于第一管芯102和/或第二管芯104的侧壁。应注意，互连108被简单地而不是按比例示出。例如，互连108可以包括一起形成互连108的一个或多个层。此外，互连108可以部分或完全延伸穿过管芯102和104中的一个或两个，或者甚至可以仅在管芯102和104的表面处或沿着管芯102和104的表面提供，作为管芯102和104内的互连器件的迹线图案。
示例性实施方案
图2示出了根据实施方案的加工堆叠管芯的示例性过程200。在(A)中，衬底202(可以是例如硅晶圆)可以包括键合层204，键合层204可以包括诸如氧化物的绝缘体或电介质层，或者混合键合层，例如绝缘材料(诸如氧化物)和导电互连层的组合。该键合层204可以形成在衬底202的一侧或两侧上。层204可以由第一保护层206和/或第二保护层208保护。另选地，衬底202可以暴露和/或具有任意数量的保护层。
在(B)中，衬底202可以在载体212上被分割成多个分割的管芯210。在一个实施方案中，载体212可以包括加工片、划片片或带、夹环等。另外，衬底202可以使用锯划片、湿蚀刻或干蚀刻或激光方法或其组合来分割。在一个实施方案中，分割的管芯210可以具有基本平面的表面。
在(C)中，分割的管芯210可以暴露于紫外光(UV)(例如，以固化在用作衬底202的载体212的带上的粘合剂层，以减少管芯210与接触带的表面之间的粘合力等)。另外，在一个实施方案中，载体212可以在分割的管芯210在载体212上时被拉伸，以准备清洁和进一步加工分割的管芯210。例如，进一步的加工可以包括减小分割的管芯210的厚度。
在(D)中，分割的管芯210可以被清洁，并且分割的管芯210的侧壁可以被蚀刻。例如，清洁可以移除一个或多个保护层，包括保护层206和/或保护层208。在实施方案中，蚀刻可以溶解氧化硅、氮化硅和/或硅，以消除颗粒和/或碎片。包括酸在内的化学蚀刻剂211可以用于蚀刻管芯210的表面的外围，包括键合层204，并且也可以用于蚀刻分割的管芯210的侧壁。在分割的管芯210的表面和/或侧壁被蚀刻的示例中(例如，对于硅管芯210)，蚀刻剂211可以包括氢氟酸和合适氧化剂(例如硝酸)的化学混合物。在一些应用中，湿蚀刻剂可以由缓冲氢氟酸和合适有机酸的混合物与氧化剂结合构成。在其他应用中，可以将合适的金属络合剂添加到蚀刻溶液中，以保护管芯210键合表面上的金属免受蚀刻剂的影响。在一个示例中，金属络合剂或钝化剂可以由具有三唑部分的分子构成，例如苯并三唑(BTA)等。在一个实施方案中，BTA可以保护分割的管芯210的表面上的铜免受蚀刻溶液的腐蚀或溶解。
在蚀刻管芯210的表面(和侧壁)并剥离保护层206和/或208之后，络合剂从管芯210的键合表面上被清除。作为湿蚀刻的替代，也可以使用干蚀刻方法清洁管芯210的侧壁，包括使用与蚀刻硅中使用的过程类似的等离子体加工。在干侧壁蚀刻步骤之后，保护层206可以从管芯210的侧壁的键合表面被剥离。清洁保护层206还可以包括清洁由干蚀刻产生的任何有机材料残留物。在一个实施方案中，经加工的管芯210的侧壁上的有机残留物可以完整保留。强粘附的侧壁有机残留物可以最小化来自管芯210的后续颗粒脱落。
另外，分割的管芯210的清洁和/或进一步加工可以发生在旋转夹具214(或类似物)上。化学蚀刻剂211被喷射到划片的晶圆表面上，并在管芯210的顶表面上方形成薄层，并填充管芯210之间的间隙。在一个实施方案中，蚀刻分割的管芯210的侧壁可以导致管芯210的侧壁上的缺陷被移除。
任选地，在实施方案中，管芯210的侧壁可以被选择性地涂覆，以涂覆到侧壁和可能存在于侧壁上的任何颗粒和/或碎片。例如，可以使用旋涂工艺、电涂工艺等将选择性涂层218施加到侧壁上。用涂层218将颗粒和/或碎片涂覆到侧壁，以将颗粒和/或碎片粘附到侧壁，防止颗粒和/或碎片污染管芯210的其他区域，包括管芯210的键合表面。在各种实施方案中，涂层218包括诸如玻璃、掺硼玻璃、掺磷玻璃等的材料，其粘附到侧壁的硅上，并且通常不会粘附到任何其他表面上。
在各种实施方案中，涂层218包括大约50nm或更小的层，该层将颗粒和碎片捕获到管芯210的侧壁，并防止它们从侧壁脱落。涂层218可以在预定温度(例如，大约80℃等)下热固化到管芯210以稳定预定的持续时间。虽然涂层218可以如所讨论的那样在清洁管芯210之后添加，但是在各种实施方案中，涂层218可以在过程200中的其他步骤沉积到侧壁上。
在(E)中，分割的管芯210可以经历等离子体工艺(诸如灰化)，以移除保护层206的任何残留物。在(F)中，分割的管芯210可以被清洁，以移除由步骤(E)产生的任何残留物或碎屑的颗粒。在(G)中，分割的管芯210(包括氧化物层204中的一个或两个)可以被等离子体激活(表面激活)，以准备分割的管芯210用于直接键合。在(H)中，等离子体激活的分割的管芯210可以被清洁。在(I)中，一个或多个分割的管芯210可以键合到第二衬底216的准备好的表面。特别地，分割的管芯210的键合层204(例如，具有或不具有导电层的氧化物或电介质层)可以直接键合到第二衬底216的准备好的表面。在一个实施方案中，分割的管芯210(经由键合层204)可以使用直接键合或混合键合技术等键合到第二衬底216，其中分割的管芯210直接键合(并且在一些情况下电连接)到第二衬底216的表面的部分，而不使用粘合剂。
在各种实施方式中，衬底216可以包括硅晶圆、GaAs、金刚石涂覆衬底、碳化硅、氧化硅、氮化硅、铌酸锂、钽酸锂、平板、玻璃、陶瓷、电路板、封装、内插器、具有或不具有一个或多个嵌入式器件的结构等的另一个准备好的表面。在一个实施方案中，准备好的衬底216包括另一个管芯210或另一个键合管芯304的表面，如下面进一步讨论的。
图3示出了根据实施方案的加工堆叠管芯的示例性过程300。如上所述，过程300的步骤(A)-(D)以与过程200的步骤(A)-(D)一致的方式起作用。这包括蚀刻管芯210的表面和外围(在相同或单独的过程步骤中)，以从管芯210的表面和外围移除硅或氧化物的颗粒和碎片。
任选地，在实施方案中，管芯210的侧壁可以被选择性地涂覆，以涂覆到侧壁和可能存在于侧壁上的任何颗粒和/或碎片，如上所述。例如，可以使用旋涂工艺、电涂工艺等将选择性涂层218施加到侧壁上。用涂层218将颗粒和/或碎片涂覆到侧壁，以将颗粒和/或碎片粘附到侧壁，防止颗粒和/或碎片污染管芯210的其他区域，包括管芯210的键合表面。在各种实施方案中，涂层218包括诸如玻璃、掺硼玻璃、掺磷玻璃等的材料，其粘附到侧壁的硅上，并且通常不会粘附到任何其他表面上。
在各种实施方案中，涂层218包括大约50nm或更小的层，该层将颗粒和碎片捕获到管芯210的侧壁，并防止它们从侧壁脱落。涂层218可以在预定温度(例如，大约80℃等)下热固化到管芯210以稳定预定的持续时间。虽然涂层218可以如所讨论的那样在清洁管芯210之后添加，但是在各种实施方案中，涂层218可以在过程300中的其他步骤沉积到侧壁上。
继续参考过程300，在(E)中，对于所有描述的过程步骤(在一些实施方案中，包括分割)，分割的管芯210可以被转移到旋转夹具214(或类似物)，并且在诸如旋转板214或类似物的单个载体上进行加工/清洁。另选地，对于每个工位处的一个或多个过程，分割的管芯210可以在不同的载体(诸如旋转板302)之间转移。在(F)中，当仍然在旋转板302上时，分割的管芯210可以经受等离子体处理以移除保护层206的任何残留物(以与过程200的步骤(E)相似的方式)。
在(G)中，分割的管芯210可以被清洁，以移除由(F)中的等离子体工艺产生的残留物。在(H)中，分割的管芯210可以被等离子体激活(表面激活)，以准备分割的管芯210(包括键合层204)用于直接键合。在(I)中，等离子体激活的分割的管芯210可以被清洁。
在(J)中，一个或多个分割的管芯210可以键合到第二衬底216的准备好的表面。特别地，键合层204(例如，具有或不具有导电层的氧化物或电介质层)可以键合到第二衬底216的准备好的表面。在一个实施方案中，分割的管芯210(经由氧化物层204)可以使用直接键合或混合键合技术等(例如，没有粘合剂或居间层)直接键合到第二衬底216。
在(K)中，一个或多个类似于分割的管芯210准备的附加的分割的管芯304(例如，管芯304也可以从衬底202分割)可以键合到一个或多个分割的管芯210的暴露的第二表面，形成一个或多个管芯叠层。特别地，分割的管芯304的键合层306(例如，具有或不具有导电层的氧化物或电介质层)可以直接键合到分割的管芯210的第二表面，该第二表面也已经准备好用于键合。根据需要，键合的准备可以包括一个或多个清洁、表面平坦化和等离子体处理过程步骤。另外，管芯210的第二表面(包括外围)也可以被蚀刻以移除不期望的颗粒和碎片等。
附加的分割的管芯304可以以类似的方式添加，以形成具有期望数量的管芯层的管芯叠堆。在一些实施方案中，分割的管芯210和第二衬底216可以在键合之后被热处理，在添加每层分割的管芯304之后进行附加的热处理。另选地，一旦堆叠管芯(210,304)的几层或所有层就位并被键合，分割的管芯210、分割的管芯304和第二衬底216就被热处理。
图4示出了根据实施方案的加工堆叠管芯的另一个示例性过程400。在(A)中，抗蚀剂层402被涂覆在分割的管芯210上，管芯210包括键合层204(例如，具有或不具有导电层或结构的绝缘或电介质层)和衬底区域202(例如，硅)。在实施方式中，抗蚀剂层402可以被图案化，例如以暴露分割的管芯210的外围，同时保护分割的管芯210的其余表面。在各种实施方案中，分割的管芯210可以使用划片和/或划线来分割。
在(B)中，分割的管芯210的暴露边缘和侧壁可以被清洁和蚀刻，在分割的管芯210的外围处产生底切或凹部。例如，分割的管芯210的粗切边缘可以通过蚀刻变得平滑。另外，分割的管芯210的外围可以凹进，以在外围处具有分割的管芯210的减小的总厚度，从而在分割的管芯210的边缘处产生空间。例如，在衬底202(例如硅)上具有键合层204(例如，电介质、氧化物等)的分割的管芯210可以被蚀刻以移除在分割的管芯210的外围处的键合层204的一些氧化物，并且在一些情况下，也移除衬底202的部分硅。蚀刻导致键合层204的电介质氧化物从分割的管芯210的边缘向后凹进，暴露凹部下面的衬底202的硅。在一个实施方案中，由凹部形成的空间可以允许在直接键合期间对键合表面有一些容差，以提高直接键合技术的可靠性并从键合中移除应力。
在一个实施方案中，分割的管芯210可以在升高的温度(例如，120℃)下加工，使得设置在氧化物层204上的抗蚀剂层402流动并从分割的管芯210的边缘拉回。当分割的管芯210的边缘被蚀刻时，氧化物层204的暴露部分可以被移除。另外，根据蚀刻所用的持续时间和配方，可以额外地移除衬底202的一些硅。例如，持续时间越长，可以移除的衬底202的量越大。在一些情况下，由于分割的管芯210的蚀刻，电介质氧化物层204可以具有倾斜的轮廓。如果蚀刻进行到衬底202的深度，该倾斜轮廓可以延伸到衬底202(例如硅)中。
在一些实施方案中，根据需要，回蚀刻电介质层204的过程可以使用光刻方法结合干蚀刻、湿蚀刻或两者来执行。例如，管芯210的表面可以被图案化，并且电介质层204的不需要的部分可以通过干蚀刻方法移除，并且任何不需要的暴露导电特征可以例如通过湿蚀刻方法移除。在其他应用中，可能优选的是在一次操作中移除不需要的电介质和导电部分。在一个示例中，可以将包含卤化物离子的湿蚀刻剂(例如，可氧化导电特征的缓冲氢氟酸和包含过氧化氢或硝酸(或类似物)的配方)施加到管芯210的表面，以移除不需要的电介质和导电特征。在移除不需要的电介质和导电特征之后，可以施加保护层以用于分割操作。
在(C)中，抗蚀剂层402可以从分割的管芯210的表面移除。另外，在(D)中，分割的管芯210可以被清洁。
在(E)和(F)中，分割的管芯210可以键合到第二衬底404(诸如，另一管芯210或304、第二衬底216等)，该第二衬底404已经被准备用于键合，如上所述。在一个实施方案中，可以使用或混合技术等(例如，没有粘合剂或居间层)将分割的管芯210键合到衬底404的准备好的表面。在图4的图示中，在(E)和(F)中，仅管芯210被示出为具有氧化物层204。然而，在一些实施方案中，待键合的两个部件(例如，管芯210、管芯304或衬底216)可以包括在键合表面处的氧化物区域(诸如，氧化物层204)。换句话说，部件在相应的氧化物区域处键合。在一些应用中，管芯210的电介质或氧化物层204和衬底202的准备好的表面可以包括导电特征(未示出)。管芯210和衬底202的准备好的表面的电介质部分可以在较低的温度下初始键合。任何导电特征都可以在150到350℃之间的较高温度下接合。在其他应用中，电介质部分和导电特征键合在相同的温度下形成。
在(E)中所示的实施方式中，由于步骤(D)的蚀刻，分割的管芯210的氧化物层204的边缘可以包括底切408。在该实施方式中，分割的管芯210可以包括在分割的管芯210的外围处的底切408，使得氧化物层204的面积小于衬底202和/或衬底404的覆盖区的面积。另外或另选地，在(F)中所示的实施方式中，由于步骤(D)的蚀刻，衬底202和衬底404的边缘可以包括底切410。在该实施方式中，分割的管芯210可以包括在分割的管芯210的外围处的底切410，使得氧化物层204的面积大于衬底202和/或衬底404的覆盖区的面积。在该实施方式中，衬底202和衬底404可以分别对应于第一键合微电子部件和第二键合微电子部件。
根据各种实施方案，本文所述的边缘或侧壁蚀刻技术可以降低用于分割的管芯210的大批量制造的直接键合工艺的复杂性和成本。另外，从分割的管芯210的外围和/或边缘移除划片颗粒和碎片可以减少晶圆对晶圆、管芯对晶圆、管芯对管芯和管芯对系统封装中的工艺相关缺陷。此外，通过使堆叠的分割的管芯210的边缘变圆，可以降低以三维布置堆叠的封装的分割的管芯210中的应力。本文所述技术还可以导致和直接键合互连制造的器件的更少的管芯加工步骤、更高的制造产量和更高的边际利润率。所公开技术的其他优点对于本领域技术人员来说也是显而易见的。
图5(A)是根据实施方案的具有凹进键合层204(例如，具有或不具有导电层的绝缘层或电介质层)的示例性管芯210的一部分的剖面图。另外，图5(B)是具有凹进键合层204(例如，氧化物区域)的管芯210的剖面图的放大图。如图所示，管芯210可以包括从衬底202向后凹进的键合层204。例如，图5(B)的剖面图可以对应于图4的步骤(D)中所示的剖面图。另外，图5(B)在键合层204的一侧上包括凹部，然而，如图4的步骤(D)和图5(C)所示，凹部也可以位于键合层204的两侧(或另一侧)上。
特别地，氧化物层204的倾斜轮廓502可能由于蚀刻而延伸到衬底202中(例如，如参考图4的步骤(D)所述)。另外，倾斜轮廓502可以在衬底202的周边提供间隙，使得即使在衬底202的周边存在任何颗粒的情况下，也可以在例如分割的管芯210和第二衬底216(或类似物)的准备好的表面之间实现紧密的键合。
例如，这在图5(C)中示出，其中示例性管芯210被示出为键合到另一示例性管芯210’，形成示例性管芯叠堆或示例性微电子组件500(或类似物)。如图5(C)的图示中所示，键合层204包括诸如氧化物的绝缘或电介质材料并且还可以包括一个或多个导电层或结构504，并且直接键合到键合层204’，键合层204’也包括诸如氧化物的绝缘或电介质材料，并且也可以包括一个或多个导电层或结构504’。导电特征504和504’可以仅延伸到相应的键合层204和204’中，或者可以部分或全部延伸穿过管芯201和210’。键合层204处的凹部和键合层204’处的凹部(如果存在的话)可以在组件500的外围处形成间隙506，在间隙506处，管芯210键合到管芯210’。在各种实施方案中，间隙506可以具有这样的尺寸，使得保留在间隙506中的任何颗粒508都不会妨碍键合表面204和204’之间形成紧密的键合，包括导电结构504和504’之间紧密且导电的可靠键合。在各种实施方案中，间隙506可以根据需要填充，例如用密封剂、电介质材料、底部填充材料等。在其他实施方案中，间隙506可以保持未填充，或者可以根据需要填充其他惰性或活性材料。可以在管芯210和210’的背面形成如图5(A)和图5(B)所示的类似轮廓，并且可以将多于两个的管芯堆叠在一起。
图6是示出根据实施方案的用于加工堆叠管芯的示例性过程的流程图600。在602，该过程包括从晶圆部件(诸如衬底202)中分割多个半导体管芯部件(诸如，分割的管芯210或分割的管芯304)。在实施方案中，半导体管芯部件中的每一个具有基本平面的表面。在另一个实施方案中，该过程包括在半导体管芯部件的基本平面的表面上方(在分割之前或之后)沉积保护涂层(诸如保护涂层206)。
在一个实施方案中，该过程包括在分割后加热多个半导体管芯部件，以使保护涂层(诸如保护涂层206)从多个半导体管芯部件的外围后退。另外，多个半导体管芯部件的外围和/或多个半导体管芯部件的基本平面的表面可以被蚀刻到预选深度。
另选地，多个半导体管芯部件可以包括基础半导体层上方的电介质层。另外，电介质层可以具有基本平面的表面，并且如上所述，电介质层可以包括一个或多个导电特征。在一个实施方案中，该过程包括蚀刻多个半导体管芯部件的外围，使得电介质层的至少一部分被移除，并且在多个半导体管芯部件的外围处的基础半导体层被暴露。
在604，该过程包括从多个半导体管芯部件的边缘移除材料的颗粒和碎片。另选地，颗粒和碎片可以从多个半导体管芯部件的侧壁移除。在一个实施方案中，颗粒和碎片可以通过蚀刻多个半导体管芯部件的边缘和/或侧壁来移除。任选地，边缘和/或侧壁的蚀刻发生在多个半导体管芯部件在切割载体上时。另外，蚀刻可以使用等离子体蚀刻和/或包含氢氟酸和硝酸以及苯并三唑(BTA)的化学蚀刻剂。在替代实施方式中，保护涂层(诸如保护涂层206)可以被施加到多个半导体管芯部件的基本平面的表面，以保护基本平面的表面免受蚀刻剂的影响。
在606，该过程包括经由基本平面的表面将多个半导体管芯部件中的一个或多个键合到准备好的键合表面。例如，键合可以通过使用或键合技术等的直接键合来进行，而不需要粘合剂或居间层。键合可以包括在管芯的键合表面和准备好的键合表面处电耦接相对的导电特征。
本文所述公开的过程使用方框流程图来示出。描述所公开的过程的顺序不旨在被解释为限制，并且可以以任何顺序组合任何数量的所描述的过程框以实现该过程或另选过程。另外，在不脱离本文描述的主题的实质和范围的情况下，可以从这些过程中删除各个框。此外，在不脱离本文描述的主题的范围的情况下，所公开的过程可以在任何合适的制造或加工设备或系统中连同任何硬件、软件、固件或它们的组合一起实现。
尽管在本文中讨论了各种实施方式和示例，但是通过组合各个实施方式和示例的特征和元素，其他实施方式和示例也是可能的。
结论
尽管已经用结构特征和/或方法动作专用的语言描述了本公开的具体实施，但是应当理解，这些具体实施不必限于所描述的特定特征或动作。相反，公开了特定特征和动作作为实现示例性装置和技术的代表性形式。
本文档的每个权利要求构成单独的实施方案，并且组合不同权利要求和/或不同实施方案的实施方案在本公开的范围内，并且在阅读本公开后对于本领域普通技术人员将是显而易见的。

Claims (31)

1.一种微电子系统，包括：
第一微电子部件，所述第一微电子部件至少由基础半导体层和电介质层构成，所述电介质层具有基本平面的表面；和
第二微电子部件，所述第二微电子部件在没有粘合剂的情况下直接键合到所述第一微电子部件的所述电介质层，所述电介质层在所述电介质层的外围处具有底切，使得所述电介质层的面积小于所述第一微电子部件和/或所述第二微电子部件的覆盖区的面积。
2.根据权利要求1所述的微电子系统，其中，所述第一微电子部件的所述基础半导体层在所述基础半导体层的外围处具有底切，所述底切对应于在所述第一微电子部件的所述电介质层的所述外围处的所述底切。
3.根据权利要求1所述的微电子系统，其中，所述第二微电子部件至少由基础半导体层和具有基本平面的表面的电介质层构成，所述第一微电子部件的所述电介质层直接键合到所述第二微电子部件的所述电介质层，并且所述第二微电子部件的所述电介质层在所述第二微电子部件的所述电介质层的外围处具有底切，使得所述第二微电子部件的所述电介质层的面积小于所述第一微电子部件和/或所述第二微电子部件的所述覆盖区的所述面积。
4.根据权利要求3所述的微电子系统，其中，在所述第一微电子部件和/或所述第二微电子部件的所述基础半导体层的外围处的底切对应于在所述第一微电子部件和/或所述第二微电子部件的所述电介质层的所述外围处的底切。
5.一种微电子系统，包括：
第一微电子部件，所述第一微电子部件至少由第一基础半导体层和第一电介质层构成，所述第一电介质层具有第一基本平面的表面；和
第二微电子部件，所述第二微电子部件至少由第二基础半导体层和第二电介质层构成，所述第二电介质层具有第二基本平面的表面，所述第二电介质层在所述第一基本平面的表面和所述第二基本平面的表面处在没有粘合剂的情况下直接键合到所述第一电介质层，所述第一基础半导体层和所述第二基础半导体层分别在所述第一基础半导体层和所述第二基础半导体层的外围处具有底切，使得所述第一基础半导体层的覆盖区的面积和所述第二基础半导体层的覆盖区的面积小于所述第一电介质层和/或所述第二电介质层的面积。
6.根据权利要求5所述的微电子系统，其中，所述底切对应于在所述第一微电子部件和/或所述第二微电子部件的所述第一电介质层和/或所述第二电介质层的所述外围处的底切。
7.一种用于形成微电子系统的方法，包括：
从晶圆部件分割多个半导体管芯部件，所述半导体管芯部件各自具有基本平面的表面；
从所述多个半导体管芯部件的边缘移除材料的颗粒和碎片；以及
经由所述基本平面的表面将所述多个半导体管芯部件中的一个或多个键合到准备好的键合表面。
8.根据权利要求7所述的用于形成微电子系统的方法，还包括蚀刻所述多个半导体管芯部件的所述边缘，以从所述多个半导体管芯部件的所述边缘移除所述颗粒和所述碎片。
9.根据权利要求8所述的用于形成微电子系统的方法，还包括当所述多个半导体管芯部件在划片载体上时蚀刻所述多个半导体管芯部件的所述边缘。
10.根据权利要求8所述的用于形成微电子系统的方法，还包括使用化学蚀刻剂蚀刻所述多个半导体管芯部件的所述边缘，所述化学蚀刻剂包括氢氟酸和硝酸以及苯并三唑(BTA)。
11.根据权利要求8所述的用于形成微电子系统的方法，还包括使用等离子体蚀刻来蚀刻所述多个半导体管芯部件的所述边缘。
12.根据权利要求8所述的用于形成微电子系统的方法，还包括蚀刻所述多个半导体管芯部件的所述边缘，以减小所述多个半导体管芯部件的厚度，使得在所述多个半导体管芯部件中的每一个的一个或多个所述边缘处产生空间。
13.根据权利要求8所述的用于形成微电子系统的方法，其中，所述半导体管芯部件包括作为所述基本平面的表面的氧化物层，并且其中，所述蚀刻包括移除在所述多个半导体管芯部件的所述边缘处的所述氧化物层的至少一部分。
14.根据权利要求8所述的用于形成微电子系统的方法，还包括在所述蚀刻之前将保护涂层施加到所述多个半导体管芯部件的所述基本平面的表面，以保护所述基本平面的表面免受蚀刻剂的影响。
15.根据权利要求14所述的用于形成微电子系统的方法，还包括：
在分割后加热所述多个半导体管芯部件，以使所述保护涂层从所述多个半导体管芯部件的外围后退；以及
将所述多个半导体管芯部件的所述外围蚀刻到预选深度。
16.根据权利要求15所述的用于形成微电子系统的方法，其中，所述多个半导体管芯部件包括在基础半导体层上方的电介质层，其中，所述蚀刻所述多个半导体管芯部件的所述外围包括在所述多个半导体管芯部件的所述外围处移除所述电介质层并暴露所述基础半导体层。
17.根据权利要求7所述的用于形成微电子系统的方法，还包括蚀刻所述多个半导体管芯部件的所述基本平面的表面。
18.根据权利要求17所述的用于形成微电子系统的方法，还包括将所述基本平面的表面蚀刻到预选深度或蚀刻达预选持续时间。
19.根据权利要求7所述的用于形成微电子系统的方法，其中，所述多个半导体管芯部件中的所述一个或多个使用没有粘合剂的直接键合技术或者金属对金属扩散键合来键合。
20.根据权利要求7所述的用于形成微电子系统的方法，还包括从所述多个半导体管芯部件的侧壁移除材料的颗粒和碎片，其中，通过蚀刻所述多个半导体管芯部件的所述侧壁来从所述侧壁移除所述颗粒和所述碎片。
21.根据权利要求7所述的用于形成微电子系统的方法，还包括将材料的颗粒和碎片涂覆到所述多个半导体管芯部件的侧壁，其中，通过在所述多个半导体管芯部件的所述侧壁上沉积涂层将所述颗粒和所述碎片涂覆到所述侧壁。
22.根据权利要求21所述的用于形成微电子系统的方法，还包括用玻璃、掺硼玻璃或掺磷玻璃旋涂或电涂所述多个半导体管芯部件的所述侧壁。
23.根据权利要求22所述的用于形成微电子系统的方法，还包括将所述玻璃、所述掺硼玻璃或所述掺磷玻璃热固化到所述多个半导体管芯部件的所述侧壁。
24.一种器具，包括：
第一微电子部件，所述第一微电子部件至少由电介质层构成，所述电介质层具有基本平面的表面；和
第二微电子部件，所述第二微电子部件在没有粘合剂的情况下直接键合到所述第一微电子部件的所述电介质层，所述电介质层在所述第一微电子部件的外围处具有底切，使得所述电介质层的面积小于所述第一微电子部件和/或所述第二微电子部件的覆盖区的面积。
25.根据权利要求21所述的器具，其中，所述第一微电子部件或所述第二微电子部件包括直接带隙半导体或间接带隙半导体。
26.一种器具，包括：
第一部件，所述第一部件至少由平面电介质层构成；
第二部件，所述第二部件在没有粘合剂的情况下直接键合到所述第一部件的所述电介质层，所述电介质层在所述第一部件的外围处具有底切。
27.根据权利要求26所述的器具，其中，所述第一部件或所述第二部件包括直接带隙半导体或间接带隙半导体。
28.根据权利要求26所述的器具，其中，所述第一部件或所述第二部件包括非半导体材料。
29.根据权利要求26所述的器具，其中，所述第一部件和所述第二部件包括微电子管芯。
30.一种用于形成器具的方法，包括：
将具有基本平面的表面的微电子部件分割成多个子部件；
从所述子部件的边缘移除材料的颗粒和碎片；以及
将所述子部件中的一个或多个键合到具有基本平面的表面的准备好的键合表面。
31.一种器具，包括：
第一部件，所述第一部件至少由平面电介质层构成；
第二部件，所述第二部件在没有粘合剂的情况下直接键合到所述第一部件的所述电介质层，使得所述电介质层的面积小于所述第一微电子部件和/或所述第二微电子部件的覆盖区的面积。
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