JP7129427B2 - 処理された積層ダイ - Google Patents
処理された積層ダイ Download PDFInfo
- Publication number
- JP7129427B2 JP7129427B2 JP2019562412A JP2019562412A JP7129427B2 JP 7129427 B2 JP7129427 B2 JP 7129427B2 JP 2019562412 A JP2019562412 A JP 2019562412A JP 2019562412 A JP2019562412 A JP 2019562412A JP 7129427 B2 JP7129427 B2 JP 7129427B2
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- JP
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- Prior art keywords
- semiconductor die
- die
- die components
- forming
- layer
- Prior art date
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Description
本出願は、2018年4月23日に出願された米国特許出願第15/960,179号、及び2017年5月11日に出願された米国特許仮出願第62/504,834号の米国特許法第119条(e)(1)の利益を主張するものであり、その全体が参照により本明細書に組み込まれる。
以下の説明は、集積回路(integrated circuit、「IC」)の処理に関する。より具体的には、以下の説明は、接合の準備において個片化されたダイを処理するための技術に関する。
この説明では、図に図示されるデバイス及びシステムは、多数の構成要素を有するものとして示されている。本明細書に記載されるようなデバイス及び/又はシステムの様々な実装形態は、より少ない構成要素を含んでもよく、本開示の範囲内にとどまり得る。あるいは、デバイス及び/又はシステムの他の実装形態は、追加の構成要素、又は記載された構成要素の様々な組み合わせを含んでもよく、本開示の範囲内にとどまる。
実施形態例
結論
Claims (20)
- 超小型電子システムを形成するための方法であって、
ウェハ構成要素から複数の半導体ダイ構成要素を個片化することであって、前記半導体ダイ構成要素が各々、実質的に平坦な表面を有する、個片化することと、
前記複数の半導体ダイ構成要素の縁部から材料の粒子及び破片を除去することと、
前記複数の半導体ダイ構成要素の前記実質的に平坦な表面の周辺部を、事前選択された深さ又は事前選択された持続時間にエッチングすることと、
前記エッチングの前、かつ、前記個片化の後に前記複数の半導体ダイ構成要素を加熱して、前記複数の半導体ダイ構成要素の前記実質的に平坦な表面上の保護コーティングを、前記複数の半導体ダイ構成要素の前記周辺部から後退させることと、
前記複数の半導体ダイ構成要素のうちの1つ以上を、前記実質的に平坦な表面を介して、準備された接合表面に接合することと、を含む、方法。 - 前記複数の半導体ダイ構成要素の前記周辺部を前記エッチングすることにより、前記複数の半導体ダイ構成要素の前記縁部から前記粒子及び破片を除去する、請求項1に記載の超小型電子システムを形成するための方法。
- 前記複数の半導体ダイ構成要素がダイシングキャリア上にある間に、前記複数の半導体ダイ構成要素の前記縁部をエッチングすることを更に含む、請求項2に記載の超小型電子システムを形成するための方法。
- ベンゾトリアゾール(BTA)と共にフッ化水素酸及び硝酸を含む化学エッチング液を使用して、前記複数の半導体ダイ構成要素の前記縁部をエッチングすることを更に含む、請求項2に記載の超小型電子システムを形成するための方法。
- プラズマエッチングを使用して、前記複数の半導体ダイ構成要素の前記縁部をエッチングすることを更に含む、請求項2に記載の超小型電子システムを形成するための方法。
- 前記複数の半導体ダイ構成要素の各々の前記縁部のうちの1つ以上において空間が創られるように、前記複数の半導体ダイ構成要素の前記縁部をエッチングして前記複数の半導体ダイ構成要素の厚さを低減することを更に含む、請求項2に記載の超小型電子システムを形成するための方法。
- 前記半導体ダイ構成要素が、前記実質的に平坦な表面として酸化物層を含み、前記エッチングすることが、前記複数の半導体ダイ構成要素の前記縁部において前記酸化物層の少なくとも一部分を除去することを含む、請求項2に記載の超小型電子システムを形成するための方法。
- 前記エッチングの前に、前記複数の半導体ダイ構成要素の前記実質的に平坦な表面に前記保護コーティングを塗布して、前記実質的に平坦な表面をエッチング液から保護することを更に含む、請求項2に記載の超小型電子システムを形成するための方法。
- 前記複数の半導体ダイ構成要素が、ベース半導体層の上に誘電体層を含み、前記複数の半導体ダイ構成要素の前記周辺部を前記エッチングすることが、前記誘電体層を除去することと、前記複数の半導体ダイ構成要素の前記周辺部に前記ベース半導体層を露出させることと、を含む、請求項1に記載の超小型電子システムを形成するための方法。
- さらに、前記複数の半導体ダイ構成要素の前記周辺部において前記誘電体層に加えて前記複数の半導体ダイ構成要素の一部を除去することを含む、請求項9に記載の超小型電子システムを形成するための方法。
- さらに、前記ベース半導体層の面積が前記誘電体層の占有面積よりも小さいように、前記ベース半導体層の周辺部においてアンダーカットを形成することを含む、請求項10に記載の超小型電子システムを形成するための方法。
- さらに、前記準備された接合表面の面積が前記誘電体層の占有面積よりも小さいように、前記準備された接合表面の周辺部においてアンダーカットを形成することを含む、請求項11に記載の超小型電子システムを形成するための方法。
- さらに、前記誘電体層の面積が前記ベース半導体層の占有面積よりも小さいように、前記誘電体層の周辺部においてアンダーカットを形成することを含む、請求項9に記載の超小型電子システムを形成するための方法。
- 前記保護コーティングは、前記複数の半導体ダイ構成要素の少なくとも前記周辺部を露出させるようにパターン化されたレジスト層を備える、請求項1に記載の超小型電子システムを形成するための方法。
- 前記複数の半導体ダイ構成要素のうちの前記1つ以上が、接着剤を用いない直接接合技術又は金属間拡散接合のいずれかを使用して接合される、請求項1に記載の超小型電子システムを形成するための方法。
- 前記複数の半導体ダイ構成要素の側壁から材料の粒子及び破片を除去することを更に含み、前記粒子及び破片が、前記複数の半導体ダイ構成要素の前記側壁をエッチングすることによって、前記側壁から除去される、請求項1に記載の超小型電子システムを形成するための方法。
- 前記複数の半導体ダイ構成要素の側壁に材料の粒子及び破片をコーティングすることを更に含み、前記粒子及び破片が、前記複数の半導体ダイ構成要素の前記側壁上にコーティング層を堆積させることによって、前記側壁にコーティングされる、請求項1に記載の超小型電子システムを形成するための方法。
- 前記複数の半導体ダイ構成要素の前記側壁を、ガラス、ホウ素ドープガラス、又はリンドープガラスでスピンコーティング又はエレクトロコーティングすることを更に含む、請求項17に記載の超小型電子システムを形成するための方法。
- 前記複数の半導体ダイ構成要素の前記側壁に、前記ガラス、前記ホウ素ドープガラス、又は前記リンドープガラスを、熱硬化することを更に含む、請求項18に記載の超小型電子システムを形成するための方法。
- 超小型電子システムを形成するための方法であって、
ウェハ構成要素から複数の半導体ダイ構成要素を個片化することであって、前記半導体ダイ構成要素が各々、ベース半導体層の上に誘電体層を含むと共に、実質的に平坦な表面を有する、個片化することと、
前記複数の半導体ダイ構成要素の周辺部を、事前選択された深さ又は事前選択された持続時間にエッチングすることであって、前記複数の半導体ダイ構成要素の前記周辺部において前記誘電体層の少なくとも一部を除去することを含む前記エッチングすることと、
前記誘電体層の面積が前記ベース半導体層の専有面積よりも小さくなるように、前記誘電体層の周辺部にアンダーカットを形成することと、
前記複数の半導体ダイ構成要素のうちの1つ以上を、前記実質的に平坦な表面を介して、準備された接合表面に接合することと、を含む、方法。
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CN110574151A (zh) | 2019-12-13 |
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KR102320674B1 (ko) | 2021-11-01 |
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EP3635775A1 (en) | 2020-04-15 |
TWI749220B (zh) | 2021-12-11 |
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CN110574151B (zh) | 2023-12-15 |
US20180331066A1 (en) | 2018-11-15 |
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TW201907505A (zh) | 2019-02-16 |
US10879212B2 (en) | 2020-12-29 |
TW202209560A (zh) | 2022-03-01 |
EP3635775A4 (en) | 2021-05-26 |
US20230282610A1 (en) | 2023-09-07 |
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