CN104600023A - 半导体集成电路制造的方法 - Google Patents

半导体集成电路制造的方法 Download PDF

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Publication number
CN104600023A
CN104600023A CN201410373394.5A CN201410373394A CN104600023A CN 104600023 A CN104600023 A CN 104600023A CN 201410373394 A CN201410373394 A CN 201410373394A CN 104600023 A CN104600023 A CN 104600023A
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Prior art keywords
conductive component
dielectric layer
metal plug
layer
opening
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CN201410373394.5A
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CN104600023B (zh
Inventor
谢铭峰
曾文弘
谢弘璋
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开了一种制造半导体集成电路(IC)的方法。提供了第一导电部件和第二导电部件。在第一导电部件上形成第一硬掩模(HM)。在第一和第二导电部件上方形成图案化的介电层，第一开口暴露第二导电部件。在第一开口中形成第一金属插塞以与第一导电部件接触。在第一金属插塞上形成第二HM，并且在衬底上方形成另一个图案化的介电层，第二开口暴露出第一金属插塞与第一导电部件的子集。在第二开口中形成第二金属插塞。

Description

半导体集成电路制造的方法
技术领域
本发明总体涉及半导体集成电路，更具体地，涉及半导体集成电路的制造方法。
背景技术
半导体集成电路(IC)工业已然经历了快速发展。IC设计和材料的技术进步产生了数代IC，其中，每一代都比前一代具有更小且更复杂的电路。在IC演进的过程中，在几何尺寸(即，可以使用制造工艺创建的最小组件(或线))减小的同时，通常增加了功能密度(即，每芯片面积的互连器件的数量)。
这种按比例缩小处理通常通过提高生产效率并降低相关成本来提供益处。这种按比例缩小还增加了IC处理和制造的复杂性。为实现这些进步，需要IC处理和制造的类似发展。当通过多种技术节点按比例缩小诸如金属氧化物半导体场效应晶体管(MOSFET)的半导体器件时，促进晶体管和其他器件之间的布线的导电线和相关介电材料的互连在IC性能改进中发挥着更为重要的作用。尽管制造IC器件的现有方法通常足以满足它们的期望目的，但是它们不是在所有方面都完全令人满意。例如，开发用于互连结构的更耐用金属插塞形成件存在挑战。期望对该区域进行改进。
发明内容
根据本发明的一个方面，提供了一种用于制造半导体集成电路(IC)的方法，该方法包括：在衬底中提供由第一介电层分离的第一导电部件和第二导电部件，其中，第二导电部件的顶面水平地位于第一导电部件的顶面下面；将第一硬掩模(HM)形成为第一导电部件上的顶层；在第一导电部件和第二导电部件上方形成第二介电层，在第二介电层和第一介电层中具有第一开口以暴露第二导电部件；在第一开口中形成第一金属插塞以与第二导电部件接触；在第一金属插塞上形成第二HM作为顶层；在第一导电部件和第一金属插塞之上形成第三介电层，在第三介电层中具有第二开口以暴露第一导电部件与第一金属插塞的子集；以及在第二开口中形成第二金属插塞以连接至第一导电部件与第一金属插塞的子集。
优选地，第一HM的形成包括：使第一导电部件凹进以形成第一沟槽；在衬底上方沉积第一HM层，包括填充在第一沟槽中；以及去除过多的第一HM层。
优选地，第一开口的形成包括：在第二介电层上方形成光刻胶图案；以及通过光刻胶图案来选择性蚀刻第二介电层和第一介电层，其中，选择性蚀刻相对于第一硬掩模具有选择性。
优选地，在选择性蚀刻期间，第一导电部件受到第一HM保护。
优选地，第一金属插塞的形成包括：用第一金属层填充在第一开口中；以及使第一金属层和第二介电层凹进，其中，该凹进被控制，使得所示凹进回蚀第一金属层和第二介电层直至暴露出第一HM。
优选地，第二HM的形成包括：使第一金属插塞凹进以形成第二沟槽；在衬底上方沉积第二HM层，包括填充在第二沟槽中；以及使第二HM层凹进，直至暴露出第一HM。
优选地，在使第二HM层凹进之后，第一HM和第二HM分别覆盖第一导电部件和第一金属插塞。
优选地，第二开口的形成包括：在第三介电层上方形成光刻胶图案；以及通过光刻胶图案来蚀刻第三介电层。
根据本发明的另一方面，提供了一种用于制造半导体集成电路(IC)的方法，该方法包括：提供器件前体；使HK/MG凹进以在HK/MG上形成第一沟槽；在第一沟槽中形成第一硬掩模(HM)，其中，第一HM是HK/MG上的顶层；在HK/MG和导电部件上方形成第二介电层，在第二介电层和第一介电层中具有第一开口以暴露出导电部件；在第一开口中形成第一金属插塞；将第二HM形成作为第一金属插塞上的顶层；在HK/MG和第一金属插塞上方形成第三介电层，在第三介电层中具有第二开口以暴露HK/MG与第一金属插塞的子集；以及在第二开口中形成第二金属插塞以和HK/MG与第一金属插塞的子集连接。其中，提供器件前体包括：位于衬底上方的高k/金属栅极(HK/MG)；沿着HK/MG侧壁的侧壁间隔件，位于衬底上方的导电部件，其中，导电部件的顶面水平地位于HK/MG的顶面下面；和分离HK/MG和导电部件的第一介电层。
优选地，导电部件包括源极和漏极部件。
优选地，第一开口的形成包括：在第二介电层上方形成光刻胶图案；以及通过光刻胶图案来选择性蚀刻第二介电层和第一介电层，其中，选择性蚀刻相对于第一硬掩模具有选择性。
优选地，在选择性蚀刻期间，由第一HM和侧壁间隔件保护HK/MG。
优选地，通过化学机械抛光(CMP)使第一金属层和第二介电层凹进。
优选地，该方法还包括：在沉积第二介电层之前，在衬底上方沉积CMP停止层，衬底上方包括在HK/MG上方；以及CMP在CMP停止层处停止。
优选地，第二HM的形成包括：使第一金属插塞凹进以形成第二沟槽；在衬底上方沉积第二HM层，包括填充在第二沟槽中；以及使第二HM层凹进，直至暴露出第一HM。
优选地，在使第二HM层凹进之后，第一HM覆盖HK/MG并且第二HM覆盖第一金属插塞。
根据本发明的又一方面，提供了一种用于制造半导体集成电路(IC)的方法，该方法包括：在衬底中提供由第一介电层分离的第一导电部件和第二导电部件；形成作为第一导电部件上的顶层的第一硬掩模(HM)；在第一导电部件和第二导电部件上方形成第一图案化的介电层，其中，第一图案化的介电层具有开口以暴露出第二导电部件；在第一开口中形成第一金属插塞以连接第二导电部件；形成作为第一金属插塞上的顶层的第二HM；在第一导电部件和第一金属插塞上方形成第二图案化的介电层，其中，第二图案化的介电层具有第二开口以暴露出第一导电部件与第一金属插塞的子集；以及在第二开口中形成第二金属插塞以连接第一导电部件与第一金属插塞的子集。
优选地，第一HM的形成包括：使第一导电部件凹进以形成第一沟槽；在衬底上方沉积第一HM层，包括填充在第一沟槽中；以及去除过多的第一HM层。
优选地，第一图案化的介电层的形成包括：在第一介电层上方沉积第二介电层；在第二介电层上方形成光刻胶图案；以及通过光刻胶图案来选择性蚀刻第二介电层和第一介电层，其中，选择性蚀刻相对于第一硬掩模具有选择性。
优选地，第二HM的形成包括：使第一金属插塞凹进以形成第二沟槽；在衬底上方沉积第二HM层，包括填充在第二沟槽中；以及去除过多的第二HM层。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的各方面。应该注意，根据工业中的标准实践，各种部件没有被按比例绘制，并且仅被用于说明目的。实际上，为了论述清楚的目的，多种部件的尺寸可以被任意地增加或减小。
图1是用于制造根据本公开的多个方面构造的半导体集成电路(IC)的示例性方法的流程图。
图2至图8是处于根据图1的方法构造的制造阶段的示例性半导体集成电路(IC)的截面图。
具体实施方式
以下公开提供了用于实现本发明的不同特征的多个不同实施例或实例。下面描述组件和布置的特定实例以简化本公开。当然，这些仅是实例，并且不旨在限制。例如，以下说明书中的第一特征在第二特征之上或上形成可以包括第一和第二特征直接接触形成的实施例，并且还可以包括可以在第一和第二特征之间形成附加部件，使得第一和第二特征可以不直接接触的实施例。另外，本公开可以在多个实例中重复参考数字和/或字母。该重复用于简单和清楚的目的，并且其本身不指示所论述的多种实施例和/或结构之间的关系。
而且，为简化说明，在此可以使用诸如“之下”、“下面”、“下部”、“之上”、“上部”等的空间相对术语，以描述一个元件或特征与图中所示的另一个元件或特征的关系。除了图中所示的定向之外，空间相对术语旨在包括正在使用或操作的器件的不同定向。例如，如果图中的器件被翻转，则被描述为在其他元件或特征“下面”或“之下”的元件将被定向为在其他元件或特征“之上”。因此，示例性术语“之下”可以包括之上和之下的定向。装置可以另外被定向(旋转90度或者以其他定向)，并且在此使用的空间相对术语可作同样地解释。
本公开旨在但并不限于FinFET器件。例如，FinFET器件可以是互补金属氧化物半导体(CMOS)器件，其包括P型金属氧化物半导体(PMOS)FinFET器件和N型金属氧化物半导体(NMOS)FinFET器件。以下公开将继续采用FinFET实例，以示出本发明的多种实施例。然而，应当理解，除非特别要求，该应用不应该限于特定类型的器件。
图1是根据本公开的多个方面制造一个或多个半导体器件的方法100的一个实施例的流程图。举例来说，方法100会参考图2中所示的半导体器件前体200和图3A至图3B、图4至图8中所示的半导体器件500进行详细讨论。应当理解，可以在该方法之前、期间和之后提供附加步骤，并且对于该方法的其他实施例，所描述的一些步骤可以被替换或删除。
参考图1和图2，方法100通过接收半导体器件前体200而开始于步骤102。半导体器件前体200包括衬底210。在本实施例中，衬底210包括硅。在可选实施例中，衬底可以包括锗、硅锗、砷化镓或其他合适半导体材料。可替换地并且对于一些实施例而言，衬底210可以包括外延层。例如，衬底210可以具有上覆块状半导体的外延层。而且，衬底210可以产生应变来增强性能。例如，外延层可以包括不同于块状半导体材料的半导体材料，诸如，通过包括选择性外延生长(SEG)的工艺而形成的上覆块状硅的硅锗层或者上覆块状硅锗的硅层。而且，衬底210可以包括绝缘体上半导体(SOI)结构，诸如，掩埋介电层。而且，可替换地，衬底210可以包括掩埋介电层，诸如，埋氧(BOX)层，诸如，通过被称为注氧隔离(SIMOX)技术的方法、晶元接合、SEG或其他合适方法形成的掩埋介电层。实际上，多种实施例可以包括任何多种衬底结构和材料。
半导体器件前体200还可以包括多种隔离部件220。隔离部件220将衬底210中的多种器件区分隔开。隔离部件220包括通过使用不同处理技术形成的不同结构。例如，隔离部件220可以包括浅沟槽隔离(STI)部件。STI的形成可以包括在衬底210中蚀刻沟槽，并且用诸如氧化硅、氮化硅、或氮氧化硅的绝缘材料填充沟槽。填充后的沟槽可以具有多层结构，诸如，采用氮化硅填充沟槽的热氧化物衬垫层。可以执行化学机械抛光(CMP)，以回抛过多绝缘体材料并且平坦化隔离部件220的顶面。
半导体器件前体200还包括一个或多个第一导电部件230。在一个实施例中，第一导电部件230可以包括高k/金属栅极(HK/MG)，即，围绕在鳍状结构之上的三维HK/MG。作为实例，HK/MG可以包括栅极介电层和金属栅极(MG)。栅极介电层可以包括LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba、Sr)TiO3(BST)、Al2O3、Si3N4、氮氧化物(SiON)或其他合适材料。MG可以包括单层或多层，诸如，金属层、衬垫层、浸润层以及粘合层。MG可以包括Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、Al、WN、Cu、W或任何合适材料。另外，在HK/MG的侧壁上形成侧壁间隔件240。侧壁间隔件240可以包括诸如氧化硅的介电材料。可替换地，侧壁间隔件240可以包括氮化硅、碳化硅、氮氧化硅或它们的组合。侧壁间隔件240可以通过本领域中已知的沉积和干蚀刻工艺形成。
在另一个实施例中，第一导电部件230包括电极、电容器、电阻器或电阻器的一部分。在又一个实施例中，第一导电部件230包括互连结构的一部分。例如，第一导电部件230包括接触件、金属通孔或金属线。
半导体器件前体200还包括衬底210中的第二导电部件250。第二导电部件250的顶面与第一导电部件230的顶面可能不在一个水平面上。在一个实施例中，如图2所示，第二导电部件250的顶面水平地位于第一导电部件230的顶面下面的深度d处。在一个实施例中，第二导电部件250包括掺杂区(诸如，源极或漏极)或栅电极。在另一个实施例中，第二导电部件250包括电极、电容器、电阻器或电阻器的一部分或者互连结构的一部分。
半导体器件前体200还包括沉积在衬底210之上(包括位于每个第一导电部件230上方/之间并且位于第二导电部件250上方)的第一介电层260。第一介电层260包括氧化硅、氮化硅、氮氧化物、具有低于热氧化硅的介电常数(k)的介电材料(因此被称为低k介电材料层)或其他合适的介电材料层。第一介电层260包括单层或多层。可以执行CMP以去除过多的第一介电层260，从而暴露第一导电部件230的顶面以及为第一导电部件230和第一介电层260提供基本平坦的顶面。
参考图1和图3A至图3B，一旦接收到半导体器件前体200，则该方法100通过在第一导电部件230上形成第一硬掩模(HM)层310而进行至步骤104。在一个实施例中，如图3A中所示，首先通过选择性蚀刻来使第一导电部件230凹进以形成第一沟槽305。选择性蚀刻可以包括湿蚀刻、干蚀刻或它们的结合。在另一个实施例中，通过包括图案化和蚀刻的合适工艺而形成第一沟槽305。然后，通过诸如化学汽相沉积(CVD)或物理汽相沉积(PVD)的合适技术由第一HM层310填充第一沟槽305。第一HM层310包括氧化钛、氧化钽、氮化硅、氧化硅、碳化硅以及氮碳化硅。在本实施例中，HM层310不同于第一介电层260，以在后续蚀刻期间实现蚀刻选择性，这会在后面进行描述。在一个实施例中，然后执行CMP处理以去除过多的第一HM层310。控制CMP处理以能够去除第一沟槽305之上的第一HM层310，因此，如图3B所示，第一HM层310中位于第一沟槽305内的部分变为第一导电部件230的顶层。
参考图1和图4，方法100进行至步骤106，形成位于衬底210上方的且具有第一开口415的第二介电层410。第二介电层410在很多方面都类似于以上结合图2论述的第一介电层260。在第一开口415的底部，暴露出第二导电部件250的一部分。可以通过光刻图案化和蚀刻工艺形成第一开口415。在本实施例中，如图4中所示，第一开口415成形为与各自的第二导电部件250对准而不与第一导电部件230对准。由于第一开口415的深度基本相同，可以改进蚀刻工艺窗。在一个实施例中，第一开口415通过蚀刻工艺形成，该蚀刻工艺选择性地去除第二介电层410和第一介电层260，但是基本上不蚀刻侧壁间隔件240和第一HM 310。因此，由于保护侧壁间隔件240和第一HM 310，放宽了对第一开口图案化工艺中的覆盖物的约束，并且同时改进了蚀刻工艺窗。
参考图1和图5，方法100进行至步骤108，在第一开口415中形成第一金属插塞420以形成向下延伸至第二导电部件250的完全接触件。在一个实施例中，首先通过诸如PVD和CVD的合适沉积技术在第一开口415中形成第一阻挡层。第一阻挡层可以包括金属并且导电，但是不允许在第一介电材料层260和将被填充在第一开口415中的第一金属层420之间的相互扩散和反应。第一阻挡层可以包括难熔金属和它们的氮化物。在多种实例中，第一阻挡层包括TiN、TaN、Co、WN、TiSiN、TaSiN或它们的组合。第一阻挡层可以包括多个薄膜。
然后，第一金属层420填充在第一开口415中以及第一阻挡层上方。第一金属层420可以包括铜(Cu)、铝(Al)、钨(W)、铜或诸如铜镁(CuMn)、铜铝(CuAl)或铜硅(CuSi)的铜合金或其他合适导电材料。可以通过PVD、CVD、金属有机化学汽相沉积(MOCVD)或镀法来沉积第一金属层420。
在本实施例中，在通过第一金属层420填充第一开口415之后，执行凹进，以回蚀过多的第一金属层420以及过多的第一阻挡层和第二介电层410，并且提供基本平坦的表面。控制开槽，使得该开槽回蚀至暴露出第一HM 310的顶面。作为一个实例，执行CMP，以回抛过多的第一金属层420以及过多的第一阻挡层和第二介电层410。因此，第一金属层420中填充在第一开口415内的部分形成第一金属插塞420。首先通过填充在第一开口415中随后通过回凹(recessing back)，形成具有自对准特性的第一金属插塞420。同时结合侧壁间隔件240，第一HM 310提供了电隔离以防止第一金属插塞420和第一导电部件230之间的电短路。
参考图1和图6，方法100进行至步骤110，在第一金属插塞420上形成第二HM 510。第二HM 510形成为在多个方面类似于以上结合图3A和图3B论述的第一HM 310。第二HM层510包括氧化钛、氧化钽、氮化硅、氧化硅、碳化硅以及氮碳化硅。在一个实施例中，通过选择性蚀刻使第一金属插塞420凹进以形成第二沟槽。然后，由第二HM层510填充第二沟槽，随后执行凹进工艺以去除过多的HM层510。因此，第二HM层510中填充在第二沟槽中内的部分变为第一金属插塞420的顶层。在本实施例中，控制凹进，使得该凹进回蚀第二HM层510至暴露出第一HM 310的顶面。因此，分别作为第一导电部件230和第一金属插塞420上的顶层，第一HM 310和第二HM 510提供隔离层，以防止第一导电部件230和第一金属插塞420与将被形成的第二金属插塞之间的电短路，这会在后文进行描述。
参考图1和图7，方法100进行至步骤112，形成位于衬底210上方(包括位于第一导电部件230和第一金属插塞420上方)且具有第二开口615的第三介电层610。第三介电层610和第二开口615的形成在多个方面类似于以上关于图4论述的第二介电层410和第一开口415。第二开口615形成为暴露第一导电部件230和第一金属插塞420(其与第二导电部件250连接)的子集。为了清楚以更好地描述方法100起见，现在分别通过参考数字230A、420A和250A标记第一导电部件230、第一金属插塞420和第二导电部件250的子集，并且分别通过参考数字230B、420B和250B标记第一导电部件230、第一金属插塞420和第二导电部件250的其他部分。在一个实施例中，通过光刻图案化和蚀刻工艺形成第二开口615。在蚀刻工艺期间，还移除了第一导电部件230A上的第一HM 310和第一金属插塞420A上的第二HM 510。由于第二开口615的深度基本相同，改进蚀刻工艺窗。
参考图1和图8，方法100进行至步骤114，在第二开口615中形成第二金属插塞710以形成向下延伸至第一导电部件230A和第一金属插塞420A的完全接触件。因此，第二金属插塞710的形成在很多方面类似于以上结合图5论述的第一金属插塞420。在一个实施例中，首先在第二开口615中形成第二阻挡层。第二阻挡层可以包括难熔金属和它们的氮化物。在多种实例中，第二阻挡层包括TiN、TaN、Co、WN、TiSiN、TaSiN或它们的结合。第二阻挡层可以包括多个薄膜。
然后，第二金属层710填充在第二开口615中，包括沉积在第二阻挡层之上。第二金属层710可以包括铜(Cu)、铝(Al)、钨(W)、铜或诸如铜镁(CuMn)、铜铝(CuAl)或铜硅(CuSi)的铜合金或其他合适的导电材料。然后，执行凹进，以回蚀过多的第二金属层710以及过多的第二阻挡层，从而形成第二金属插塞710以及与第三介电层610基本共面的表面。
通过首先填充在第二开口615中随后进行回凹，形成具有自对准性质的第二金属插塞710。在形成第二金属插塞710期间，第一HM 310和第二HM 510强化了第一导电部件230B以及第一金属插塞420B与第二金属插塞710之间的保护，这样放宽了工艺约束并且改进了工艺窗。
在本实施例中，通过位于第二导电部件250A顶面之上的两个金属插塞而非一个金属插塞为第二导电部件250A提供了垂直导电连接，其中第二金属插塞710位于第一金属插塞420A顶部。通常，在形成开口期间，开口在其延伸得更深时会变得更窄。因此，为获得开口的目标底部尺寸，较深开口通常在顶部处需要较宽开口。因此，分离两个邻近开口的间隔可能变得更小。较小分离间隔可能使工艺窗更窄，诸如，对错位的容差更小。还可导致减小器件封装密度中更多约束。因此，代替一个更深开口，在该两插塞方案中，每个开口均形成为较深开口的一部分，因此可以实现较小顶部宽度(与较深开口相比)。
在方法100之前、期间和之后，可以提供附加步骤，并且对于方法100的附加实施例，所描述的一些步骤可以被替换、删除或移动。例如，在沉积第二介电层410(在步骤106中)之前，可以在衬底之上沉积蚀刻停止层，以在使第一金属层420凹进时增强蚀刻工艺控制(在步骤108中)。器件500可以进一步经受CMOS或MOS技术处理，以形成多种部件和区域。
基于上文，本公开提供了一种用于制造半导体器件的方法。该方法采用形成硬掩模作为导电部件的顶层，以在形成金属插塞期间防止相应的导电部件与另一个导电部件连接。该方法还采用形成具有自对准性质的金属插塞。该方法展示出具有放宽的工艺约束的互连件的集成、增强的电短路保护以及改进的工艺窗。
本公开提供了制造半导体IC的多个不同实施例，其提供了优于现有方法的一个或多个改进。在一个实施例中，一种用于制造半导体集成电路(IC)的方法包括在衬底中提供第一导电部件和第二导电部件。第一和第二导电部件通过第一介电层分离。第二导电部件的顶面水平位于第一导电部件的顶面下面。该方法还包括：在第一导电部件上形成第一硬掩模(HM)作为顶层；在第一和第二导电部件之上沉积第二介电层；在第一和第二介电层中形成第一开口以暴露第二导电部件；在第一开口中形成第一金属插塞以与第二导电部件接触；在第一金属插塞上形成第二HM作为顶层；在第一导电部件和第一金属插塞之上沉积第三介电层；在第三介电层中形成第二开口以暴露第一导电部件和第一金属插塞的子集；以及在第二开口中形成第二金属插塞以连接至第一导电部件和第一金属插塞的子集。
在另一个实施例中，一种用于制造半导体IC的方法包括提供器件前体。器件前体包括位于衬底中的高-k/金属栅极(HK/MG)、沿着HK/WG侧壁的侧壁间隔件、位于衬底中的导电部件以及分离HK/MG和第二导电部件的第一介电层。导电部件的顶面水平位于HK/MG的顶面下面。该方法还包括：使HK/MG凹进以在HK/MG上形成第一沟槽；在第一沟槽中形成第一硬掩模(HM)，因此第一HM是HK/MG上的顶层。该方法还包括：在HK/MG和导电部件之上沉积第二介电层；在第二和第一介电层中形成第一开口以暴露导电部件；由第一金属层填充第一开口以与导电部件接触；使第一金属层和第二介电层凹进直到暴露第一HM。因此，在第一开口中形成第一金属插塞。该方法还包括：在第一金属插塞上形成第二HM作为顶层；在HK/MG和第一金属插塞之上沉积第三介电层；在第三介电层中形成第二开口以暴露HK/MG和第一金属插塞的子集；以及在第二开口中形成第二金属插塞以与HK/MG和第一金属插塞的子集连接。
在又一个实施例中，一种用于制造半导体IC的方法包括：在衬底中提供通过第一介电层分离的第一导电部件和第二导电部件。该方法还包括：在第一导电部件上形成第一硬掩模(HM)作为顶层；在第一和第二导电部件之上形成第一图案化的介电层。因此。第一图案化的介电层具有开口以暴露第二导电部件。该方法还包括：在第一开口中形成第一金属插塞以连接第二导电部件；在第一金属插塞上形成第二HM作为顶层；在第一导电部件和第一金属插塞之上形成第二图案化的介电层。因此，第二图案化的介电层具有第二开口以暴露第一金属插塞和第一导电部件的子集；以及在第二开口中形成第二金属插塞以连接第一金属插塞的子集和第一导电部件。
以上概述了多个实施例的特征，使得本领域技术人员可以更好地理解本公开的多个方面。本领域技术人员将想到，它们可以容易地使用本公开作为用于设计或修改用于实现与在此介绍的实施例相同的目的和/或实现与其相同优点的其他处理和结构的基础。本领域技术人员还将认识到，这样的等效结构不脱离本公开的精神和范围，并且可以在不脱离本公开的精神和范围的情况下，在此作出多种改变、替换和更改。

Claims (10)

1.一种用于制造半导体集成电路(IC)的方法，所述方法包括：
在衬底中提供由第一介电层分离的第一导电部件和第二导电部件，其中，所述第二导电部件的顶面水平地位于所述第一导电部件的顶面下面；
将第一硬掩模(HM)形成为所述第一导电部件上的顶层；
在所述第一导电部件和所述第二导电部件上方形成第二介电层，在所述第二介电层和所述第一介电层中具有第一开口以暴露所述第二导电部件；
在所述第一开口中形成第一金属插塞以与所述第二导电部件接触；
在所述第一金属插塞上形成第二HM作为顶层；
在所述第一导电部件和所述第一金属插塞之上形成第三介电层，在所述第三介电层中具有第二开口以暴露所述第一导电部件与所述第一金属插塞的子集；以及
在所述第二开口中形成第二金属插塞以连接至所述第一导电部件与所述第一金属插塞的子集。
2.根据权利要求1所述的方法，其中，所述第一HM的形成包括：
使所述第一导电部件凹进以形成第一沟槽；
在所述衬底上方沉积第一HM层，包括填充在所述第一沟槽中；以及
去除过多的所述第一HM层。
3.根据权利要求1所述的方法，其中，所述第一开口的形成包括：
在所述第二介电层上方形成光刻胶图案；以及
通过所述光刻胶图案来选择性蚀刻所述第二介电层和所述第一介电层，其中，所述选择性蚀刻相对于所述第一硬掩模具有选择性。
4.根据权利要求3所述的方法，其中，在所述选择性蚀刻期间，所述第一导电部件受到所述第一HM保护。
5.根据权利要求1所述的方法，其中，所述第一金属插塞的形成包括：
用第一金属层填充在所述第一开口中；以及
使所述第一金属层和所述第二介电层凹进，其中，所述凹进被控制，使得所示凹进回蚀所述第一金属层和所述第二介电层直至暴露出所述第一HM。
6.根据权利要求1所述的方法，其中，所述第二HM的形成包括：
使所述第一金属插塞凹进以形成第二沟槽；
在所述衬底上方沉积第二HM层，包括填充在所述第二沟槽中；以及
使所述第二HM层凹进，直至暴露出所述第一HM。
7.根据权利要求6所述的方法，其中，在使所述第二HM层凹进之后，所述第一HM和所述第二HM分别覆盖所述第一导电部件和所述第一金属插塞。
8.根据权利要求1所述的方法，其中，所述第二开口的形成包括：
在所述第三介电层上方形成光刻胶图案；以及
通过所述光刻胶图案来蚀刻所述第三介电层。
9.一种用于制造半导体集成电路(IC)的方法，所述方法包括：
提供器件前体，包括：
位于衬底上方的高k/金属栅极(HK/MG)；
沿着HK/MG侧壁的侧壁间隔件，
位于所述衬底上方的导电部件，其中，所述导电部件的顶面水平地位于所述HK/MG的顶面下面；和
分离所述HK/MG和所述导电部件的第一介电层；
使所述HK/MG凹进以在所述HK/MG上形成第一沟槽；
在所述第一沟槽中形成第一硬掩模(HM)，其中，所述第一HM是所述HK/MG上的顶层；
在所述HK/MG和所述导电部件上方形成第二介电层，在所述第二介电层和所述第一介电层中具有第一开口以暴露出所述导电部件；
在所述第一开口中形成第一金属插塞；
将第二HM形成作为所述第一金属插塞上的顶层；
在所述HK/MG和所述第一金属插塞上方形成第三介电层，在所述第三介电层中具有第二开口以暴露所述HK/MG与所述第一金属插塞的子集；以及
在所述第二开口中形成第二金属插塞以和所述HK/MG与所述第一金属插塞的所述子集连接。
10.一种用于制造半导体集成电路(IC)的方法，所述方法包括：
在衬底中提供由第一介电层分离的第一导电部件和第二导电部件；
形成作为所述第一导电部件上的顶层的第一硬掩模(HM)；
在所述第一导电部件和所述第二导电部件上方形成第一图案化的介电层，其中，所述第一图案化的介电层具有开口以暴露出所述第二导电部件；
在所述第一开口中形成第一金属插塞以连接所述第二导电部件；
形成作为所述第一金属插塞上的顶层的第二HM；
在所述第一导电部件和所述第一金属插塞上方形成第二图案化的介电层，其中，所述第二图案化的介电层具有第二开口以暴露出所述第一导电部件与所述第一金属插塞的子集；以及
在所述第二开口中形成第二金属插塞以连接所述第一导电部件与所述第一金属插塞的子集。
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